^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLOGIC LINUX SOFTWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Qlogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (www.qlogic.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _QLA1280_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _QLA1280_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Data bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BIT_0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BIT_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BIT_2 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BIT_3 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BIT_4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BIT_5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BIT_6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BIT_7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BIT_8 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BIT_9 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BIT_10 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BIT_11 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BIT_12 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BIT_13 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BIT_14 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BIT_15 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BIT_16 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BIT_17 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BIT_18 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BIT_19 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BIT_20 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BIT_21 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BIT_22 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BIT_23 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BIT_24 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BIT_25 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BIT_26 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BIT_27 0x8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BIT_28 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BIT_29 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BIT_30 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BIT_31 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if MEMORY_MAPPED_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RD_REG_WORD(addr) readw_relaxed(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RD_REG_WORD_dmasync(addr) readw(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WRT_REG_WORD(addr, data) writew(data, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #else /* MEMORY_MAPPED_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RD_REG_WORD(addr) inw((unsigned long)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* MEMORY_MAPPED_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Host adapter default definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAX_BUSES 2 /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MAX_B_BITS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX_TARGETS 16 /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_T_BITS 4 /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX_LUNS 8 /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAX_L_BITS 3 /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Watchdog time quantum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Command retry count (0-65535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COMMAND_RETRY_COUNT 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Maximum outstanding commands in ISP queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX_OUTSTANDING_COMMANDS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define COMPLETED_HANDLE ((unsigned char *) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (MAX_OUTSTANDING_COMMANDS + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* ISP request and response entry counts (37-65535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * SCSI Request Block structure (sp) that is placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * on cmd->SCp location of every I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct srb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct list_head list; /* (8/16) LU queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct scsi_cmnd *cmd; /* (4/8) SCSI command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* NOTE: the sp->cmd will be NULL when this completion is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * called, so you should know the scsi_cmnd when using this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct completion *wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dma_addr_t saved_dma_handle; /* for unmap of single transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint8_t flags; /* (1) Status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uint8_t dir; /* direction of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * SRB flag definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SRB_TIMEOUT (1 << 0) /* Command timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SRB_SENT (1 << 1) /* Command sent to ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SRB_ABORTED (1 << 3) /* Command aborted command already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * ISP I/O Register Set structure definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint16_t id_l; /* ID low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint16_t id_h; /* ID high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) uint16_t cfg_0; /* Configuration 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ISP_CFG0_1020 BIT_0 /* ISP1020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ISP_CFG0_1040A BIT_3 /* ISP1040A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ISP_CFG0_1040B BIT_4 /* ISP1040B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ISP_CFG0_1040C BIT_5 /* ISP1040C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint16_t cfg_1; /* Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ISP_CFG1_SXP BIT_0 /* SXP register select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint16_t ictrl; /* Interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ISP_RESET BIT_0 /* ISP soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint16_t istatus; /* Interface status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RISC_INT BIT_2 /* RISC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCI_INT BIT_1 /* PCI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint16_t semaphore; /* Semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint16_t nvram; /* NVRAM register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NV_DESELECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define NV_CLOCK BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define NV_SELECT BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define NV_DATA_OUT BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define NV_DATA_IN BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) uint16_t flash_data; /* Flash BIOS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uint16_t flash_address; /* Flash BIOS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint16_t unused_1[0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* cdma_* and ddma_* are 1040 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uint16_t cdma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) uint16_t cdma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint16_t cdma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) uint16_t cdma_fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint16_t cdma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uint16_t cdma_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint16_t cdma_address_count_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint16_t cdma_address_count_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint16_t cdma_address_count_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint16_t cdma_address_count_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uint16_t unused_2[0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint16_t ddma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) uint16_t ddma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uint16_t ddma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uint16_t ddma_fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uint16_t ddma_xfer_count_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint16_t ddma_xfer_count_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uint16_t ddma_addr_count_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) uint16_t ddma_addr_count_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint16_t ddma_addr_count_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) uint16_t ddma_addr_count_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uint16_t unused_3[0x0e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint16_t mailbox0; /* Mailbox 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint16_t mailbox1; /* Mailbox 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint16_t mailbox2; /* Mailbox 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint16_t mailbox3; /* Mailbox 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint16_t mailbox4; /* Mailbox 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) uint16_t mailbox5; /* Mailbox 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint16_t mailbox6; /* Mailbox 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint16_t mailbox7; /* Mailbox 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uint16_t host_cmd; /* Host command and control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HOST_INT BIT_7 /* host interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BIOS_ENABLE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) uint16_t gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) uint16_t gpio_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uint16_t unused_6[0x11]; /* d0-f0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uint16_t scsiControlPins; /* f2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MAILBOX_REGISTER_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * ISP product identification definitions in mailboxes after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PROD_ID_1 0x4953
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PROD_ID_2 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PROD_ID_2a 0x5020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PROD_ID_3 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PROD_ID_4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * ISP host command and control register command definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HC_RESET_RISC 0x1000 /* Reset RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * ISP mailbox Self-Test status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MBS_BUSY 4 /* Busy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * ISP mailbox command complete status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MBS_CMD_CMP 0x4000 /* Command Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MBS_INV_CMD 0x4001 /* Invalid Command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MBS_CMD_ERR 0x4005 /* Command Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * ISP mailbox asynchronous event status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * ISP mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MBC_NOP 0 /* No Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MBC_LOAD_RAM 1 /* Load RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MBC_DUMP_RAM 3 /* Dump RAM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MBC_WRITE_RAM_WORD 4 /* Write ram word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MBC_READ_RAM_WORD 5 /* Read ram word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MBC_LOAD_RAM_A64_ROM 9 /* Load RAM 64bit ROM version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MBC_DUMP_RAM_A64_ROM 0x0a /* Dump RAM 64bit ROM version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MBC_BUS_RESET 0x18 /* SCSI bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * ISP Get/Set Target Parameters mailbox command control flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TP_PPR BIT_5 /* PPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TP_SYNC BIT_12 /* Synchronous data transfers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TP_WIDE BIT_13 /* Wide data transfers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TP_PARITY BIT_14 /* Parity checking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * NVRAM Command values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define NV_START_BIT BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define NV_WRITE_OP (BIT_26 | BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define NV_READ_OP (BIT_26 | BIT_25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define NV_DELAY_COUNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * QLogic ISP1280/ISP12160 NVRAM structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct nvram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint8_t id0; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uint8_t id1; /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint8_t id2; /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uint8_t id3; /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint8_t version; /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint8_t bios_configuration_mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) uint8_t bios_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) uint8_t selectable_scsi_boot_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) uint8_t cd_rom_boot_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint8_t disable_loading_risc_code:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint8_t enable_64bit_addressing:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } cntr_flags_1; /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) uint8_t boot_lun_number:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) uint8_t scsi_bus_number:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) uint8_t unused_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } cntr_flags_2l; /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) uint8_t boot_target_number:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint8_t unused_12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint8_t unused_13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) uint8_t unused_14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) uint8_t unused_15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } cntr_flags_2h; /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) uint16_t unused_8; /* 8, 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uint16_t unused_10; /* 10, 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uint16_t unused_12; /* 12, 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint16_t unused_14; /* 14, 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint8_t reserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint8_t burst_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uint8_t reserved_1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) uint8_t fifo_threshold:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } isp_config; /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * 0 = Disable, 1 = high only, 3 = Auto term
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uint8_t scsi_bus_1_control:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) uint8_t scsi_bus_0_control:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uint8_t unused_0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) uint8_t unused_1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uint8_t unused_2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uint8_t auto_term_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } termination; /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint16_t isp_parameter; /* 18, 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint16_t w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint16_t enable_fast_posting:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint16_t report_lvd_bus_transition:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint16_t unused_2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) uint16_t unused_3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uint16_t disable_iosbs_with_bus_reset_status:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint16_t disable_synchronous_backoff:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint16_t unused_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint16_t synchronous_backoff_reporting:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) uint16_t disable_reselection_fairness:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint16_t unused_9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint16_t unused_10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint16_t unused_11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint16_t unused_12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint16_t unused_13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint16_t unused_14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uint16_t unused_15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) } firmware_feature; /* 20, 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) uint16_t unused_22; /* 22, 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint8_t initiator_id:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) uint8_t scsi_reset_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint8_t scsi_bus_size:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uint8_t scsi_bus_type:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } config_1; /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uint8_t bus_reset_delay; /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uint8_t retry_count; /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uint8_t retry_delay; /* 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uint8_t async_data_setup_time:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uint8_t req_ack_active_negation:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uint8_t data_line_active_negation:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uint8_t unused_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } config_2; /* 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t unused_29; /* 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint16_t selection_timeout; /* 30, 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uint16_t max_queue_depth; /* 32, 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) uint16_t unused_34; /* 34, 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) uint16_t unused_36; /* 36, 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) uint16_t unused_38; /* 38, 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint8_t renegotiate_on_error:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint8_t stop_queue_on_check:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint8_t auto_request_sense:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint8_t tag_queuing:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) uint8_t enable_sync:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint8_t enable_wide:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t parity_checking:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uint8_t disconnect_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } parameter; /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint8_t execution_throttle; /* 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint8_t sync_period; /* 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) union { /* 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uint8_t flags_43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint8_t sync_offset:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint8_t device_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t lun_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t unused_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } flags1x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint8_t sync_offset:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint8_t device_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uint8_t unused_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint8_t unused_7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } flags1x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) union { /* PPR flags for the 1x160 controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint8_t unused_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint8_t ppr_options:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint8_t ppr_bus_width:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint8_t unused_8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint8_t enable_ppr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } flags; /* 44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } ppr_1x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t unused_45; /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } target[MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } bus[MAX_BUSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint16_t unused_248; /* 248, 249 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) union { /* 254 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint8_t unused_254;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint8_t system_id_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) } sysid_1x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint8_t chksum; /* 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * ISP queue - command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cmd_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define COMMAND_TYPE 1 /* Command entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __le32 handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uint8_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __le16 cdb_len; /* SCSI command length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __le32 dseg_0_address; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) __le32 dseg_1_address; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __le32 dseg_2_address; /* Data segment 2 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __le32 dseg_2_length; /* Data segment 2 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __le32 dseg_3_address; /* Data segment 3 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __le32 dseg_3_length; /* Data segment 3 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * ISP queue - continuation entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct cont_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define CONTINUE_TYPE 2 /* Continuation entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __le32 reserved; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __le32 dseg_0_address; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __le32 dseg_1_address; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 dseg_2_address; /* Data segment 2 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __le32 dseg_2_length; /* Data segment 2 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __le32 dseg_3_address; /* Data segment 3 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __le32 dseg_3_length; /* Data segment 3 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) __le32 dseg_4_address; /* Data segment 4 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) __le32 dseg_4_length; /* Data segment 4 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __le32 dseg_5_address; /* Data segment 5 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) __le32 dseg_5_length; /* Data segment 5 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) __le32 dseg_6_address; /* Data segment 6 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __le32 dseg_6_length; /* Data segment 6 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * ISP queue - status entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define STATUS_TYPE 3 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define RF_CONT BIT_0 /* Continuation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define RF_FULL BIT_1 /* Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define RF_BAD_HEADER BIT_2 /* Bad header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __le32 handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __le16 scsi_status; /* SCSI status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __le16 state_flags; /* State flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SF_GOT_SENSE BIT_13 /* Got Sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SF_GOT_STATUS BIT_12 /* Got Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SF_SENT_CDB BIT_10 /* Send CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SF_GOT_TARGET BIT_9 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SF_GOT_BUS BIT_8 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __le16 status_flags; /* Status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le16 time; /* Time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __le16 req_sense_length;/* Request sense data length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __le32 residual_length; /* Residual transfer length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __le16 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint8_t req_sense_data[32]; /* Request sense data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * ISP queue - marker entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mrk_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MARKER_TYPE 4 /* Marker entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uint8_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uint8_t modifier; /* Modifier (7-0). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MK_SYNC_ID 1 /* Synchronize ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) uint8_t reserved_1[53];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * ISP queue - extended command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Unused by the driver!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct ecmd_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint8_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __le16 cdb_len; /* SCSI command length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uint8_t scsi_cdb[88]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * ISP queue - 64-Bit addressing, command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define COMMAND_A64_TYPE 9 /* Command A64 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __le32 handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uint8_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __le16 cdb_len; /* SCSI command length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __le32 reserved_1[2]; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __le32 dseg_0_address[2]; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __le32 dseg_1_address[2]; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } cmd_a64_entry_t, request_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * ISP queue - 64-Bit addressing, continuation entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct cont_a64_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __le32 dseg_0_address[2]; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __le32 dseg_1_address[2]; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __le32 dseg_2_address[2]; /* Data segment 2 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) __le32 dseg_2_length; /* Data segment 2 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __le32 dseg_3_address[2]; /* Data segment 3 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) __le32 dseg_3_length; /* Data segment 3 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __le32 dseg_4_address[2]; /* Data segment 4 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __le32 dseg_4_length; /* Data segment 4 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * ISP queue - enable LUN entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct elun_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) uint8_t entry_status; /* Entry Status not used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __le16 lun; /* Bit 15 is bus number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __le16 reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uint8_t reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) uint8_t command_count; /* Number of ATIOs allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uint8_t immed_notify_count; /* Number of Immediate Notify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* entries allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint8_t group_6_length; /* SCSI CDB length for group 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* commands (2-26). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint8_t group_7_length; /* SCSI CDB length for group 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* commands (2-26). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) __le16 reserved_6[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * ISP queue - modify LUN entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * Unused by the driver!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct modify_lun_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uint8_t operators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) uint8_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) uint8_t reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint8_t command_count; /* Number of ATIOs allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uint8_t immed_notify_count; /* Number of Immediate Notify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* entries allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __le16 reserved_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __le16 reserved_7[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * ISP queue - immediate notify entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct notify_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint8_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* entries allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __le16 seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __le16 reserved_5[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uint8_t sense_data[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * ISP queue - notify acknowledge entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct nack_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint8_t event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __le16 seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __le16 reserved_4[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * ISP queue - Accept Target I/O (ATIO) entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct atio_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) uint8_t cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) uint8_t cdb[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint8_t sense_data[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * ISP queue - Continue Target I/O (CTIO) entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct ctio_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __le32 dseg_0_address; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __le32 dseg_1_address; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) __le32 dseg_2_address; /* Data segment 2 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __le32 dseg_2_length; /* Data segment 2 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) __le32 dseg_3_address; /* Data segment 3 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __le32 dseg_3_length; /* Data segment 3 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * ISP queue - CTIO returned entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct ctio_ret_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define CTIO_RET_TYPE 7 /* CTIO return entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __le32 dseg_0_address; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __le32 dseg_1_address; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __le16 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint8_t sense_data[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * ISP queue - CTIO A64 entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct ctio_a64_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) __le32 reserved_4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) __le32 dseg_0_address[2];/* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __le32 dseg_0_length; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __le32 dseg_1_address[2];/* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __le32 dseg_1_length; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * ISP queue - CTIO returned entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct ctio_a64_ret_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uint8_t lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) __le32 option_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint8_t tag_value; /* Received queue tag message value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) uint8_t tag_type; /* Received queue tag message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) __le16 reserved_4[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint8_t sense_data[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * ISP request and response queue entry sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define RESPONSE_ENTRY_SIZE (sizeof(struct response))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define REQUEST_ENTRY_SIZE (sizeof(request_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * ISP status entry - completion status definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define CS_COMPLETE 0x0 /* No errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define CS_DMA 0x2 /* A DMA direction error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define CS_TRANSPORT 0x3 /* Transport error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define CS_RESET 0x4 /* SCSI bus reset occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define CS_ABORTED 0x5 /* System aborted command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define CS_TIMEOUT 0x6 /* Timeout error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define CS_FREE 0x14 /* Unexpected bus free. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define CS_ARS_FAILED 0x1e /* ARS failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define CS_UNKNOWN 0x81 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define CS_RETRY 0x82 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * ISP target entries - Option flags bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define OF_DATA_IN BIT_6 /* Data in to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* (data from target to initiator) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define OF_DATA_OUT BIT_7 /* Data out from initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* (data from initiator to target) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define OF_NO_DATA (BIT_7 | BIT_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define OF_SSTS BIT_31 /* Send SCSI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * BUS parameters/settings structure - UNUSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct bus_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uint8_t id; /* Host adapter SCSI id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) uint8_t bus_reset_delay; /* SCSI bus reset delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) uint8_t failed_reset_count; /* number of time reset failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) uint8_t unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) uint16_t device_enables; /* Device enable bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) uint16_t lun_disables; /* LUN disable bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uint16_t qtag_enables; /* Tag queue enables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uint16_t hiwat; /* High water mark per device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) uint8_t reset_marker:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) uint8_t disable_scsi_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct qla_driver_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) uint32_t no_sync:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint32_t no_wide:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint32_t no_ppr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) uint32_t no_nvram:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) uint16_t sync_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) uint16_t wide_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint16_t ppr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Linux Host Adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct scsi_qla_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Linux adapter configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct Scsi_Host *host; /* pointer to host data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct scsi_qla_host *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned char __iomem *mmpbase; /* memory mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned long host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) uint8_t devnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) uint8_t revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) uint8_t ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) unsigned long actthreads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unsigned long isr_count; /* Interrupt count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) unsigned long spurious_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Outstandings ISP commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* BUS configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct bus_param bus_settings[MAX_BUSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Received ISP mailbox data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dma_addr_t request_dma; /* Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) request_t *request_ring; /* Base virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) request_t *request_ring_ptr; /* Current address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) uint16_t req_ring_index; /* Current index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) uint16_t req_q_cnt; /* Number of available entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dma_addr_t response_dma; /* Physical address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct response *response_ring; /* Base virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct response *response_ring_ptr; /* Current address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) uint16_t rsp_ring_index; /* Current index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct list_head done_q; /* Done queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct completion *mailbox_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct timer_list mailbox_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) uint32_t online:1; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) uint32_t reset_marker:1; /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) uint32_t disable_host_adapter:1; /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) uint32_t reset_active:1; /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) uint32_t abort_isp_active:1; /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) uint32_t disable_risc_code_load:1; /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct nvram nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int nvram_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Firmware Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) unsigned short fwstart; /* start address for F/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned char fwver1; /* F/W version first char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned char fwver2; /* F/W version second char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned char fwver3; /* F/W version third char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #endif /* _QLA1280_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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