^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pmcraid.h -- PMC Sierra MaxRAID controller driver header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written By: Anil Ravindranath<anil_ravindranath@pmc-sierra.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * PMC-Sierra Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2008, 2009 PMC Sierra Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _PMCRAID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _PMCRAID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <net/netlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <net/genetlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Driver name : string representing the driver name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Device file : /dev file to be used for management interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Driver version: version string in major_version.minor_version.patch format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Driver date : date information in "Mon dd yyyy" format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMCRAID_DRIVER_NAME "PMC MaxRAID"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PMCRAID_DEVFILE "pmcsas"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PMCRAID_DRIVER_VERSION "1.0.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PMCRAID_FW_VERSION_1 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Maximum number of adapters supported by current version of the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PMCRAID_MAX_ADAPTERS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Bit definitions as per firmware, bit position [0][1][2].....[31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PMC_BIT8(n) (1 << (7-n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PMC_BIT16(n) (1 << (15-n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PMC_BIT32(n) (1 << (31-n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* PMC PCI vendor ID and device ID values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_VENDOR_ID_PMC 0x11F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_PMC_MAXRAID 0x5220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * MAX_CMD : maximum commands that can be outstanding with IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MAX_IO_CMD : command blocks available for IO commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * MAX_HCAM_CMD : command blocks avaibale for HCAMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * MAX_INTERNAL_CMD : command blocks avaible for internal commands like reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PMCRAID_MAX_CMD 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PMCRAID_MAX_IO_CMD 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMCRAID_MAX_HCAM_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PMCRAID_MAX_INTERNAL_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MAX_IOADLS : max number of scatter-gather lists supported by IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * IOADLS_INTERNAL : number of ioadls included as part of IOARCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * IOADLS_EXTERNAL : number of ioadls allocated external to IOARCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PMCRAID_IOADLS_INTERNAL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PMCRAID_IOADLS_EXTERNAL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PMCRAID_MAX_IOADLS PMCRAID_IOADLS_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* HRRQ_ENTRY_SIZE : size of hrrq buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * IOARCB_ALIGNMENT : alignment required for IOARCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * IOADL_ALIGNMENT : alignment requirement for IOADLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * MSIX_VECTORS : number of MSIX vectors supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HRRQ_ENTRY_SIZE sizeof(__le32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PMCRAID_IOARCB_ALIGNMENT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PMCRAID_IOADL_ALIGNMENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PMCRAID_IOASA_ALIGNMENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PMCRAID_NUM_MSIX_VECTORS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* various other limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PMCRAID_VENDOR_ID_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMCRAID_PRODUCT_ID_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMCRAID_SERIAL_NUM_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PMCRAID_LUN_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PMCRAID_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PMCRAID_DEVICE_ID_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMCRAID_SENSE_DATA_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PMCRAID_ADD_CMD_PARAM_LEN 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PMCRAID_MAX_BUS_TO_SCAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMCRAID_MAX_NUM_TARGETS_PER_BUS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMCRAID_MAX_NUM_LUNS_PER_TARGET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* IOA bus/target/lun number of IOA resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PMCRAID_IOA_BUS_ID 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PMCRAID_IOA_TARGET_ID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PMCRAID_IOA_LUN_ID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMCRAID_VSET_BUS_ID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMCRAID_VSET_LUN_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PMCRAID_PHYS_BUS_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PMCRAID_VIRTUAL_ENCL_BUS_ID 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PMCRAID_MAX_VSET_TARGETS 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMCRAID_MAX_VSET_LUNS_PER_TARGET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMCRAID_IOA_MAX_SECTORS 32767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMCRAID_VSET_MAX_SECTORS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMCRAID_MAX_CMD_PER_LUN 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Number of configuration table entries (resources), includes 1 FP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 1 Enclosure device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMCRAID_MAX_RESOURCES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Adapter Commands used by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PMCRAID_QUERY_RESOURCE_STATE 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMCRAID_RESET_DEVICE 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* options to select reset target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ENABLE_RESET_MODIFIER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESET_DEVICE_LUN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RESET_DEVICE_TARGET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RESET_DEVICE_BUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMCRAID_IDENTIFY_HRRQ 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PMCRAID_QUERY_IOA_CONFIG 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PMCRAID_QUERY_CMD_STATUS 0xCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PMCRAID_ABORT_CMD 0xC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* CANCEL ALL command, provides option for setting SYNC_COMPLETE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * on the target resources for which commands got cancelled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PMCRAID_CANCEL_ALL_REQUESTS 0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMCRAID_SYNC_COMPLETE_AFTER_CANCEL PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* HCAM command and types of HCAM supported by IOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PMCRAID_HOST_CONTROLLED_ASYNC 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PMCRAID_HCAM_CODE_CONFIG_CHANGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PMCRAID_HCAM_CODE_LOG_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* IOA shutdown command and various shutdown types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PMCRAID_IOA_SHUTDOWN 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PMCRAID_SHUTDOWN_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PMCRAID_SHUTDOWN_PREPARE_FOR_NORMAL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PMCRAID_SHUTDOWN_NONE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PMCRAID_SHUTDOWN_ABBREV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* SET SUPPORTED DEVICES command and the option to select all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * devices to be supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PMCRAID_SET_SUPPORTED_DEVICES 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ALL_DEVICES_SUPPORTED PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* This option is used with SCSI WRITE_BUFFER command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PMCRAID_WR_BUF_DOWNLOAD_AND_SAVE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* IOASC Codes used by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PMCRAID_IOASC_SENSE_MASK 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PMCRAID_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PMCRAID_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PMCRAID_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PMCRAID_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PMCRAID_IOASC_GOOD_COMPLETION 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PMCRAID_IOASC_GC_IOARCB_NOTFOUND 0x005A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PMCRAID_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PMCRAID_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PMCRAID_IOASC_NR_SYNC_REQUIRED 0x023F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PMCRAID_IOASC_ME_READ_ERROR_NO_REALLOC 0x03110C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PMCRAID_IOASC_HW_CANNOT_COMMUNICATE 0x04050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PMCRAID_IOASC_HW_DEVICE_TIMEOUT 0x04080100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PMCRAID_IOASC_HW_DEVICE_BUS_STATUS_ERROR 0x04448500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PMCRAID_IOASC_HW_IOA_RESET_REQUIRED 0x04448600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PMCRAID_IOASC_IR_INVALID_RESOURCE_HANDLE 0x05250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PMCRAID_IOASC_AC_TERMINATED_BY_HOST 0x0B5A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PMCRAID_IOASC_UA_BUS_WAS_RESET 0x06290000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PMCRAID_IOASC_TIME_STAMP_OUT_OF_SYNC 0x06908B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PMCRAID_IOASC_UA_BUS_WAS_RESET_BY_OTHER 0x06298000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Driver defined IOASCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PMCRAID_IOASC_IOA_WAS_RESET 0x10000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PMCRAID_IOASC_PCI_ACCESS_ERROR 0x10000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Various timeout values (in milliseconds) used. If any of these are chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * specific, move them to pmcraid_chip_details structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PMCRAID_PCI_DEASSERT_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PMCRAID_BIST_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PMCRAID_AENWAIT_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PMCRAID_TRANSOP_TIMEOUT 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PMCRAID_RESET_TIMEOUT (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PMCRAID_CHECK_FOR_RESET_TIMEOUT ((HZ / 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PMCRAID_VSET_IO_TIMEOUT (60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PMCRAID_INTERNAL_TIMEOUT (60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PMCRAID_SHUTDOWN_TIMEOUT (150 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PMCRAID_RESET_BUS_TIMEOUT (60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PMCRAID_RESET_HOST_TIMEOUT (150 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PMCRAID_REQUEST_SENSE_TIMEOUT (30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PMCRAID_SET_SUP_DEV_TIMEOUT (2 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* structure to represent a scatter-gather element (IOADL descriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pmcraid_ioadl_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } __attribute__((packed, aligned(PMCRAID_IOADL_ALIGNMENT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* pmcraid_ioadl_desc.flags values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IOADL_FLAGS_CHAINED PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IOADL_FLAGS_LAST_DESC PMC_BIT8(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IOADL_FLAGS_READ_LAST PMC_BIT8(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IOADL_FLAGS_WRITE_LAST PMC_BIT8(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* additional IOARCB data which can be CDB or additional request parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * or list of IOADLs. Firmware supports max of 512 bytes for IOARCB, hence then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * number of IOADLs are limted to 27. In case they are more than 27, they will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * be used in chained form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct pmcraid_ioarcb_add_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_INTERNAL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __u8 add_cmd_params[PMCRAID_ADD_CMD_PARAM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * IOA Request Control Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pmcraid_ioarcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __le64 ioarcb_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le32 resource_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __le32 response_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __le64 ioadl_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __le32 ioadl_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __le32 data_transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __le64 ioasa_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __le16 ioasa_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __le16 cmd_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __le16 add_cmd_param_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __le16 add_cmd_param_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __le32 reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __u8 request_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __u8 request_flags0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __u8 request_flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __u8 hrrq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __u8 cdb[PMCRAID_MAX_CDB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct pmcraid_ioarcb_add_data add_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } __attribute__((packed, aligned(PMCRAID_IOARCB_ALIGNMENT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* well known resource handle values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PMCRAID_IOA_RES_HANDLE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PMCRAID_INVALID_RES_HANDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* pmcraid_ioarcb.request_type values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define REQ_TYPE_SCSI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define REQ_TYPE_IOACMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define REQ_TYPE_HCAM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* pmcraid_ioarcb.flags0 values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TRANSFER_DIR_WRITE PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define INHIBIT_UL_CHECK PMC_BIT8(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SYNC_OVERRIDE PMC_BIT8(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SYNC_COMPLETE PMC_BIT8(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define NO_LINK_DESCS PMC_BIT8(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* pmcraid_ioarcb.flags1 values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DELAY_AFTER_RESET PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TASK_TAG_SIMPLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TASK_TAG_ORDERED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TASK_TAG_QUEUE_HEAD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* toggle bit offset in response handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HRRQ_TOGGLE_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HRRQ_RESPONSE_BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* IOA Status Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pmcraid_ioasa_vset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __le32 failing_lba_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __le32 failing_lba_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pmcraid_ioasa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __le32 ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __le16 returned_status_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le16 available_status_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 residual_data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __le32 ilid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __le32 fd_ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le32 fd_res_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __le32 fd_res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* resource specific sense information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pmcraid_ioasa_vset vset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* IOA autosense data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le16 auto_sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le16 error_data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __u8 sense_data[PMCRAID_SENSE_DATA_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PMCRAID_DRIVER_ILID 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Config Table Entry per Resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pmcraid_config_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __u8 resource_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __u8 bus_protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __le16 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __u8 common_flags0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __u8 common_flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __u8 unique_flags0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __u8 unique_flags1; /*also used as vset target_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) __le32 resource_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __le32 resource_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __u8 device_id[PMCRAID_DEVICE_ID_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __u8 lun[PMCRAID_LUN_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* extended configuration table sizes are also of 32 bytes in size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct pmcraid_config_table_entry_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pmcraid_config_table_entry cfgte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* resource types (config_table_entry.resource_type values) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RES_TYPE_AF_DASD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define RES_TYPE_GSCSI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define RES_TYPE_VSET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define RES_TYPE_IOA_FP 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define RES_IS_IOA(res) ((res).resource_type == RES_TYPE_IOA_FP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RES_IS_GSCSI(res) ((res).resource_type == RES_TYPE_GSCSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RES_IS_VSET(res) ((res).resource_type == RES_TYPE_VSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define RES_IS_AFDASD(res) ((res).resource_type == RES_TYPE_AF_DASD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* bus_protocol values used by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define RES_TYPE_VENCLOSURE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* config_table_entry.common_flags0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MULTIPATH_RESOURCE PMC_BIT32(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* unique_flags1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMPORT_MODE_MANUAL PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* well known resource handle values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define RES_HANDLE_IOA 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define RES_HANDLE_NONE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* well known resource address values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define RES_ADDRESS_IOAFP 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RES_ADDRESS_INVALID 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* BUS/TARGET/LUN values from resource_addrr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define RES_BUS(res_addr) (le32_to_cpu(res_addr) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RES_TARGET(res_addr) ((le32_to_cpu(res_addr) >> 16) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define RES_LUN(res_addr) 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* configuration table structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct pmcraid_config_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __le16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __u8 table_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __u8 reserved2[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct pmcraid_config_table_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) entries[PMCRAID_MAX_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct pmcraid_config_table_entry_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) entries_ext[PMCRAID_MAX_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* config_table.flags value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MICROCODE_UPDATE_REQUIRED PMC_BIT32(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * HCAM format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PMCRAID_HOSTRCB_LDNSIZE 4056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Error log notification format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct pmcraid_hostrcb_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __le32 fd_ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __le32 fd_ra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __le32 fd_rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __le32 prc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) __u8 data[PMCRAID_HOSTRCB_LDNSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } __attribute__ ((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct pmcraid_hcam_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __u8 op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __u8 notification_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __u8 notification_lost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __u8 overlay_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __le32 ilid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __le32 timestamp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) __le32 timestamp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PMCRAID_AEN_GROUP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct pmcraid_hcam_ccn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct pmcraid_hcam_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct pmcraid_config_table_entry cfg_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct pmcraid_config_table_entry cfg_entry_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PMCRAID_CCN_EXT_SIZE 3944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct pmcraid_hcam_ccn_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct pmcraid_hcam_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct pmcraid_config_table_entry_ext cfg_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct pmcraid_config_table_entry_ext cfg_entry_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __u8 reserved[PMCRAID_CCN_EXT_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct pmcraid_hcam_ldn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct pmcraid_hcam_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct pmcraid_hostrcb_error error_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* pmcraid_hcam.op_code values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HOSTRCB_TYPE_CCN 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HOSTRCB_TYPE_LDN 0xE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* pmcraid_hcam.notification_type values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define NOTIFICATION_TYPE_ENTRY_CHANGED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define NOTIFICATION_TYPE_ENTRY_NEW 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define NOTIFICATION_TYPE_ENTRY_DELETED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define NOTIFICATION_TYPE_STATE_CHANGE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define NOTIFICATION_TYPE_ENTRY_STATECHANGED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define NOTIFICATION_TYPE_ERROR_LOG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define NOTIFICATION_TYPE_INFORMATION_LOG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define HOSTRCB_NOTIFICATIONS_LOST PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* pmcraid_hcam.flags values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define HOSTRCB_INTERNAL_OP_ERROR PMC_BIT8(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HOSTRCB_ERROR_RESPONSE_SENT PMC_BIT8(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* pmcraid_hcam.overlay_id values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define HOSTRCB_OVERLAY_ID_08 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define HOSTRCB_OVERLAY_ID_09 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define HOSTRCB_OVERLAY_ID_11 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define HOSTRCB_OVERLAY_ID_12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define HOSTRCB_OVERLAY_ID_13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HOSTRCB_OVERLAY_ID_14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define HOSTRCB_OVERLAY_ID_16 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define HOSTRCB_OVERLAY_ID_17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HOSTRCB_OVERLAY_ID_20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HOSTRCB_OVERLAY_ID_FF 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Implementation specific card details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct pmcraid_chip_details {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* hardware register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long ioastatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned long ioarrin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long global_intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long ioa_host_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long ioa_host_msix_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long ioa_host_intr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long ioa_host_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned long ioa_host_mask_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long host_ioa_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long host_ioa_intr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* timeout used during transitional to operational state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned long transop_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* IOA to HOST doorbells (interrupts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define INTRS_TRANSITION_TO_OPERATIONAL PMC_BIT32(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define INTRS_IOARCB_TRANSFER_FAILED PMC_BIT32(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define INTRS_IOA_UNIT_CHECK PMC_BIT32(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define INTRS_NO_HRRQ_FOR_CMD_RESPONSE PMC_BIT32(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define INTRS_CRITICAL_OP_IN_PROGRESS PMC_BIT32(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define INTRS_IO_DEBUG_ACK PMC_BIT32(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define INTRS_IOARRIN_LOST PMC_BIT32(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define INTRS_SYSTEM_BUS_MMIO_ERROR PMC_BIT32(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define INTRS_IOA_PROCESSOR_ERROR PMC_BIT32(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define INTRS_HRRQ_VALID PMC_BIT32(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define INTRS_OPERATIONAL_STATUS PMC_BIT32(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define INTRS_ALLOW_MSIX_VECTOR0 PMC_BIT32(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Host to IOA Doorbells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DOORBELL_RUNTIME_RESET PMC_BIT32(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DOORBELL_IOA_RESET_ALERT PMC_BIT32(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DOORBELL_IOA_DEBUG_ALERT PMC_BIT32(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DOORBELL_ENABLE_DESTRUCTIVE_DIAGS PMC_BIT32(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DOORBELL_IOA_START_BIST PMC_BIT32(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DOORBELL_INTR_MODE_MSIX PMC_BIT32(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DOORBELL_INTR_MSIX_CLR PMC_BIT32(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DOORBELL_RESET_IOA PMC_BIT32(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Global interrupt mask register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define GLOBAL_INTERRUPT_MASK 0x5ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PMCRAID_ERROR_INTERRUPTS (INTRS_IOARCB_TRANSFER_FAILED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) INTRS_IOA_UNIT_CHECK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) INTRS_NO_HRRQ_FOR_CMD_RESPONSE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) INTRS_IOARRIN_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) INTRS_SYSTEM_BUS_MMIO_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) INTRS_IOA_PROCESSOR_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PMCRAID_PCI_INTERRUPTS (PMCRAID_ERROR_INTERRUPTS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) INTRS_HRRQ_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) INTRS_TRANSITION_TO_OPERATIONAL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) INTRS_ALLOW_MSIX_VECTOR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* control_block, associated with each of the commands contains IOARCB, IOADLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * memory for IOASA. Additional 3 * 16 bytes are allocated in order to support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * additional request parameters (of max size 48) any command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct pmcraid_control_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct pmcraid_ioarcb ioarcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_EXTERNAL + 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct pmcraid_ioasa ioasa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } __attribute__ ((packed, aligned(PMCRAID_IOARCB_ALIGNMENT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* pmcraid_sglist - Scatter-gather list allocated for passthrough ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct pmcraid_sglist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 num_dma_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct scatterlist *scatterlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* page D0 inquiry data of focal point resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct pmcraid_inquiry_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) __u8 ph_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __u8 page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) __u8 add_page_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __be16 fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __u8 reserved3[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PMCRAID_TIMESTAMP_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define PMCRAID_REQ_TM_STR_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PMCRAID_SCSI_SET_TIMESTAMP 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PMCRAID_SCSI_SERVICE_ACTION 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct pmcraid_timestamp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) __u8 reserved1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) __u8 timestamp[PMCRAID_REQ_TM_STR_LEN]; /* current time value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __u8 reserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* pmcraid_cmd - LLD representation of SCSI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct pmcraid_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Ptr and bus address of DMA.able control block for this command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct pmcraid_control_block *ioa_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dma_addr_t ioa_cb_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* pointer to mid layer structure of SCSI commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct list_head free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct completion wait_for_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct timer_list timer; /* needed for internal commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 timeout; /* current timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 index; /* index into the command list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u8 completion_req; /* for handling internal commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u8 release; /* for handling completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void (*cmd_done) (struct pmcraid_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct pmcraid_instance *drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct pmcraid_sglist *sglist; /* used for passthrough IOCTLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* scratch used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* during reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct pmcraid_resource_entry *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int hrrq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* used during IO command error handling. Sense buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * for REQUEST SENSE command if firmware is not sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * auto sense data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 *sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dma_addr_t sense_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Interrupt registers of IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct pmcraid_interrupts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void __iomem *ioa_host_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) void __iomem *ioa_host_msix_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) void __iomem *ioa_host_interrupt_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) void __iomem *ioa_host_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) void __iomem *ioa_host_interrupt_mask_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void __iomem *global_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) void __iomem *host_ioa_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void __iomem *host_ioa_interrupt_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* ISR parameters LLD allocates (one for each MSI-X if enabled) vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct pmcraid_isr_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct pmcraid_instance *drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 hrrq_id; /* hrrq entry index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* AEN message header sent as part of event data to applications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct pmcraid_aen_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 hostno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u8 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Controller state event message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct pmcraid_state_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct pmcraid_aen_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 ioa_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PMC_DEVICE_EVENT_RESET_START 0x11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PMC_DEVICE_EVENT_RESET_SUCCESS 0x11000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PMC_DEVICE_EVENT_RESET_FAILED 0x11000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define PMC_DEVICE_EVENT_SHUTDOWN_START 0x11000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define PMC_DEVICE_EVENT_SHUTDOWN_SUCCESS 0x11000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PMC_DEVICE_EVENT_SHUTDOWN_FAILED 0x11000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct pmcraid_hostrcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct pmcraid_instance *drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct pmcraid_aen_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct pmcraid_hcam_hdr *hcam; /* pointer to hcam buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct pmcraid_cmd *cmd; /* pointer to command block used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dma_addr_t baddr; /* system address of hcam buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) atomic_t ignore; /* process HCAM response ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PMCRAID_AEN_HDR_SIZE sizeof(struct pmcraid_aen_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Per adapter structure maintained by LLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct pmcraid_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Array of allowed-to-be-exposed resources, initialized from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Configutation Table, later updated with CCNs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct pmcraid_resource_entry *res_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct list_head free_res_q; /* res_entries lists for easy lookup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct list_head used_res_q; /* List of to be exposed resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spinlock_t resource_lock; /* spinlock to protect resource list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void __iomem *mapped_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) void __iomem *ioa_status; /* Iomapped IOA status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void __iomem *mailbox; /* Iomapped mailbox register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void __iomem *ioarrin; /* IOmapped IOARR IN register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct pmcraid_interrupts int_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct pmcraid_chip_details *chip_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* HostRCBs needed for HCAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct pmcraid_hostrcb ldn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct pmcraid_hostrcb ccn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct pmcraid_state_msg scn; /* controller state change msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Bus address of start of HRRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dma_addr_t hrrq_start_bus_addr[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Pointer to 1st entry of HRRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __le32 *hrrq_start[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Pointer to last entry of HRRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __le32 *hrrq_end[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Pointer to current pointer of hrrq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) __le32 *hrrq_curr[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Lock for HRRQ access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) spinlock_t hrrq_lock[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct pmcraid_inquiry_data *inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dma_addr_t inq_data_baddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct pmcraid_timestamp_data *timestamp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dma_addr_t timestamp_data_baddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* size of configuration table entry, varies based on the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 config_table_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Expected toggle bit at host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 host_toggle_bit[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Wait Q for threads to wait for Reset IOA completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) wait_queue_head_t reset_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct pmcraid_cmd *reset_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* structures for supporting SIGIO based AEN. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct fasync_struct *aen_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct mutex aen_queue_lock; /* lock for aen subscribers list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct cdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct Scsi_Host *host; /* mid layer interface structure handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct pci_dev *pdev; /* PCI device structure handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* No of Reset IOA retries . IOA marked dead if threshold exceeds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u8 ioa_reset_attempts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define PMCRAID_RESET_ATTEMPTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u8 current_log_level; /* default level for logging IOASC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 num_hrrq; /* Number of interrupt vectors allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 interrupt_mode; /* current interrupt mode legacy or msix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_t dev; /* Major-Minor numbers for Char device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Used as ISR handler argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct pmcraid_isr_param hrrq_vector[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Message id as filled in last fired IOARCB, used to identify HRRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) atomic_t last_message_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* configuration table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct pmcraid_config_table *cfg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dma_addr_t cfg_table_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* structures related to command blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct kmem_cache *cmd_cachep; /* cache for cmd blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct dma_pool *control_pool; /* pool for control blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) char cmd_pool_name[64]; /* name of cmd cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) char ctl_pool_name[64]; /* name of control cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct pmcraid_cmd *cmd_list[PMCRAID_MAX_CMD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct list_head free_cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct list_head pending_cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) spinlock_t free_pool_lock; /* free pool lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) spinlock_t pending_pool_lock; /* pending pool lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Tasklet to handle deferred processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct tasklet_struct isr_tasklet[PMCRAID_NUM_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Work-queue (Shared) for deferred reset processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct work_struct worker_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* No of IO commands pending with FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) atomic_t outstanding_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* should add/delete resources to mid-layer now ?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) atomic_t expose_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 ioa_state:4; /* For IOA Reset sequence FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define IOA_STATE_OPERATIONAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define IOA_STATE_UNKNOWN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define IOA_STATE_DEAD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define IOA_STATE_IN_SOFT_RESET 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define IOA_STATE_IN_HARD_RESET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define IOA_STATE_IN_RESET_ALERT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define IOA_STATE_IN_BRINGDOWN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define IOA_STATE_IN_BRINGUP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 ioa_reset_in_progress:1; /* true if IOA reset is in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 ioa_hard_reset:1; /* TRUE if Hard Reset is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 ioa_unit_check:1; /* Indicates Unit Check condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 ioa_bringdown:1; /* whether IOA needs to be brought down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 force_ioa_reset:1; /* force adapter reset ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 reinit_cfg_table:1; /* reinit config table due to lost CCN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u32 ioa_shutdown_type:2;/* shutdown type used during reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define SHUTDOWN_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define SHUTDOWN_NORMAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define SHUTDOWN_ABBREV 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 timestamp_error:1; /* indicate set timestamp for out of sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* LLD maintained resource entry structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct pmcraid_resource_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct list_head queue; /* link to "to be exposed" resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct pmcraid_config_table_entry cfg_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct pmcraid_config_table_entry_ext cfg_entry_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct scsi_device *scsi_dev; /* Link scsi_device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) atomic_t read_failures; /* count of failed READ commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) atomic_t write_failures; /* count of failed WRITE commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* To indicate add/delete/modify during CCN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 change_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define RES_CHANGE_ADD 0x1 /* add this to mid-layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define RES_CHANGE_DEL 0x2 /* remove this from mid-layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 reset_progress; /* Device is resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * When IOA asks for sync (i.e. IOASC = Not Ready, Sync Required), this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * flag will be set, mid layer will be asked to retry. In the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * attempt, this flag will be checked in queuecommand() to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * SYNC_COMPLETE flag in IOARCB (flag_0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 sync_reqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* target indicates the mapped target_id assigned to this resource if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * this is VSET resource. For non-VSET resources this will be un-used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * or zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Data structures used in IOASC error code logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct pmcraid_ioasc_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 ioasc_code; /* IOASC code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 log_level; /* default log level assignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) char *error_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Initial log_level assignments for various IOASCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define IOASC_LOG_LEVEL_NONE 0x0 /* no logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define IOASC_LOG_LEVEL_MUST 0x1 /* must log: all high-severity errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define IOASC_LOG_LEVEL_HARD 0x2 /* optional – low severity errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Error information maintained by LLD. LLD initializes the pmcraid_error_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * statically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct pmcraid_ioasc_error pmcraid_ioasc_error_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x01180600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "Recovered Error, soft media error, sector reassignment suggested"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x015D0000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "Recovered Error, failure prediction threshold exceeded"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x015D9200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "Recovered Error, soft Cache Card Battery error threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x015D9200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "Recovered Error, soft Cache Card Battery error threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x02048000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "Not Ready, IOA Reset Required"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x02408500, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "Not Ready, IOA microcode download required"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x03110B00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "Medium Error, data unreadable, reassignment suggested"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x03110C00, IOASC_LOG_LEVEL_MUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "Medium Error, data unreadable do not reassign"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x03310000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "Medium Error, media corrupted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x04050000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "Hardware Error, IOA can't communicate with device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x04080000, IOASC_LOG_LEVEL_MUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) "Hardware Error, device bus error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x04088000, IOASC_LOG_LEVEL_MUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "Hardware Error, device bus is not functioning"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x04118000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "Hardware Error, IOA reserved area data check"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x04118100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "Hardware Error, IOA reserved area invalid data pattern"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x04118200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "Hardware Error, IOA reserved area LRC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x04320000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "Hardware Error, reassignment space exhausted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x04330000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "Hardware Error, data transfer underlength error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x04330000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "Hardware Error, data transfer overlength error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x04418000, IOASC_LOG_LEVEL_MUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "Hardware Error, PCI bus error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x04440000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "Hardware Error, device error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x04448200, IOASC_LOG_LEVEL_MUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "Hardware Error, IOA error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x04448300, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "Hardware Error, undefined device response"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x04448400, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "Hardware Error, IOA microcode error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x04448600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "Hardware Error, IOA reset required"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x04449200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "Hardware Error, hard Cache Fearuee Card Battery error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x0444A000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "Hardware Error, failed device altered"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x0444A200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "Hardware Error, data check after reassignment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x0444A300, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "Hardware Error, LRC error after reassignment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x044A0000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "Hardware Error, device bus error (msg/cmd phase)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x04670400, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "Hardware Error, new device can't be used"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x04678000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "Hardware Error, invalid multiadapter configuration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x04678100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "Hardware Error, incorrect connection between enclosures"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x04678200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "Hardware Error, connections exceed IOA design limits"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x04678300, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "Hardware Error, incorrect multipath connection"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x04679000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "Hardware Error, command to LUN failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x064C8000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "Unit Attention, cache exists for missing/failed device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x06670100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "Unit Attention, incompatible exposed mode device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x06670600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "Unit Attention, attachment of logical unit failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x06678000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "Unit Attention, cables exceed connective design limit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x06678300, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "Unit Attention, incomplete multipath connection between" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "IOA and enclosure"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x06678400, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "Unit Attention, incomplete multipath connection between" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "device and enclosure"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x06678500, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "Unit Attention, incomplete multipath connection between" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "IOA and remote IOA"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x06678600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "Unit Attention, missing remote IOA"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x06679100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "Unit Attention, enclosure doesn't support required multipath" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "function"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x06698200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "Unit Attention, corrupt array parity detected on device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x066B0200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "Unit Attention, array exposed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x066B8200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "Unit Attention, exposed array is still protected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x066B9200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "Unit Attention, Multipath redundancy level got worse"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x07270000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "Data Protect, device is read/write protected by IOA"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x07278000, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "Data Protect, IOA doesn't support device attribute"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x07278100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "Data Protect, NVRAM mirroring prohibited"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x07278400, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "Data Protect, array is short 2 or more devices"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x07278600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "Data Protect, exposed array is short a required device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x07278700, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "Data Protect, array members not at required addresses"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x07278800, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) "Data Protect, exposed mode device resource address conflict"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x07278900, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "Data Protect, incorrect resource address of exposed mode device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x07278A00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "Data Protect, Array is missing a device and parity is out of sync"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x07278B00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "Data Protect, maximum number of arrays already exist"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x07278C00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "Data Protect, cannot locate cache data for device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x07278D00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "Data Protect, cache data exits for a changed device"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x07279100, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) "Data Protect, detection of a device requiring format"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x07279200, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "Data Protect, IOA exceeds maximum number of devices"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x07279600, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) "Data Protect, missing array, volume set is not functional"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x07279700, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "Data Protect, single device for a volume set"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x07279800, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "Data Protect, missing multiple devices for a volume set"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x07279900, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "Data Protect, maximum number of volument sets already exists"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x07279A00, IOASC_LOG_LEVEL_HARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "Data Protect, other volume set problem"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* macros to help in debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define pmcraid_err(...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) printk(KERN_ERR "MaxRAID: "__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define pmcraid_info(...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (pmcraid_debug_log) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) printk(KERN_INFO "MaxRAID: "__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* check if given command is a SCSI READ or SCSI WRITE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define SCSI_READ_CMD 0x1 /* any of SCSI READ commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define SCSI_WRITE_CMD 0x2 /* any of SCSI WRITE commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define SCSI_CMD_TYPE(opcode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ({ u8 op = opcode; u8 __type = 0;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (op == READ_6 || op == READ_10 || op == READ_12 || op == READ_16)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __type = SCSI_READ_CMD;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) else if (op == WRITE_6 || op == WRITE_10 || op == WRITE_12 || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) op == WRITE_16)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) __type = SCSI_WRITE_CMD;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __type;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define IS_SCSI_READ_WRITE(opcode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ({ u8 __type = SCSI_CMD_TYPE(opcode); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) (__type == SCSI_READ_CMD || __type == SCSI_WRITE_CMD) ? 1 : 0;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * pmcraid_ioctl_header - definition of header structure that precedes all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * buffers given as ioctl arguments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * .signature : always ASCII string, "PMCRAID"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * .reserved : not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * .buffer_length : length of the buffer following the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct pmcraid_ioctl_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u8 signature[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) u32 buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define PMCRAID_IOCTL_SIGNATURE "PMCRAID"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * pmcraid_passthrough_ioctl_buffer - structure given as argument to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * passthrough(or firmware handled) IOCTL commands. Note that ioarcb requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * 32-byte alignment so, it is necessary to pack this structure to avoid any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * holes between ioctl_header and passthrough buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * .ioactl_header : ioctl header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * .ioarcb : filled-up ioarcb buffer, driver always reads this buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * .ioasa : buffer for ioasa, driver fills this with IOASA from firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * .request_buffer: The I/O buffer (flat), driver reads/writes to this based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * the transfer directions passed in ioarcb.flags0. Contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * of this buffer are valid only when ioarcb.data_transfer_len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * is not zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct pmcraid_passthrough_ioctl_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct pmcraid_ioctl_header ioctl_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct pmcraid_ioarcb ioarcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct pmcraid_ioasa ioasa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u8 request_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * keys to differentiate between driver handled IOCTLs and passthrough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * IOCTLs passed to IOA. driver determines the ioctl type using macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * _IOC_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define PMCRAID_DRIVER_IOCTL 'D'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define PMCRAID_PASSTHROUGH_IOCTL 'F'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define DRV_IOCTL(n, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_DRIVER_IOCTL, (n), (size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define FMW_IOCTL(n, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_PASSTHROUGH_IOCTL, (n), (size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * _ARGSIZE: macro that gives size of the argument type passed to an IOCTL cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * This is to facilitate applications avoiding un-necessary memory allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * For example, most of driver handled ioctls do not require ioarcb, ioasa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define _ARGSIZE(arg) (sizeof(struct pmcraid_ioctl_header) + sizeof(arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Driver handled IOCTL command definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define PMCRAID_IOCTL_RESET_ADAPTER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) DRV_IOCTL(5, sizeof(struct pmcraid_ioctl_header))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* passthrough/firmware handled commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define PMCRAID_IOCTL_PASSTHROUGH_COMMAND \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) FMW_IOCTL(1, sizeof(struct pmcraid_passthrough_ioctl_buffer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define PMCRAID_IOCTL_DOWNLOAD_MICROCODE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) FMW_IOCTL(2, sizeof(struct pmcraid_passthrough_ioctl_buffer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #endif /* _PMCRAID_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags