^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 USI Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef _PMC8001_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define _PMC8001_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <scsi/libsas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* for Request Opcode of IOMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OPC_INB_ECHO 1 /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OPC_INB_PHYSTART 4 /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OPC_INB_PHYSTOP 5 /* 0x005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 0x8 RESV IN SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OPC_INB_RSVD 8 /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* 0xC, 0xD, 0xE removed in SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OPC_INB_SSP_ABORT 15 /* 0x00F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* 0x13 SMP_RESPONSE is removed in SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OPC_INB_SMP_ABORT 20 /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 0x16 RESV IN SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OPC_INB_RSVD1 22 /* 0x016 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OPC_INB_SATA_ABORT 24 /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 0x1A RESV IN SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OPC_INB_RSVD2 26 /* 0x01A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OPC_INB_GPIO 34 /* 0x022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* 0x25 RESV IN SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OPC_INB_RSVD3 37 /* 0x025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 0x2D RESV IN SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OPC_INB_RSVD4 45 /* 0x02D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OPC_INB_REG_DEV 50 /* 0x032 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* for Response Opcode of IOMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPC_OUB_ECHO 1 /* 0x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OPC_OUB_RSVD 4 /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OPC_OUB_SSP_COMP 5 /* 0x005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OPC_OUB_SMP_COMP 6 /* 0x006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OPC_OUB_RSVD1 10 /* 0x00A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OPC_OUB_SATA_COMP 13 /* 0x00D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OPC_OUB_RSVD2 16 /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OPC_OUB_RSVD3 19 /* 0x013 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OPC_OUB_RSVD4 31 /* 0x01F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OPC_OUB_RSVD5 41 /* 0x029 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OPC_OUB_HW_EVENT 1792 /* 0x700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OPC_OUB_DEV_REGIST 2098 /* 0x832 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* spcv specific commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* for phy start*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SSC_DISABLE_15 (0x01 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SSC_DISABLE_30 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SSC_DISABLE_60 (0x04 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SAS_ASE (0x01 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SPINHOLD_DISABLE (0x00 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SPINHOLD_ENABLE (0x01 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LINKMODE_SAS (0x01 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LINKMODE_DSATA (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LINKMODE_AUTO (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LINKRATE_15 (0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LINKRATE_30 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LINKRATE_60 (0x04 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LINKRATE_120 (0x08 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*phy_stop*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PHY_STOP_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PHY_STOP_ERR_DEVICE_ATTACHED 0x1046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* phy_profile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PHY_DWORD_LENGTH 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Thermal related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define THERMAL_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define THERMAL_LOG_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define THERMAL_PAGE_CODE_7H 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define THERMAL_PAGE_CODE_8H 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LTEMPHIL 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RTEMPHIL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Encryption info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SCRATCH_PAD3_ENC_DISABLED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCRATCH_PAD3_ENC_READY 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCRATCH_PAD3_SMF_ENABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SCRATCH_PAD3_SM_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCRATCH_PAD3_ERR_CODE 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SEC_MODE_SMF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SEC_MODE_SMA 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SEC_MODE_SMB 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CIPHER_MODE_ECB 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CIPHER_MODE_XTS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* SAS protocol timer configuration page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define STP_MCT_TMO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SSP_MCT_TMO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SAS_MAX_OPEN_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SMP_MAX_CONN_TIMER 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define STP_FRM_TIMER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define STP_IDLE_TIME 5 /* 5 us; controller default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SAS_MFD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SAS_OPNRJT_RTRY_INTVL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SAS_DOPNRJT_RTRY_TMO 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SAS_COPNRJT_RTRY_TMO 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SPCV_DOORBELL_CLEAR_TIMEOUT (30 * 1000 * 1000) /* 30 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SPC_DOORBELL_CLEAR_TIMEOUT (15 * 1000 * 1000) /* 15 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) is DOPNRJT_RTRY_TMO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SAS_DOPNRJT_RTRY_THR 23438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SAS_COPNRJT_RTRY_THR 23438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SAS_MAX_AIP 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IT_NEXUS_TIMEOUT 0x7D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Port recovery timeout, 10000 ms for PM8006 controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CHIP_8006_PORT_RECOVERY_TIMEOUT 0x640000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef __LITTLE_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct sas_identify_frame_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 frame_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 dev_type:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 _un0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 _un1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 _un20:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 smp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 stp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 ssp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 _un247:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 initiator_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 _un30:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 smp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 stp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 ssp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 _un347:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 target_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Byte 4 - 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 _un4_11[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Byte 12 - 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 _un21_27[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct sas_identify_frame_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 _un0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 dev_type:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 frame_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 _un1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 _un247:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 ssp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 stp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 smp_iport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 _un20:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 initiator_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 _un347:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 ssp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 stp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u8 smp_tport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 _un30:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 target_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Byte 4 - 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 _un4_11[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Byte 12 - 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 _un21_27[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #error "Bitfield order not defined!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mpi_msg_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __le32 header; /* Bits [11:0] - Message operation code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Bits [15:12] - Message Category */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Bits [21:16] - Outboundqueue ID for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) operation completion message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Bits [23:22] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Bits [28:24] - Buffer Count, indicates how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) many buffer are allocated for the massage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Bits [30:29] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Bits [31] - Message Valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * brief the data structure of PHY Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * use to describe enable the phy (128 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct phy_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __le32 ase_sh_lm_slr_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct sas_identify_frame_local sas_identify; /* 28 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __le32 spasti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 reserved[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * brief the data structure of PHY Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * use to disable the phy (128 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct phy_stop_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __le32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 reserved[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* set device bits fis - device to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct set_dev_bits_fis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 fis_type; /* 0xA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 n_i_pmport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* b7 : n Bit. Notification bit. If set device needs attention. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* b6 : i Bit. Interrupt Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* b5-b4: reserved2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* b3-b0: PM Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* PIO setup FIS - device to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct pio_setup_fis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 fis_type; /* 0x5f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 i_d_pmPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* b7 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* b6 : i bit. Interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* b5 : d bit. data transfer direction. set to 1 for device to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* b4 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* b3-b0: PM Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 lbal_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 lbam_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 lbah_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 sector_count_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 _r_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 e_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 _r_c[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u8 transfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * brief the data structure of SATA Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * use to describe the sata task response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct sata_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 sata_resp[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * brief the data structure of SAS HW Event Notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * use to alert the host about the hardware event(64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* updated outbound struct for spcv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct hw_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __le32 lr_status_evt_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __le32 evt_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __le32 phyid_npip_portstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct sas_identify_frame sas_identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct dev_to_host_fis sata_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * brief the data structure for thermal event notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct thermal_hw_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __le32 thermal_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __le32 rht_lht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * brief the data structure of REGISTER DEVICE Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * use to describe MPI REGISTER DEVICE Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct reg_dev_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __le32 phyid_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __le32 dtype_dlr_mcn_ir_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __le32 firstburstsize_ITNexustimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __le32 upper_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * brief the data structure of DEREGISTER DEVICE Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * use to request spc to remove all internal resources associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * with the device id (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct dereg_dev_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 reserved[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * brief the data structure of DEVICE_REGISTRATION Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * use to notify the completion of the device registration (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct dev_reg_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * brief the data structure of Local PHY Control Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * use to issue PHY CONTROL to local phy (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct local_phy_ctl_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __le32 phyop_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 reserved1[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * brief the data structure of Local Phy Control Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * use to describe MPI Local Phy Control Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct local_phy_ctl_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __le32 phyop_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define OP_BITS 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define ID_BITS 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * brief the data structure of PORT Control Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * use to control port properties (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct port_ctl_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __le32 portop_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __le32 param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __le32 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 reserved1[27];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * brief the data structure of HW Event Ack Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * use to acknowledge receive HW event (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct hw_event_ack_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) __le32 phyid_sea_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __le32 param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __le32 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 reserved1[27];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * brief the data structure of PHY_START Response Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * indicates the completion of PHY_START command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct phy_start_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) __le32 phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * brief the data structure of PHY_STOP Response Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * indicates the completion of PHY_STOP command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct phy_stop_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __le32 phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * brief the data structure of SSP Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * use to indicate a SSP Completion (n bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct ssp_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __le32 ssptag_rescv_rescpad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct ssp_response_iu ssp_resp_iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) __le32 residual_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SSP_RESCV_BIT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * brief the data structure of SATA EVNET response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * use to indicate a SATA Completion (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct sata_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __le32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __le32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __le32 event_param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __le32 event_param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __le32 sata_addr_h32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __le32 sata_addr_l32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __le32 e_udt1_udt0_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __le32 e_udt5_udt4_udt3_udt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le32 a_udt1_udt0_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __le32 a_udt5_udt4_udt3_udt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __le32 hwdevid_diferr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __le32 err_framelen_byteoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __le32 err_dataframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * brief the data structure of SSP EVNET esponse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * use to indicate a SSP Completion (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct ssp_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) __le32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) __le32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __le32 ssp_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) __le32 event_param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __le32 event_param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) __le32 sas_addr_h32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __le32 sas_addr_l32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __le32 e_udt1_udt0_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) __le32 e_udt5_udt4_udt3_udt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) __le32 a_udt1_udt0_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __le32 a_udt5_udt4_udt3_udt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) __le32 hwdevid_diferr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __le32 err_framelen_byteoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __le32 err_dataframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * brief the data structure of General Event Notification Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * use to describe MPI General Event Notification Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct general_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __le32 inb_IOMB_payload[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define GENERAL_EVENT_PAYLOAD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define OPCODE_BITS 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * brief the data structure of SMP Request Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * use to describe MPI SMP REQUEST Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct smp_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __le32 len_ip_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Bits [0] - Indirect response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Bits [1] - Indirect Payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Bits [15:2] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Bits [23:16] - direct payload Len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Bits [31:24] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 smp_req16[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 smp_req[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) __le64 long_req_addr;/* sg dma address, LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __le32 long_req_size;/* LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __le64 long_resp_addr;/* sg dma address, LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le32 long_resp_size;/* LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 _r_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } long_smp_req;/* sequencer extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __le32 rsvd[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * brief the data structure of SMP Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * use to describe MPI SMP Completion Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct smp_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 _r_a[252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *brief the data structure of SSP SMP SATA Abort Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct task_abort_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) __le32 tag_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __le32 abort_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 reserved[27];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* These flags used for SSP SMP & SATA Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define ABORT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define ABORT_SINGLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define ABORT_ALL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * brief the data structure of SSP SATA SMP Abort Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct task_abort_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __le32 scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * brief the data structure of SAS Diagnostic Start/End Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct sas_diag_start_end_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) __le32 operation_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 reserved[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * brief the data structure of SAS Diagnostic Execute Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct sas_diag_execute_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __le32 cmdtype_cmddesc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __le32 pat1_pat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __le32 codepat_errmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __le32 pmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __le32 pERF1CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define SAS_DIAG_PARAM_BYTES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * brief the data structure of Set Device State Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * use to describe MPI Set Device State Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct set_dev_state_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __le32 nds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 reserved[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * brief the data structure of SATA Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * use to describe MPI SATA IO Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * Note: This structure is common for normal / encryption I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct sata_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __le32 ncqtag_atap_dir_m_dad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct host_to_dev_fis sata_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 reserved2; /* dword 11. rsvd for normal I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* EPLE Descl for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u32 addr_low; /* dword 12. rsvd for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 addr_high; /* dword 13. reserved for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __le32 len; /* dword 14: length for normal I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* EPLE Desch for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) __le32 esgl; /* dword 15. rsvd for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* The below fields are reserved for normal I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) __le32 key_index_mode; /* dword 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __le32 sector_cnt_enss;/* dword 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __le32 keytagl; /* dword 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __le32 keytagh; /* dword 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) __le32 twk_val0; /* dword 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __le32 twk_val1; /* dword 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __le32 twk_val2; /* dword 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __le32 twk_val3; /* dword 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) __le32 enc_addr_low; /* dword 28. Encryption SGL address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) __le32 enc_len; /* dword 30. Encryption length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) __le32 enc_esgl; /* dword 31. Encryption esgl bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * brief the data structure of SSP INI TM Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * use to describe MPI SSP INI TM Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct ssp_ini_tm_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) __le32 relate_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __le32 tmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 lun[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) __le32 ds_ads_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct ssp_info_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 lun[8];/* SCSI Logical Unit Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u8 reserved1;/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u8 efb_prio_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* B7 : enabledFirstBurst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* B6-3 : taskPriority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* B2-0 : taskAttribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 reserved2; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u8 additional_cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* B7-2 : additional_cdb_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* B1-0 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * brief the data structure of SSP INI IO Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * use to describe MPI SSP INI IO Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Note: This structure is common for normal / encryption I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct ssp_ini_io_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) __le32 dad_dir_m_tlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct ssp_info_unit ssp_iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) __le32 addr_low; /* dword 12: sgl low for normal I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* epl_descl for encryption I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __le32 addr_high; /* dword 13: sgl hi for normal I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* dpl_descl for encryption I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __le32 len; /* dword 14: len for normal I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* edpl_desch for encryption I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) __le32 esgl; /* dword 15: ESGL bit for normal I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* user defined tag mask for enc I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* The below fields are reserved for normal I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 udt[12]; /* dword 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __le32 sectcnt_ios; /* dword 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) __le32 key_cmode; /* dword 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) __le32 ks_enss; /* dword 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __le32 keytagl; /* dword 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __le32 keytagh; /* dword 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __le32 twk_val0; /* dword 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) __le32 twk_val1; /* dword 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __le32 twk_val2; /* dword 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __le32 twk_val3; /* dword 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __le32 enc_len; /* dword 30: Encryption length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __le32 enc_esgl; /* dword 31: ESGL bit for encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * use to initiate SSP I/O operation with optional DIF/ENC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct ssp_dif_enc_io_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __le32 dirMTlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) __le32 sspiu0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __le32 sspiu1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __le32 sspiu2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __le32 sspiu3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __le32 sspiu4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __le32 sspiu5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __le32 sspiu6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) __le32 epl_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __le32 dpl_desl_ndplr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __le32 dpl_desh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) __le32 uum_uuv_bss_difbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 udt[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __le32 sectcnt_ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) __le32 key_cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __le32 ks_enss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __le32 keytagl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) __le32 keytagh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __le32 twk_val0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __le32 twk_val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __le32 twk_val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __le32 twk_val3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __le32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) __le32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __le32 esgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * brief the data structure of Firmware download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * use to describe MPI FW DOWNLOAD Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct fw_flash_Update_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __le32 cur_image_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __le32 cur_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __le32 total_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 reserved0[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) __le32 sgl_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __le32 sgl_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __le32 ext_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 reserved1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define FWFLASH_IOMB_RESERVED_LEN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * brief the data structure of FW_FLASH_UPDATE Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct fw_flash_Update_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * brief the data structure of Get NVM Data Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * use to get data from NVM in HBA(64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct get_nvm_data_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) __le32 len_ir_vpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __le32 vpd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __le32 resp_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) __le32 resp_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __le32 resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u32 reserved1[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct set_nvm_data_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) __le32 len_ir_vpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __le32 vpd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) __le32 resp_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) __le32 resp_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) __le32 resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 reserved1[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * brief the data structure for SET CONTROLLER CONFIG COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * use to modify controller configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct set_ctrl_cfg_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) __le32 cfg_pg[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 reserved[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * brief the data structure for GET CONTROLLER CONFIG COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * use to get controller configuration page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct get_ctrl_cfg_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __le32 pgcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) __le32 int_vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 reserved[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * brief the data structure for KEK_MANAGEMENT COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * use for KEK management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct kek_mgmt_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __le32 new_curidx_ksop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) __le32 kblob[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u32 reserved1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * brief the data structure for DEK_MANAGEMENT COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * use for DEK management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct dek_mgmt_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) __le32 kidx_dsop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __le32 dekidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) __le32 addr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) __le32 addr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __le32 nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) __le32 dbf_tblsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * brief the data structure for SET PHY PROFILE COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * use to retrive phy specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct set_phy_profile_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __le32 ppc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 reserved[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * brief the data structure for GET PHY PROFILE COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * use to retrive phy specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct get_phy_profile_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __le32 ppc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) __le32 profile[29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * brief the data structure for EXT FLASH PARTITION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * use to manage ext flash partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct ext_flash_partition_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) __le32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) __le32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) __le32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) __le32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __le32 len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) __le32 ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 reserved1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define TWI_DEVICE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define C_SEEPROM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define VPD_FLASH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define AAP1_RDUMP 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define IOP_RDUMP 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define EXPAN_ROM 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define IPMode 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define NVMD_TYPE 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define NVMD_STAT 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define NVMD_LEN 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * brief the data structure of Get NVMD Data Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * use to describe MPI Get NVMD Data Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct get_nvm_data_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) __le32 ir_tda_bn_dps_das_nvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) __le32 dlen_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) __le32 nvm_data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * brief the data structure of SAS Diagnostic Start/End Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct sas_diag_start_end_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * brief the data structure of SAS Diagnostic Execute Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct sas_diag_execute_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) __le32 cmdtype_cmddesc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) __le32 Status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) __le32 ReportData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * brief the data structure of Set Device State Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * use to describe MPI Set Device State Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct set_dev_state_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __le32 pds_nds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* new outbound structure for spcv - begins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * brief the data structure for SET CONTROLLER CONFIG COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * use to modify controller configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct set_ctrl_cfg_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) __le32 err_qlfr_pgcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct get_ctrl_cfg_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) __le32 err_qlfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) __le32 confg_page[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct kek_mgmt_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) __le32 kidx_new_curr_ksop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) __le32 err_qlfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct dek_mgmt_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) __le32 kekidx_tbls_dsop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) __le32 dekidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) __le32 err_qlfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u32 reserved[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct get_phy_profile_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) __le32 ppc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) __le32 ppc_specific_rsp[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct flash_op_ext_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) __le32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) __le32 epart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) __le32 epart_sect_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u32 reserved[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct set_phy_profile_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __le32 ppc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) __le32 ppc_specific_rsp[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct ssp_coalesced_comp_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) __le32 coal_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) __le32 tag0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __le32 ssp_tag0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) __le32 tag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) __le32 ssp_tag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) __le32 add_tag_ssp_tag[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* new outbound structure for spcv - ends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* brief data structure for SAS protocol timer configuration page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct SASProtocolTimerConfig {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) __le32 pageCode; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __le32 MST_MSI; /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) __le32 STP_SSP_MCT_TMO; /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) __le32 STP_FRM_TMO; /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) __le32 STP_IDLE_TMO; /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __le32 OPNRJT_RTRY_INTVL; /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) __le32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) __le32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) __le32 MAX_AIP; /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define NDS_BITS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define PDS_BITS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * HW Events type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define HW_EVENT_RESET_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define HW_EVENT_PHY_STOP_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define HW_EVENT_SAS_PHY_UP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define HW_EVENT_SATA_PHY_UP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define HW_EVENT_SATA_SPINUP_HOLD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define HW_EVENT_PHY_DOWN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define HW_EVENT_PORT_INVALID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define HW_EVENT_BROADCAST_CHANGE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define HW_EVENT_PHY_ERROR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define HW_EVENT_BROADCAST_SES 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define HW_EVENT_MALFUNCTION 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define HW_EVENT_BROADCAST_EXP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define HW_EVENT_PHY_START_STATUS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define HW_EVENT_PORT_RECOVER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define HW_EVENT_PORT_RESET_COMPLETE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define PORT_NOT_ESTABLISHED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define PORT_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define PORT_LOSTCOMM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define PORT_IN_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define PORT_3RD_PARTY_RESET 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define PORT_INVALID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * SSP/SMP/SATA IO Completion Status values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define IO_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define IO_ABORTED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define IO_OVERFLOW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define IO_UNDERFLOW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define IO_FAILED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define IO_ABORT_RESET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define IO_NOT_VALID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define IO_NO_DEVICE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define IO_ILLEGAL_PARAMETER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define IO_LINK_FAILURE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define IO_PROG_ERROR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define IO_EDC_IN_ERROR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define IO_EDC_OUT_ERROR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define IO_ERROR_HW_TIMEOUT 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define IO_XFER_ERROR_BREAK 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define IO_OPEN_CNX_ERROR_BREAK 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* This error code 0x18 is not used on SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define IO_XFER_ERROR_NAK_RECEIVED 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define IO_XFER_ERROR_PEER_ABORTED 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define IO_XFER_ERROR_RX_FRAME 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define IO_XFER_ERROR_DMA 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define IO_XFER_ERROR_SATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* This error code 0x22 is not used on SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* This error code 0x25 is not used on SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* The following error code 0x31 and 0x32 are not using (obsolete) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define IO_XFER_CMD_FRAME_ISSUED 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define IO_PORT_IN_RESET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define IO_DS_NON_OPERATIONAL 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define IO_DS_IN_RECOVERY 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define IO_TM_TAG_NOT_FOUND 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define IO_XFER_PIO_SETUP_ERROR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define IO_DS_IN_ERROR 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define IO_ABORT_IN_PROGRESS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define IO_ABORT_DELAYED 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define IO_INVALID_LENGTH 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /********** additional response event values *****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define IO_DS_INVALID 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* WARNING: the value is not contiguous from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define MPI_IO_RQE_BUSY_FULL 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * An encryption IO request failed due to DEK Key Tag mismatch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * The key tag supplied in the encryption IOMB does not match with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * the Key Tag in the referenced DEK Entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * An encryption I/O request failed because the initial value (IV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * in the unwrapped DEK blob didn't match the IV used to unwrap it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* An encryption I/O request failed due to an internal RAM ECC or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * interface error while unwrapping the DEK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* An encryption I/O request failed due to an internal RAM ECC or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * interface error while unwrapping the DEK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define IO_XFR_ERROR_INTERNAL_RAM 0x2045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * An encryption I/O request failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * because the DEK index specified in the I/O was outside the bounds of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * the total number of entries in the host DEK table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* define DIF IO response error status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define IO_XFR_ERROR_DIF_MISMATCH 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* define operator management response status and error qualifier code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /***************** additional response event values ***************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* WARNING: This error code must always be the last number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * If you add error code, modify this code also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * It is used as an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define IO_ERROR_UNKNOWN_GENERIC 0x2023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* MSGU CONFIGURATION TABLE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define SPCv_MSGU_CFG_TABLE_RESET 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define MSGU_IBDB_SET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define MSGU_HOST_INT_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define MSGU_HOST_INT_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define MSGU_IOPIB_INT_STATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define MSGU_IOPIB_INT_MASK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define MSGU_IBDB_CLEAR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define MSGU_MSGU_CONTROL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define MSGU_ODR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define MSGU_ODCR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define MSGU_ODMR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define MSGU_ODMR_U 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define MSGU_ODMR_CLR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define MSGU_ODMR_CLR_U 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define MSGU_OD_RSVD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define MSGU_SCRATCH_PAD_0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define MSGU_SCRATCH_PAD_1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define MSGU_SCRATCH_PAD_2 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define MSGU_SCRATCH_PAD_3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define MSGU_HOST_SCRATCH_PAD_0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define MSGU_HOST_SCRATCH_PAD_1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define MSGU_HOST_SCRATCH_PAD_2 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define MSGU_HOST_SCRATCH_PAD_3 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define MSGU_HOST_SCRATCH_PAD_4 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define MSGU_HOST_SCRATCH_PAD_5 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define MSGU_HOST_SCRATCH_PAD_6 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define MSGU_HOST_SCRATCH_PAD_7 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* bit definition for ODMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define ODMR_CLEAR_ALL 0 /* clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* bit definition for ODCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) interrupt vector*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* MSIX Interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define MSIX_TABLE_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define MSIX_TABLE_ELEMENT_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) MSIX_INTERRUPT_CONTROL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define MSIX_INTERRUPT_DISABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define MSIX_INTERRUPT_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* state definition for Scratch Pad1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define SCRATCH_PAD_RAAE_READY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define SCRATCH_PAD_ILA_READY 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define SCRATCH_PAD_IOP0_READY 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define SCRATCH_PAD_IOP1_READY 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define SCRATCH_PAD_MIPSALL_READY_16PORT (SCRATCH_PAD_IOP1_READY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SCRATCH_PAD_IOP0_READY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SCRATCH_PAD_ILA_READY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SCRATCH_PAD_RAAE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define SCRATCH_PAD_MIPSALL_READY_8PORT (SCRATCH_PAD_IOP0_READY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) SCRATCH_PAD_ILA_READY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SCRATCH_PAD_RAAE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* boot loader state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* state definition for Scratch Pad2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define SCRATCH_PAD2_POR 0x00 /* power on state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define SCRATCH_PAD2_ERR 0x02 /* error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define SCRATCH_PAD2_RDY 0x03 /* ready state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) Mask, bit1-0 State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) Reserved bit 2 to 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* main configuration offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* 0x28 - 0x4C - RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define MAIN_MPI_ILA_RELEASE_TYPE 0xA4 /* DWORD 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define MAIN_MPI_INACTIVE_FW_VERSION 0XB0 /* DWORD 0x2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* Gereral Status Table offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define GST_GSTLEN_MPIS_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define GST_MSGUTCNT_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define GST_IOPTCNT_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* 0x14 - 0x34 - RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define GST_GPIO_INPUT_VAL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* 0x3c - 0x40 - RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define GST_RERRINFO_OFFSET0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define GST_RERRINFO_OFFSET1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define GST_RERRINFO_OFFSET2 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define GST_RERRINFO_OFFSET3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define GST_RERRINFO_OFFSET4 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define GST_RERRINFO_OFFSET5 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define GST_RERRINFO_OFFSET6 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define GST_RERRINFO_OFFSET7 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* General Status Table - MPI state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define GST_MPI_STATE_UNINIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define GST_MPI_STATE_INIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define GST_MPI_STATE_TERMINATION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define GST_MPI_STATE_ERROR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define GST_MPI_STATE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Per SAS PHY Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* end PSPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* inbound queue configuration offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define IB_PROPERITY_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define IB_BASE_ADDR_HI_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define IB_BASE_ADDR_LO_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define IB_CI_BASE_ADDR_LO_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define IB_PIPCI_BAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define IB_PIPCI_BAR_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define IB_RESERVED_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* outbound queue configuration offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define OB_PROPERITY_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define OB_BASE_ADDR_HI_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define OB_BASE_ADDR_LO_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define OB_PI_BASE_ADDR_LO_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define OB_CIPCI_BAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define OB_CIPCI_BAR_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define OB_INTERRUPT_COALES_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define OB_DYNAMIC_COALES_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define OB_PROPERTY_INT_ENABLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define PCIE_EVENT_INTERRUPT 0x003044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define PCIE_ERROR_INTERRUPT 0x00304C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* SPCV soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define SPC_REG_SOFT_RESET 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define SPCv_NORMAL_RESET_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define SPCv_SOFT_RESET_READ_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define SPCv_SOFT_RESET_NO_RESET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* signature definition for host scratch pad0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Signature for Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define SPC_REG_RESET 0x000000/* reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* bit definition for SPC_RESET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define SPC_REG_RESET_OSSP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define SPC_REG_RESET_RAAE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define SPC_REG_RESET_PCS_SPBC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define SPC_REG_RESET_PCS_LM 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define SPC_REG_RESET_PCS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define SPC_REG_RESET_GSM 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define SPC_REG_RESET_DDR2 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define SPC_REG_RESET_BDMA_CORE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define SPC_REG_RESET_PCIE_PWR 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define SPC_REG_RESET_PCIE_SFT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define SPC_REG_RESET_PCS_SXCBI 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define SPC_REG_RESET_LMS_SXCBI 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define SPC_REG_RESET_PMIC_CORE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define SPC_REG_RESET_DEVICE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define MBIC_AAP1_ADDR_BASE 0x060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define MBIC_IOP_ADDR_BASE 0x070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define GSM_ADDR_BASE 0x0700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* Dynamic map through Bar4 - 0x00700000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define GSM_CONFIG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define RAM_ECC_DB_ERR 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define RB6_ACCESS_REG 0x6A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define HDAC_EXEC_CMD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define HDA_C_PA 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define HDA_SEQ_ID_BITS 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define HDA_GSM_CMD_OFFSET_BITS 0x42C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define HDA_GSM_RSP_OFFSET_BITS 0x42E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define MBIC_AAP1_ADDR_BASE 0x060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define MBIC_IOP_ADDR_BASE 0x070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define GSM_ADDR_BASE 0x0700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define GSM_CONFIG_RESET_VALUE 0x00003b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define GPIO_ADDR_BASE 0x00090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* RB6 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define SPC_RB6_OFFSET 0x80C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* Magic number of soft reset for RB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define RB6_MAGIC_NUMBER_RST 0x1234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* Device Register status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define DEVREG_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define MEMBASE_II_SHIFT_REGISTER 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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