^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 USI Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef _PM8001_SAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define _PM8001_SAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <scsi/libsas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <scsi/sas_ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "pm8001_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRV_NAME "pm80xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRV_VERSION "0.1.40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PM8001_INIT_LOGGING 0x02 /* driver init logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PM8001_IO_LOGGING 0x08 /* I/O path logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PM8001_MSG_LOGGING 0x40 /* misc message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PM8001_DEV_LOGGING 0x80 /* development message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define pm8001_printk(fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_info("%s:: %s %d:" fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pm8001_ha->name, __func__, __LINE__, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define pm8001_dbg(HBA, level, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pm8001_printk(fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PM8001_READ_VPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) || (dev->device == 0X8076) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) || (dev->device == 0X8077) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) || (dev->device == 0X8070) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) || (dev->device == 0X8072))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PM8001_NAME_LENGTH 32/* generic length of strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern struct list_head hba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern const struct pm8001_dispatch pm8001_8001_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern const struct pm8001_dispatch pm8001_80xx_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pm8001_hba_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pm8001_ccb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pm8001_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* define task management IU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pm8001_tmf_task {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 tmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 tag_of_task_to_be_managed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct pm8001_ioctl_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 major_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 minor_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 wr_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 rd_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 *func_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TYPE_GSM_SPACE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TYPE_QUEUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TYPE_FATAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TYPE_NON_FATAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TYPE_INBOUND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TYPE_OUTBOUND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct forensic_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 direct_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 direct_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void *direct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } gsm_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 queue_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 direct_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void *direct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } queue_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 direct_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 direct_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void *direct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } data_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* bit31-26 - mask bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SCRATCH_PAD0_BAR_MASK 0xFC000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* bit25-0 - offset mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* if AAP error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Inbound doorbell bit7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Inbound doorbell bit7 SPCV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pm8001_dispatch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pm8001_ccb_info *ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct pm8001_ccb_info *ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pm8001_ccb_info *ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pm8001_device *pm8001_dev, u32 flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 phy_id, u32 phy_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 cmd_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct pm8001_device *pm8001_dev, u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct pm8001_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 encrypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct pm8001_dispatch *dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pm8001_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct asd_sas_port sas_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 port_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 wide_port_phymap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct pm8001_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pm8001_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct asd_sas_phy sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sas_identify identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 dev_sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct completion *enable_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 frame_rcvd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 frame_rcvd[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 phy_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 phy_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum sas_linkrate minimum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum sas_linkrate maximum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct completion *reset_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bool port_reset_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool reset_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* port reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PORT_RESET_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PORT_RESET_TMO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct pm8001_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum sas_device_type dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct domain_device *sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 attached_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct completion *dcompletion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct completion *setds_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) atomic_t running_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct pm8001_prd_imt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct pm8001_prd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __le64 addr; /* 64-bit buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct pm8001_prd_imt im_len; /* 64-bit length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * CCB(Command Control Block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pm8001_ccb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct sas_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 n_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_addr_t ccb_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct pm8001_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct pm8001_prd *buf_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct fw_control_ex *fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 open_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct mpi_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void *virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 num_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 element_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct mpi_mem_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* The number of element in the mpiMemory array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* The array of structures that define memroy regions*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mpi_mem region[USI_MAX_MEMCNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct encrypt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 sec_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sas_phy_attribute_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 phystart1_16[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 outbound_hw_event_pid1_16[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) union main_cfg_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 interface_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 firmware_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 max_out_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 max_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 ctrl_cap_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 gst_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 inbound_queue_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 outbound_queue_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 inbound_q_nppd_hppd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 outbound_hw_event_pid0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 outbound_hw_event_pid4_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 outbound_ncq_event_pid0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 outbound_ncq_event_pid4_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 outbound_tgt_ITNexus_event_pid0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 outbound_tgt_ITNexus_event_pid4_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 outbound_tgt_ssp_event_pid0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 outbound_tgt_ssp_event_pid4_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 outbound_tgt_smp_event_pid0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 outbound_tgt_smp_event_pid4_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 upper_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 lower_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 event_log_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 event_log_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 upper_iop_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 lower_iop_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 iop_event_log_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 iop_event_log_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 fatal_err_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 fatal_err_dump_offset0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 fatal_err_dump_length0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 fatal_err_dump_offset1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 fatal_err_dump_length1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 hda_mode_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 anolog_setup_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } pm8001_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 interface_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 firmware_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 max_out_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 max_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 ctrl_cap_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 gst_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 inbound_queue_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 outbound_queue_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 inbound_q_nppd_hppd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 rsvd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 crc_core_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 upper_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 lower_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 event_log_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 event_log_severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 upper_pcs_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 lower_pcs_event_log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 pcs_event_log_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 pcs_event_log_severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 fatal_err_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 fatal_err_dump_offset0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 fatal_err_dump_length0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 fatal_err_dump_offset1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 fatal_err_dump_length1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 gpio_led_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 analog_setup_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 int_vec_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 phy_attr_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 port_recovery_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 interrupt_reassertion_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 fatal_n_non_fatal_dump; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 ila_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 inc_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } pm80xx_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) union general_status_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 gst_len_mpistate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 iq_freeze_state0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 iq_freeze_state1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 msgu_tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 iop_tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 phy_state[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 gpio_input_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 rsvd1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 recover_err_info[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } pm8001_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 gst_len_mpistate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 iq_freeze_state0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 iq_freeze_state1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 msgu_tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 iop_tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 rsvd[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 gpio_input_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 rsvd1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 recover_err_info[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } pm80xx_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct inbound_queue_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 element_pri_size_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 upper_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 lower_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 ci_upper_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 ci_lower_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 pi_pci_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 pi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 total_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void *base_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void *ci_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __le32 consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 producer_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spinlock_t iq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct outbound_queue_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 element_size_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 upper_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 lower_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void *base_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 pi_upper_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 pi_lower_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 ci_pci_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 ci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 total_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void *pi_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 interrup_vec_cnt_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 dinterrup_to_pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __le32 producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 consumer_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct pm8001_hba_memspace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) void __iomem *memvirtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u64 membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct isr_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct pm8001_hba_info *drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct pm8001_hba_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) char name[PM8001_NAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spinlock_t lock;/* host-wide lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spinlock_t bitmap_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pci_dev *pdev;/* our device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct pm8001_hba_memspace io_mem[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mpi_mem_req memoryMap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct encrypt encrypt_info; /* support encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct forensic_data forensic_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 fatal_bar_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 forensic_last_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 fatal_forensic_shift_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 forensic_fatal_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 forensic_preserved_accumulated_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 evtlog_ib_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 evtlog_ob_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void __iomem *pspa_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*MPI SAS PHY attributes Queue Config Table Addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) union main_cfg_table main_cfg_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) union general_status_table gs_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct sas_phy_attribute_table phy_attr_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* MPI SAS PHY attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct sas_ha_struct *sas;/* SCSI/SAS glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct pm8001_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct completion *nvmd_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int tags_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned long *tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct pm8001_phy phy[PM8001_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct pm8001_port port[PM8001_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 iomb_size; /* SPC and SPCV IOMB size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct pm8001_device *devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct pm8001_ccb_info *ccb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int number_of_intr;/*will be used in remove()*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) char intr_drvname[PM8001_MAX_MSIX_VEC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [PM8001_NAME_LENGTH+1+3+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 logging_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 fw_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 smp_exp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bool controller_fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) const struct firmware *fw_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 reset_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 non_fatal_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 non_fatal_read_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 max_q_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 ib_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 ob_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 ci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 pi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 max_memcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct pm8001_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct pm8001_fw_image_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u8 vender_id[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 product_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u8 hardware_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 dest_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 fw_rev[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __be32 image_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __be32 image_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __be32 startup_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * FW Flash Update status values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define FLASH_UPDATE_IN_PROGRESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define FLASH_UPDATE_HDR_ERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define FLASH_UPDATE_OFFSET_ERR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define FLASH_UPDATE_CRC_ERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define FLASH_UPDATE_LENGTH_ERR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define FLASH_UPDATE_HW_ERR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define FLASH_UPDATE_DISABLED 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define NCQ_READ_LOG_FLAG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define NCQ_ABORT_ALL_FLAG 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define NCQ_2ND_RLE_FLAG 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define DS_OPERATIONAL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DS_PORT_IN_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define DS_IN_RECOVERY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define DS_IN_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DS_NON_OPERATIONAL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * brief param structure for firmware flash update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct fw_flash_updata_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 cur_image_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 cur_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 total_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct pm8001_prd sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct fw_control_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 retcode;/*ret code (status)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 phase;/*ret code phase*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 phaseCmplt;/*percent complete for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) update phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 version;/*Hex encoded firmware version number*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 offset;/*Used for downloading firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 len; /*len of buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 size;/* Used in OS VPD and Trace get size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) operations.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 reserved;/* padding required for 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u8 buffer[1];/* Start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct fw_control_ex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct fw_control_info *fw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void *buffer;/* keep buffer pointer to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) freed when the response comes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void *virtAddr;/* keep virtual address of the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) void *usrAddr;/* keep virtual address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) user data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 len; /* len of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void *payload; /* pointer to IOCTL Payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 inProgress;/*if 1 - the IOCTL request is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) void *param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void *param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) void *param3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* pm8001 workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) extern struct workqueue_struct *pm8001_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /******************** function prototype *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) void *funcdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void pm8001_scan_start(struct Scsi_Host *shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int pm8001_abort_task(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int pm8001_dev_found(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) void pm8001_dev_gone(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int pm8001_I_T_nexus_reset(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int pm8001_query_task(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void pm8001_open_reject_retry(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sas_task *task_to_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct pm8001_device *device_to_close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 mem_size, u32 align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct inbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 opCode, void *payload, size_t nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 responseQueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u16 messageSize, void **messagePtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct outbound_queue_table *circularQ, u8 bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct outbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void **messagePtr1, u8 *pBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct pm8001_device *pm8001_dev, u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void *fw_flash_updata_info, u32 tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct pm8001_ccb_info *ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct pm8001_tmf_task *tmf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct pm8001_device *pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 flag, u32 task_tag, u32 cmd_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) void pm8001_work_fn(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void *data, int handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct sas_task *pm8001_alloc_task(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) void pm8001_task_done(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) void pm8001_free_task(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 length, u8 *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 phy, u32 length, u32 *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ssize_t pm80xx_get_fatal_dump(struct device *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* ctl shared API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) extern struct device_attribute *pm8001_host_attrs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct sas_task *task, struct pm8001_ccb_info *ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 ccb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) smp_mb(); /*in order to force CPU ordering*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) spin_unlock(&pm8001_ha->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) task->task_done(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spin_lock(&pm8001_ha->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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