^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 USI Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "pm8001_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "pm8001_chips.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "pm80xx_hwi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(logging_level, ulong, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param(link_rate, ulong, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) " 1: Link rate 1.5G\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) " 2: Link rate 3.0G\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) " 4: Link rate 6.0G\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) " 8: Link rate 12.0G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct scsi_transport_template *pm8001_stt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * chip info structure to identify chip key functionality as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * encryption available/not, no of ports, hw specific function ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct pm8001_chip_info pm8001_chips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int pm8001_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) LIST_HEAD(hba_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct workqueue_struct *pm8001_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * The main structure which LLDD must register for scsi core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct scsi_host_template pm8001_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .queuecommand = sas_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .dma_need_drain = ata_scsi_dma_need_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .target_alloc = sas_target_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .slave_configure = sas_slave_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .scan_finished = pm8001_scan_finished,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .scan_start = pm8001_scan_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .change_queue_depth = sas_change_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .bios_param = sas_bios_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .can_queue = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .this_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .sg_tablesize = PM8001_MAX_DMA_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .eh_device_reset_handler = sas_eh_device_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .eh_target_reset_handler = sas_eh_target_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .slave_alloc = sas_slave_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .target_destroy = sas_target_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .ioctl = sas_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .compat_ioctl = sas_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .shost_attrs = pm8001_host_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .track_queue_depth = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Sas layer call this function to execute specific task.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct sas_domain_function_template pm8001_transport_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .lldd_dev_found = pm8001_dev_found,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .lldd_dev_gone = pm8001_dev_gone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .lldd_execute_task = pm8001_queue_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .lldd_control_phy = pm8001_phy_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .lldd_abort_task = pm8001_abort_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .lldd_abort_task_set = pm8001_abort_task_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .lldd_clear_aca = pm8001_clear_aca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .lldd_clear_task_set = pm8001_clear_task_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .lldd_lu_reset = pm8001_lu_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .lldd_query_task = pm8001_query_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * pm8001_phy_init - initiate our adapter phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @pm8001_ha: our hba structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @phy_id: phy id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct asd_sas_phy *sas_phy = &phy->sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) phy->phy_state = PHY_LINK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy->pm8001_ha = pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sas_phy->class = SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sas_phy->iproto = SAS_PROTOCOL_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) sas_phy->tproto = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sas_phy->type = PHY_TYPE_PHYSICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sas_phy->role = PHY_ROLE_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sas_phy->oob_mode = OOB_NOT_CONNECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sas_phy->id = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sas_phy->frame_rcvd = &phy->frame_rcvd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sas_phy->lldd_phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * pm8001_free - free hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @pm8001_ha: our hba structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < USI_MAX_MEMCNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dma_free_coherent(&pm8001_ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (pm8001_ha->memoryMap.region[i].total_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pm8001_ha->memoryMap.region[i].alignment),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pm8001_ha->memoryMap.region[i].virt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pm8001_ha->memoryMap.region[i].phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) flush_workqueue(pm8001_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) kfree(pm8001_ha->tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kfree(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * tasklet for 64 msi-x interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @opaque: the passed general host adapter struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Note: pm8001_tasklet is common for pm8001 & pm80xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void pm8001_tasklet(unsigned long opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct isr_param *irq_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) irq_vector = (struct isr_param *)opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pm8001_ha = irq_vector->drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (unlikely(!pm8001_ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * It obtains the vector number and calls the equivalent bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * half or services directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @opaque: the passed outbound queue/vector. Host structure is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * retrieved from the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct isr_param *irq_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq_vector = (struct isr_param *)opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pm8001_ha = irq_vector->drv_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (unlikely(!pm8001_ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * pm8001_interrupt_handler_intx - main INTx interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct sas_ha_struct *sha = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (unlikely(!pm8001_ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tasklet_schedule(&pm8001_ha->tasklet[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * pm8001_alloc - initiate our hba structure and 6 DMAs area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @pm8001_ha: our hba structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @ent: PCI device ID structure to match on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i, count = 0, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 ci_offset, ib_offset, ob_offset, pi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_lock_init(&pm8001_ha->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock_init(&pm8001_ha->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pm8001_ha->chip->n_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Setup Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rc = pm8001_setup_irq(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "pm8001_setup_irq failed [ret: %d]\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Request Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rc = pm8001_request_irq(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) count = pm8001_ha->max_q_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Queues are chosen based on the number of cores/msix availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ci_offset = pm8001_ha->ci_offset = ib_offset + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ob_offset = pm8001_ha->ob_offset = ci_offset + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pi_offset = pm8001_ha->pi_offset = ob_offset + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pm8001_ha->max_memcnt = pi_offset + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pm8001_phy_init(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pm8001_ha->port[i].wide_port_phymap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pm8001_ha->port[i].port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pm8001_ha->port[i].port_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) INIT_LIST_HEAD(&pm8001_ha->port[i].list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* MPI Memory region 1 for AAP Event Log for fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pm8001_ha->memoryMap.region[AAP1].alignment = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* MPI Memory region 2 for IOP Event Log for fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pm8001_ha->memoryMap.region[IOP].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pm8001_ha->memoryMap.region[IOP].alignment = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) circularQ = &pm8001_ha->inbnd_q_tbl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) spin_lock_init(&circularQ->iq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* MPI Memory region 3 for consumer Index of inbound queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((ent->driver_data) != chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* MPI Memory region 5 inbound queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pm8001_ha->memoryMap.region[ib_offset+i].element_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pm8001_ha->memoryMap.region[ib_offset+i].total_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PM8001_MPI_QUEUE * 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pm8001_ha->memoryMap.region[ib_offset+i].alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pm8001_ha->memoryMap.region[ib_offset+i].element_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pm8001_ha->memoryMap.region[ib_offset+i].total_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PM8001_MPI_QUEUE * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* MPI Memory region 4 for producer Index of outbound queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ent->driver_data != chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* MPI Memory region 6 Outbound queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pm8001_ha->memoryMap.region[ob_offset+i].element_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pm8001_ha->memoryMap.region[ob_offset+i].total_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PM8001_MPI_QUEUE * 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pm8001_ha->memoryMap.region[ob_offset+i].alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* MPI Memory region 6 Outbound queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pm8001_ha->memoryMap.region[ob_offset+i].element_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pm8001_ha->memoryMap.region[ob_offset+i].total_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PM8001_MPI_QUEUE * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Memory region write DMA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Memory region for fw flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < pm8001_ha->max_memcnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (pm8001_mem_alloc(pm8001_ha->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) &pm8001_ha->memoryMap.region[i].virt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &pm8001_ha->memoryMap.region[i].phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &pm8001_ha->memoryMap.region[i].phys_addr_hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) &pm8001_ha->memoryMap.region[i].phys_addr_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pm8001_ha->memoryMap.region[i].total_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pm8001_ha->memoryMap.region[i].alignment) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "Mem%d alloc failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Memory region for devices*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * sizeof(struct pm8001_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!pm8001_ha->devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto err_out_nodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for (i = 0; i < PM8001_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pm8001_ha->devices[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) atomic_set(&pm8001_ha->devices[i].running_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pm8001_ha->flags = PM8001F_INIT_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Initialize tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pm8001_tag_init(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) err_out_nodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (i = 0; i < pm8001_ha->max_memcnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pci_free_consistent(pm8001_ha->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (pm8001_ha->memoryMap.region[i].total_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pm8001_ha->memoryMap.region[i].alignment),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pm8001_ha->memoryMap.region[i].virt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pm8001_ha->memoryMap.region[i].phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * pm8001_ioremap - remap the pci high physical address to kernal virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * address so that we can access them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @pm8001_ha:our hba structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 logicalBar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pdev = pm8001_ha->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* map pci mem (PMC pci base 0-3)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ** logical BARs for SPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ** bar 0 and 1 - logical BAR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ** bar 2 and 3 - logical BAR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ** bar4 - logical BAR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ** bar5 - logical BAR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ** Skip the appropriate assignments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((bar == 1) || (bar == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pm8001_ha->io_mem[logicalBar].membase =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_resource_start(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pm8001_ha->io_mem[logicalBar].memsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_resource_len(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pm8001_ha->io_mem[logicalBar].memvirtaddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ioremap(pm8001_ha->io_mem[logicalBar].membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pm8001_ha->io_mem[logicalBar].memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "PCI: bar %d, logicalBar %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bar, logicalBar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "base addr %llx virt_addr=%llx len=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (u64)pm8001_ha->io_mem[logicalBar].membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (u64)(unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pm8001_ha->io_mem[logicalBar].memvirtaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pm8001_ha->io_mem[logicalBar].memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pm8001_ha->io_mem[logicalBar].membase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pm8001_ha->io_mem[logicalBar].memsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) logicalBar++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * pm8001_pci_alloc - initialize our ha card structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * @pdev: pci device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * @ent: ent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * @shost: scsi host struct which has been initialized before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const struct pci_device_id *ent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pm8001_ha->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pm8001_ha->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pm8001_ha->chip_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pm8001_ha->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pm8001_ha->sas = sha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm8001_ha->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pm8001_ha->id = pm8001_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pm8001_ha->logging_level = logging_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pm8001_ha->non_fatal_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (link_rate >= 1 && link_rate <= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pm8001_ha->link_rate = (link_rate << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) LINKRATE_60 | LINKRATE_120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "Setting link rate to default value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* IOMB size is 128 for 8088/89 controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (pm8001_ha->chip_id != chip_8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pm8001_ha->iomb_size = IOMB_SIZE_SPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Tasklet for non msi-x interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if ((!pdev->msix_cap || !pci_msi_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) || (pm8001_ha->chip_id == chip_8001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (unsigned long)&(pm8001_ha->irq_vector[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (unsigned long)&(pm8001_ha->irq_vector[j]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pm8001_ioremap(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!pm8001_alloc(pm8001_ha, ent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pm8001_free(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @pdev: pci device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int pci_go_44(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_printk(KERN_ERR, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "32-bit DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * @shost: scsi host which has been allocated outside.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * @chip_info: our ha struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct pm8001_chip_info *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int phy_nr, port_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct asd_sas_phy **arr_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct asd_sas_port **arr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) phy_nr = chip_info->n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) port_nr = phy_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memset(sha, 0x00, sizeof(*sha));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!arr_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!arr_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto exit_free2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sha->sas_phy = arr_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sha->sas_port = arr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!sha->lldd_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto exit_free1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) shost->transportt = pm8001_stt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) shost->max_id = PM8001_MAX_DEVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) shost->max_lun = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) shost->max_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) shost->unique_id = pm8001_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) shost->max_cmd_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) shost->can_queue = PM8001_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) shost->cmd_per_lun = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) exit_free1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) kfree(arr_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) exit_free2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) kfree(arr_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @shost: scsi host which has been allocated outside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @chip_info: our ha struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) const struct pm8001_chip_info *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (i = 0; i < chip_info->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) sha->sas_phy[i]->sas_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sha->sas_ha_name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sha->dev = pm8001_ha->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sha->strict_wide_ports = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) sha->lldd_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sha->sas_addr = &pm8001_ha->sas_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) sha->num_phys = chip_info->n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) sha->core.shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * pm8001_init_sas_add - initialize sas address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @pm8001_ha: our ha struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Currently we just set the fixed SAS address to our HBA,for manufacture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * it should read from the EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 sas_add[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #ifdef PM8001_READ_VPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* For new SPC controllers WWN is stored in flash vpd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * For SPC/SPCve controllers WWN is stored in EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * For Older SPC WWN is stored in NVMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) DECLARE_COMPLETION_ONSTACK(completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct pm8001_ioctl_payload payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u16 deviceid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pm8001_ha->nvmd_completion = &completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (pm8001_ha->chip_id == chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (deviceid == 0x8081 || deviceid == 0x0042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) payload.minor_function = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) payload.rd_length = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) payload.minor_function = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) payload.rd_length = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else if ((pm8001_ha->chip_id == chip_8070 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pm8001_ha->chip_id == chip_8072) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) payload.minor_function = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) payload.rd_length = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) payload.minor_function = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) payload.rd_length = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) payload.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!payload.func_specific) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) kfree(payload.func_specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) wait_for_completion(&completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0, j = 0; i <= 7; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (pm8001_ha->chip_id == chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (deviceid == 0x8081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pm8001_ha->sas_addr[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) payload.func_specific[0x704 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else if (deviceid == 0x0042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pm8001_ha->sas_addr[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) payload.func_specific[0x010 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } else if ((pm8001_ha->chip_id == chip_8070 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pm8001_ha->chip_id == chip_8072) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pm8001_ha->sas_addr[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) payload.func_specific[0x010 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pm8001_ha->sas_addr[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) payload.func_specific[0x804 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (i && ((i % 4) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) sas_add[7] = sas_add[7] + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) memcpy(&pm8001_ha->phy[i].dev_sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sas_add, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pm8001_ha->phy[i].dev_sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) kfree(payload.func_specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pm8001_ha->phy[i].dev_sas_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cpu_to_be64((u64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * pm8001_get_phy_settings_info : Read phy setting values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * @pm8001_ha : our hba.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #ifdef PM8001_READ_VPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*OPTION ROM FLASH read for the SPC cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DECLARE_COMPLETION_ONSTACK(completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct pm8001_ioctl_payload payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pm8001_ha->nvmd_completion = &completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* SAS ADDRESS read from flash / EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) payload.minor_function = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) payload.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) payload.rd_length = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) payload.func_specific = kzalloc(4096, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!payload.func_specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Read phy setting values from flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) kfree(payload.func_specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) wait_for_completion(&completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) kfree(payload.func_specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct pm8001_mpi3_phy_pg_trx_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 LaneLosCfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 LanePgaCfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 LanePisoCfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 LanePisoCfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 LanePisoCfg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 LanePisoCfg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 LanePisoCfg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 LanePisoCfg6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 LaneBctCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * @pm8001_ha : our adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * @phycfg : PHY config page to populate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct pm8001_mpi3_phy_pg_trx_config *phycfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) phycfg->LaneLosCfg = 0x00000132;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) phycfg->LanePgaCfg1 = 0x00203949;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) phycfg->LanePisoCfg1 = 0x000000FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) phycfg->LanePisoCfg2 = 0xFF000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) phycfg->LanePisoCfg3 = 0xE7011300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) phycfg->LanePisoCfg4 = 0x631C40C0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) phycfg->LanePisoCfg5 = 0xF8102036;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) phycfg->LanePisoCfg6 = 0xF74A1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) phycfg->LaneBctCtrl = 0x00FB33F8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * pm8001_get_external_phy_settings : Retrieves the external PHY settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * @pm8001_ha : our adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * @phycfg : PHY config page to populate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct pm8001_mpi3_phy_pg_trx_config *phycfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) phycfg->LaneLosCfg = 0x00000132;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) phycfg->LanePgaCfg1 = 0x00203949;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) phycfg->LanePisoCfg1 = 0x000000FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) phycfg->LanePisoCfg2 = 0xFF000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) phycfg->LanePisoCfg3 = 0xE7011300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) phycfg->LanePisoCfg4 = 0x63349140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) phycfg->LanePisoCfg5 = 0xF8102036;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) phycfg->LanePisoCfg6 = 0xF80D9300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) phycfg->LaneBctCtrl = 0x00FB33F8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * @pm8001_ha : our adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * @phymask : The PHY mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) switch (pm8001_ha->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case 0x0070: /* H1280 - 8 external 0 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 0x0072: /* H12F0 - 16 external 0 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *phymask = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case 0x0071: /* H1208 - 0 external 8 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case 0x0073: /* H120F - 0 external 16 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *phymask = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case 0x0080: /* H1244 - 4 external 4 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *phymask = 0x00F0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case 0x0081: /* H1248 - 4 external 8 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *phymask = 0x0FF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case 0x0082: /* H1288 - 8 external 8 internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) *phymask = 0xFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "Unknown subsystem device=0x%.04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pm8001_ha->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * @pm8001_ha : our adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int phymask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) memset(&phycfg_int, 0, sizeof(phycfg_int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) memset(&phycfg_ext, 0, sizeof(phycfg_ext));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pm8001_get_phy_mask(pm8001_ha, &phymask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (phymask & (1 << i)) {/* Internal PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pm8001_set_phy_profile_single(pm8001_ha, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) sizeof(phycfg_int) / sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) (u32 *)&phycfg_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) } else { /* External PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pm8001_set_phy_profile_single(pm8001_ha, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) sizeof(phycfg_ext) / sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) (u32 *)&phycfg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * @pm8001_ha : our hba.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) switch (pm8001_ha->pdev->subsystem_vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case PCI_VENDOR_ID_ATTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case PCI_VENDOR_ID_ADAPTEC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return pm8001_get_phy_settings_info(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * pm8001_setup_msix - enable MSI-X interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * @pm8001_ha: our ha struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 number_of_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int rc, cpu_online_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int allocated_irq_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* SPCv controllers supports 64 msi-x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (pm8001_ha->chip_id == chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) number_of_intr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) number_of_intr = PM8001_MAX_MSIX_VEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) cpu_online_count = num_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) number_of_intr = min_t(int, cpu_online_count, number_of_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) number_of_intr, PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) allocated_irq_vectors = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Assigns the number of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pm8001_ha->number_of_intr = number_of_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Maximum queue number updating in HBA structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pm8001_ha->max_q_num = number_of_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rc, pm8001_ha->number_of_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u32 i = 0, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int flag = 0, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (pm8001_ha->chip_id != chip_8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) flag &= ~IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "pci_enable_msix request number of intr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pm8001_ha->number_of_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) for (i = 0; i < pm8001_ha->number_of_intr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) snprintf(pm8001_ha->intr_drvname[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) sizeof(pm8001_ha->intr_drvname[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) "%s-%d", pm8001_ha->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pm8001_ha->irq_vector[i].irq_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pm8001_interrupt_handler_msix, flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) pm8001_ha->intr_drvname[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) &(pm8001_ha->irq_vector[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) for (j = 0; j < i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) free_irq(pci_irq_vector(pm8001_ha->pdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) &(pm8001_ha->irq_vector[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pci_free_irq_vectors(pm8001_ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pdev = pm8001_ha->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return pm8001_setup_msix(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * pm8001_request_irq - register interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * @pm8001_ha: our ha struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pdev = pm8001_ha->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (pdev->msix_cap && pci_msi_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return pm8001_request_msix(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) goto intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) intx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* initialize the INT-X interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pm8001_ha->irq_vector[0].irq_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * pm8001_pci_probe - probe supported device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * @pdev: pci device which kernel has been prepared for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * @ent: pci device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * This function is the main initialization function, when register a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * pci driver it is invoked, all struct an hardware initilization should be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * here, also, register interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int pm8001_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) unsigned int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 pci_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u8 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct Scsi_Host *shost = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) const struct pm8001_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct sas_ha_struct *sha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "pm80xx: driver version %s\n", DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto err_out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * Enable pci slot busmaster by setting pci command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * This is required by FW for Cyclone card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pci_reg |= 0x157;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) rc = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rc = pci_go_44(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!shost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) chip = &pm8001_chips[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!sha) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) goto err_out_free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) SHOST_TO_SAS_HA(shost) = sha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rc = pm8001_prep_sas_ha_init(shost, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* ent->driver variable is used to differentiate between controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (!pm8001_ha) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "chip_init failed [ret: %d]\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) goto err_out_ha_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto err_out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rc = scsi_add_host(shost, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) goto err_out_ha_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (pm8001_ha->chip_id != chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) for (i = 1; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* setup thermal configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pm80xx_set_thermal_config(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pm8001_init_sas_add(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* phy setting support for motherboard controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) rc = pm8001_configure_phy_settings(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto err_out_shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pm8001_post_sas_ha_init(shost, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "sas_register_ha failed [ret: %d]\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto err_out_shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) list_add_tail(&pm8001_ha->list, &hba_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pm8001_ha->flags = PM8001F_RUN_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) scsi_scan_host(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) err_out_shost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) scsi_remove_host(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) err_out_ha_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pm8001_free(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) err_out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) kfree(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) err_out_free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) err_out_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) err_out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) err_out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * pm8001_init_ccb_tag - allocate memory to CCB and tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * @shost: scsi host which has been allocated outside.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u32 max_out_io, ccb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Update to the scsi host*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) can_queue = ccb_count - PM8001_RESERVE_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) shost->can_queue = can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!pm8001_ha->tags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Memory region for ccb_info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pm8001_ha->ccb_info = (struct pm8001_ccb_info *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!pm8001_ha->ccb_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "Unable to allocate memory for ccb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) goto err_out_noccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) for (i = 0; i < ccb_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) &pm8001_ha->ccb_info[i].ccb_dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!pm8001_ha->ccb_info[i].buf_prd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "pm80xx: ccb prd memory allocation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pm8001_ha->ccb_info[i].task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pm8001_ha->ccb_info[i].device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ++pm8001_ha->tags_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) err_out_noccb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) kfree(pm8001_ha->devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static void pm8001_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct sas_ha_struct *sha = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sas_unregister_ha(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sas_remove_host(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) list_del(&pm8001_ha->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) for (i = 0; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) synchronize_irq(pci_irq_vector(pdev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) for (i = 0; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) free_irq(pm8001_ha->irq, sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* For non-msix and msix interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if ((!pdev->msix_cap || !pci_msi_enabled()) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) (pm8001_ha->chip_id == chip_8001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) tasklet_kill(&pm8001_ha->tasklet[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) tasklet_kill(&pm8001_ha->tasklet[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) scsi_host_put(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) pm8001_free(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) kfree(sha->sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) kfree(sha->sas_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) kfree(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * pm8001_pci_suspend - power management suspend main entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * @pdev: PCI device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * @state: PM state change to (usually PCI_D3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * Returns 0 success, anything else error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct sas_ha_struct *sha = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u32 device_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) sas_suspend_ha(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) flush_workqueue(pm8001_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) scsi_block_requests(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (!pdev->pm_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(&pdev->dev, " PCI PM not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) for (i = 0; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) synchronize_irq(pci_irq_vector(pdev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for (i = 0; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) free_irq(pm8001_ha->irq, sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* For non-msix and msix interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if ((!pdev->msix_cap || !pci_msi_enabled()) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) (pm8001_ha->chip_id == chip_8001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) tasklet_kill(&pm8001_ha->tasklet[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) tasklet_kill(&pm8001_ha->tasklet[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) device_state = pci_choose_state(pdev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) pm8001_printk("pdev=0x%p, slot=%s, entering "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "operating state [D%d]\n", pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pm8001_ha->name, device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) pci_set_power_state(pdev, device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * pm8001_pci_resume - power management resume main entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * @pdev: PCI device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Returns 0 success, anything else error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int pm8001_pci_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct sas_ha_struct *sha = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct pm8001_hba_info *pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) u8 i = 0, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u32 device_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) DECLARE_COMPLETION_ONSTACK(completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) device_state = pdev->current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pci_enable_wake(pdev, PCI_D0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pm8001_printk("slot=%s Enable device failed during resume\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pm8001_ha->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) goto err_out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) rc = pci_go_44(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) sas_prep_resume_ha(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* chip soft rst only for spc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (pm8001_ha->chip_id == chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* disable all the interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) rc = pm8001_request_irq(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #ifdef PM8001_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Tasklet for non msi-x interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if ((!pdev->msix_cap || !pci_msi_enabled()) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) (pm8001_ha->chip_id == chip_8001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) (unsigned long)&(pm8001_ha->irq_vector[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) (unsigned long)&(pm8001_ha->irq_vector[j]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (pm8001_ha->chip_id != chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) for (i = 1; i < pm8001_ha->number_of_intr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* Chip documentation for the 8070 and 8072 SPCv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* states that a 500ms minimum delay is required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* before issuing commands. Otherwise, the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* will enter an unrecoverable state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (pm8001_ha->chip_id == chip_8070 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pm8001_ha->chip_id == chip_8072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) mdelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Spin up the PHYs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pm8001_ha->flags = PM8001F_RUN_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) pm8001_ha->phy[i].enable_completion = &completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) wait_for_completion(&completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) sas_resume_ha(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) err_out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) scsi_remove_host(pm8001_ha->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) err_out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* update of pci device, vendor id and driver data with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * unique value for each of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static struct pci_device_id pm8001_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Support for SPC/SPCv/SPCve controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) { PCI_VENDOR_ID_ATTO, 0x8070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) { PCI_VENDOR_ID_ATTO, 0x8070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { PCI_VENDOR_ID_ATTO, 0x8072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) { PCI_VENDOR_ID_ATTO, 0x8072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) { PCI_VENDOR_ID_ATTO, 0x8070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) { PCI_VENDOR_ID_ATTO, 0x8072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { PCI_VENDOR_ID_ATTO, 0x8072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {} /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static struct pci_driver pm8001_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .id_table = pm8001_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .probe = pm8001_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .remove = pm8001_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .suspend = pm8001_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .resume = pm8001_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * pm8001_init - initialize scsi transport template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static int __init pm8001_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!pm8001_wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pm8001_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (!pm8001_stt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto err_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) rc = pci_register_driver(&pm8001_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) goto err_tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) err_tp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) sas_release_transport(pm8001_stt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) err_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) destroy_workqueue(pm8001_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static void __exit pm8001_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) pci_unregister_driver(&pm8001_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) sas_release_transport(pm8001_stt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) destroy_workqueue(pm8001_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) module_init(pm8001_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) module_exit(pm8001_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) MODULE_DESCRIPTION(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) "SAS/SATA controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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