^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 USI Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifndef _PMC8001_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define _PMC8001_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <scsi/libsas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* for Request Opcode of IOMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OPC_INB_ECHO 1 /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OPC_INB_PHYSTART 4 /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OPC_INB_PHYSTOP 5 /* 0x005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OPC_INB_SSP_ABORT 15 /* 0x00F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SMP_RESPONSE is removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OPC_INB_SMP_ABORT 20 /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OPC_INB_REG_DEV 22 /* 0x016 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OPC_INB_SATA_ABORT 24 /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OPC_INB_GPIO 34 /* 0x022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* for Response Opcode of IOMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OPC_OUB_ECHO 1 /* 0x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OPC_OUB_HW_EVENT 4 /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OPC_OUB_SSP_COMP 5 /* 0x005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OPC_OUB_SMP_COMP 6 /* 0x006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OPC_OUB_DEV_REGIST 10 /* 0x00A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OPC_OUB_SATA_COMP 13 /* 0x00D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* SMP_RECEIVED Notification is removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OPC_OUB_DEV_INFO 19 /* 0x013 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* for phy start*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPINHOLD_DISABLE (0x00 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPINHOLD_ENABLE (0x01 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LINKMODE_SAS (0x01 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LINKMODE_DSATA (0x02 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LINKMODE_AUTO (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LINKRATE_15 (0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LINKRATE_30 (0x02 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LINKRATE_60 (0x04 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* for new SPC controllers MEMBASE III is shared between BIOS and DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GSM_SM_BASE 0x4F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mpi_msg_hdr{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __le32 header; /* Bits [11:0] - Message operation code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Bits [15:12] - Message Category */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Bits [21:16] - Outboundqueue ID for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) operation completion message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Bits [23:22] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Bits [28:24] - Buffer Count, indicates how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) many buffer are allocated for the massage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Bits [30:29] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Bits [31] - Message Valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * brief the data structure of PHY Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * use to describe enable the phy (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct phy_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __le32 ase_sh_lm_slr_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct sas_identify_frame sas_identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * brief the data structure of PHY Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * use to disable the phy (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct phy_stop_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __le32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* set device bits fis - device to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct set_dev_bits_fis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 fis_type; /* 0xA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 n_i_pmport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* b7 : n Bit. Notification bit. If set device needs attention. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* b6 : i Bit. Interrupt Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* b5-b4: reserved2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* b3-b0: PM Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* PIO setup FIS - device to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct pio_setup_fis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 fis_type; /* 0x5f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 i_d_pmPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* b7 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* b6 : i bit. Interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* b5 : d bit. data transfer direction. set to 1 for device to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* b4 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* b3-b0: PM Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 lbal_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 lbam_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 lbah_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 sector_count_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 _r_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 e_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 _r_c[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 transfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * brief the data structure of SATA Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * use to describe the sata task response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct sata_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 sata_resp[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * brief the data structure of SAS HW Event Notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * use to alert the host about the hardware event(64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct hw_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le32 lr_evt_status_phyid_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __le32 evt_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __le32 npip_portstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct sas_identify_frame sas_identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dev_to_host_fis sata_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * brief the data structure of REGISTER DEVICE Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * use to describe MPI REGISTER DEVICE Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct reg_dev_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __le32 phyid_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __le32 dtype_dlr_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __le32 firstburstsize_ITNexustimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __le32 upper_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * brief the data structure of DEREGISTER DEVICE Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * use to request spc to remove all internal resources associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * with the device id (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct dereg_dev_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * brief the data structure of DEVICE_REGISTRATION Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * use to notify the completion of the device registration (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct dev_reg_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * brief the data structure of Local PHY Control Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * use to issue PHY CONTROL to local phy (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct local_phy_ctl_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le32 phyop_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 reserved1[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * brief the data structure of Local Phy Control Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * use to describe MPI Local Phy Control Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct local_phy_ctl_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __le32 phyop_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OP_BITS 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ID_BITS 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * brief the data structure of PORT Control Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * use to control port properties (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct port_ctl_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __le32 portop_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __le32 param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __le32 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 reserved1[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * brief the data structure of HW Event Ack Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * use to acknowledge receive HW event (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct hw_event_ack_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __le32 sea_phyid_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __le32 param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __le32 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 reserved1[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * brief the data structure of SSP Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * use to indicate a SSP Completion (n bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct ssp_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __le32 ssptag_rescv_rescpad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ssp_response_iu ssp_resp_iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __le32 residual_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SSP_RESCV_BIT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * brief the data structure of SATA EVNET esponse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * use to indicate a SATA Completion (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct sata_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __le32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __le32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * brief the data structure of SSP EVNET esponse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * use to indicate a SSP Completion (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ssp_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __le32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __le32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * brief the data structure of General Event Notification Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * use to describe MPI General Event Notification Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct general_event_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __le32 inb_IOMB_payload[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define GENERAL_EVENT_PAYLOAD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OPCODE_BITS 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * brief the data structure of SMP Request Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * use to describe MPI SMP REQUEST Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct smp_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __le32 len_ip_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Bits [0] - Indirect response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Bits [1] - Indirect Payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Bits [15:2] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Bits [23:16] - direct payload Len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Bits [31:24] - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 smp_req16[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 smp_req[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __le64 long_req_addr;/* sg dma address, LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __le32 long_req_size;/* LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 _r_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) __le64 long_resp_addr;/* sg dma address, LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __le32 long_resp_size;/* LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 _r_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } long_smp_req;/* sequencer extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * brief the data structure of SMP Completion Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * use to describe MPI SMP Completion Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct smp_completion_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __le32 _r_a[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *brief the data structure of SSP SMP SATA Abort Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct task_abort_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __le32 tag_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __le32 abort_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* These flags used for SSP SMP & SATA Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ABORT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define ABORT_SINGLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define ABORT_ALL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * brief the data structure of SSP SATA SMP Abort Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct task_abort_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __le32 scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * brief the data structure of SAS Diagnostic Start/End Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct sas_diag_start_end_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __le32 operation_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * brief the data structure of SAS Diagnostic Execute Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct sas_diag_execute_req{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) __le32 cmdtype_cmddesc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __le32 pat1_pat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __le32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) __le32 codepat_errmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __le32 pmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __le32 pERF1CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SAS_DIAG_PARAM_BYTES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * brief the data structure of Set Device State Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * use to describe MPI Set Device State Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct set_dev_state_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __le32 nds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * brief the data structure of sas_re_initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct sas_re_initialization_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __le32 SSAHOLT;/* bit29-set max port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ** bit28-set open reject cmd retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ** bit27-set open reject data retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ** bit26-set open reject option, remap:1 or not:0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ** bit25-set sata head of line time out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) __le32 reserved_maxPorts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * data retries: bit15-bit0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le32 sata_hol_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 reserved1[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * brief the data structure of SATA Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * use to describe MPI SATA IO Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct sata_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __le32 ncqtag_atap_dir_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct host_to_dev_fis sata_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __le32 esgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * brief the data structure of SSP INI TM Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * use to describe MPI SSP INI TM Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ssp_ini_tm_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) __le32 relate_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __le32 tmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 lun[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __le32 ds_ads_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct ssp_info_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 lun[8];/* SCSI Logical Unit Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u8 reserved1;/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 efb_prio_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* B7 : enabledFirstBurst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* B6-3 : taskPriority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* B2-0 : taskAttribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 reserved2; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 additional_cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* B7-2 : additional_cdb_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* B1-0 : reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * brief the data structure of SSP INI IO Start Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * use to describe MPI SSP INI IO Start Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct ssp_ini_io_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __le32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __le32 dir_m_tlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct ssp_info_unit ssp_iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __le32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __le32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __le32 esgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * brief the data structure of Firmware download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * use to describe MPI FW DOWNLOAD Command (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct fw_flash_Update_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __le32 cur_image_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __le32 cur_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) __le32 total_image_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 reserved0[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __le32 sgl_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) __le32 sgl_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) __le32 ext_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define FWFLASH_IOMB_RESERVED_LEN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * brief the data structure of FW_FLASH_UPDATE Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct fw_flash_Update_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * brief the data structure of Get NVM Data Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * use to get data from NVM in HBA(64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct get_nvm_data_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __le32 len_ir_vpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) __le32 vpd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __le32 resp_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __le32 resp_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __le32 resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct set_nvm_data_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __le32 len_ir_vpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __le32 vpd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __le32 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __le32 resp_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __le32 resp_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __le32 resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define TWI_DEVICE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define C_SEEPROM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define VPD_FLASH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define AAP1_RDUMP 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define IOP_RDUMP 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define EXPAN_ROM 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define IPMode 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define NVMD_TYPE 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define NVMD_STAT 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define NVMD_LEN 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * brief the data structure of Get NVMD Data Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * use to describe MPI Get NVMD Data Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct get_nvm_data_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __le32 ir_tda_bn_dps_das_nvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) __le32 dlen_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __le32 nvm_data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * brief the data structure of SAS Diagnostic Start/End Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct sas_diag_start_end_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * brief the data structure of SAS Diagnostic Execute Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct sas_diag_execute_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) __le32 cmdtype_cmddesc_phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __le32 Status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __le32 ReportData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * brief the data structure of Set Device State Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * use to describe MPI Set Device State Response (64 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct set_dev_state_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) __le32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) __le32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __le32 pds_nds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } __attribute__((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define NDS_BITS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PDS_BITS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * HW Events type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define HW_EVENT_RESET_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define HW_EVENT_PHY_STOP_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define HW_EVENT_SAS_PHY_UP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define HW_EVENT_SATA_PHY_UP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define HW_EVENT_SATA_SPINUP_HOLD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define HW_EVENT_PHY_DOWN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define HW_EVENT_PORT_INVALID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define HW_EVENT_BROADCAST_CHANGE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define HW_EVENT_PHY_ERROR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define HW_EVENT_BROADCAST_SES 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define HW_EVENT_MALFUNCTION 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define HW_EVENT_BROADCAST_EXP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define HW_EVENT_PHY_START_STATUS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define HW_EVENT_PORT_RECOVER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define HW_EVENT_PORT_RESET_COMPLETE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define PORT_NOT_ESTABLISHED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define PORT_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define PORT_LOSTCOMM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define PORT_IN_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define PORT_INVALID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * SSP/SMP/SATA IO Completion Status values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define IO_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define IO_ABORTED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define IO_OVERFLOW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define IO_UNDERFLOW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define IO_FAILED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define IO_ABORT_RESET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define IO_NOT_VALID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define IO_NO_DEVICE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define IO_ILLEGAL_PARAMETER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define IO_LINK_FAILURE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define IO_PROG_ERROR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define IO_EDC_IN_ERROR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define IO_EDC_OUT_ERROR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define IO_ERROR_HW_TIMEOUT 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define IO_XFER_ERROR_BREAK 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define IO_OPEN_CNX_ERROR_BREAK 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define IO_XFER_ERROR_NAK_RECEIVED 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define IO_XFER_ERROR_PEER_ABORTED 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define IO_XFER_ERROR_RX_FRAME 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define IO_XFER_ERROR_DMA 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define IO_XFER_ERROR_SATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define IO_XFER_CMD_FRAME_ISSUED 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define IO_PORT_IN_RESET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define IO_DS_NON_OPERATIONAL 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define IO_DS_IN_RECOVERY 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define IO_TM_TAG_NOT_FOUND 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define IO_XFER_PIO_SETUP_ERROR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define IO_DS_IN_ERROR 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define IO_ABORT_IN_PROGRESS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define IO_ABORT_DELAYED 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define IO_INVALID_LENGTH 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* WARNING: This error code must always be the last number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * If you add error code, modify this code also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * It is used as an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define IO_ERROR_UNKNOWN_GENERIC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* MSGU CONFIGURATION TABLE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MSGU_IBDB_SET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define MSGU_HOST_INT_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define MSGU_HOST_INT_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define MSGU_IOPIB_INT_STATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define MSGU_IOPIB_INT_MASK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define MSGU_MSGU_CONTROL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define MSGU_ODR 0x3C/* RevB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MSGU_ODCR 0x40/* RevB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MSGU_SCRATCH_PAD_0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MSGU_SCRATCH_PAD_1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define MSGU_SCRATCH_PAD_2 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define MSGU_SCRATCH_PAD_3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define MSGU_HOST_SCRATCH_PAD_0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MSGU_HOST_SCRATCH_PAD_1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MSGU_HOST_SCRATCH_PAD_2 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MSGU_HOST_SCRATCH_PAD_3 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MSGU_HOST_SCRATCH_PAD_4 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MSGU_HOST_SCRATCH_PAD_5 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MSGU_HOST_SCRATCH_PAD_6 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MSGU_HOST_SCRATCH_PAD_7 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define MSGU_ODMR 0x74/* RevB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* bit definition for ODMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define ODMR_CLEAR_ALL 0/* clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* bit definition for ODCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) interrupt vector*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* MSIX Interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define MSIX_TABLE_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define MSIX_TABLE_ELEMENT_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define MSIX_INTERRUPT_DISABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MSIX_INTERRUPT_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* state definition for Scratch Pad1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define SCRATCH_PAD1_ERR 0x02 /* error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define SCRATCH_PAD1_RDY 0x03 /* ready state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) Reserved bit 3 to 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* state definition for Scratch Pad2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SCRATCH_PAD2_POR 0x00 /* power on state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define SCRATCH_PAD2_ERR 0x02 /* error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define SCRATCH_PAD2_RDY 0x03 /* ready state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) Mask, bit1-0 State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) Reserved bit 2 to 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* main configuration offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Gereral Status Table offset - byte offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define GST_GSTLEN_MPIS_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define GST_MSGUTCNT_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define GST_IOPTCNT_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define GST_PHYSTATE_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define GST_PHYSTATE0_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define GST_PHYSTATE1_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define GST_PHYSTATE2_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define GST_PHYSTATE3_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define GST_PHYSTATE4_OFFSET 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define GST_PHYSTATE5_OFFSET 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define GST_PHYSTATE6_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define GST_PHYSTATE7_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define GST_RERRINFO_OFFSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* General Status Table - MPI state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define GST_MPI_STATE_UNINIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define GST_MPI_STATE_INIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define GST_MPI_STATE_TERMINATION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define GST_MPI_STATE_ERROR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define GST_MPI_STATE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define PCIE_EVENT_INTERRUPT 0x003044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define PCIE_ERROR_INTERRUPT 0x00304C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* signature definition for host scratch pad0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Signature for Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SPC_REG_RESET 0x000000/* reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* bit difination for SPC_RESET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SPC_REG_RESET_OSSP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define SPC_REG_RESET_RAAE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SPC_REG_RESET_PCS_SPBC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SPC_REG_RESET_PCS_LM 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SPC_REG_RESET_PCS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define SPC_REG_RESET_GSM 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define SPC_REG_RESET_DDR2 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define SPC_REG_RESET_BDMA_CORE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define SPC_REG_RESET_PCIE_PWR 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define SPC_REG_RESET_PCIE_SFT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define SPC_REG_RESET_PCS_SXCBI 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define SPC_REG_RESET_LMS_SXCBI 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define SPC_REG_RESET_PMIC_CORE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define SPC_REG_RESET_DEVICE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define MBIC_AAP1_ADDR_BASE 0x060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define MBIC_IOP_ADDR_BASE 0x070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define GSM_ADDR_BASE 0x0700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Dynamic map through Bar4 - 0x00700000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define GSM_CONFIG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define RAM_ECC_DB_ERR 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define RB6_ACCESS_REG 0x6A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define HDAC_EXEC_CMD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define HDA_C_PA 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define HDA_SEQ_ID_BITS 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define MBIC_AAP1_ADDR_BASE 0x060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define MBIC_IOP_ADDR_BASE 0x070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define GSM_ADDR_BASE 0x0700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define GSM_CONFIG_RESET_VALUE 0x00003b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define GPIO_ADDR_BASE 0x00090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* RB6 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define SPC_RB6_OFFSET 0x80C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Magic number of soft reset for RB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define RB6_MAGIC_NUMBER_RST 0x1234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Device Register status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define DEVREG_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define GSM_BASE 0x4F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define SHIFT_REG_64K_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define SHIFT_REG_BIT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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