^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 USI Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "pm8001_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "pm8001_hwi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "pm8001_chips.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "pm8001_ctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * read_main_config_table - read the configure table and save it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pm8001_mr32(address, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pm8001_mr32(address, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pm8001_mr32(address, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pm8001_mr32(address, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pm8001_mr32(address, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pm8001_mr32(address, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pm8001_mr32(address, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pm8001_mr32(address, MAIN_IBQ_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pm8001_mr32(address, MAIN_OBQ_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* read analog Setting offset from the configuration table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* read Error Dump Offset and Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * read_general_status_table - read the general status table and save it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *address = pm8001_ha->general_stat_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pm8001_mr32(address, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pm8001_mr32(address, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pm8001_mr32(address, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pm8001_mr32(address, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pm8001_mr32(address, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pm8001_mr32(address, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pm8001_mr32(address, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pm8001_mr32(address, 0x1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm8001_mr32(address, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pm8001_mr32(address, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pm8001_mr32(address, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pm8001_mr32(address, 0x2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pm8001_mr32(address, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pm8001_mr32(address, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pm8001_mr32(address, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pm8001_mr32(address, 0x3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pm8001_mr32(address, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pm8001_mr32(address, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pm8001_mr32(address, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pm8001_mr32(address, 0x4C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pm8001_mr32(address, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pm8001_mr32(address, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pm8001_mr32(address, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pm8001_mr32(address, 0x5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pm8001_mr32(address, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * read_inbnd_queue_table - read the inbound queue table and save it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 offset = i * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pm8001_ha->inbnd_q_tbl[i].pi_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pm8001_mr32(address, (offset + 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * read_outbnd_queue_table - read the outbound queue table and save it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 offset = i * 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pm8001_ha->outbnd_q_tbl[i].ci_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pm8001_mr32(address, (offset + 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * init_default_table_values - init the default table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 offsetib, offsetob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 ib_offset = pm8001_ha->ib_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 ob_offset = pm8001_ha->ob_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 ci_offset = pm8001_ha->ci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 pi_offset = pm8001_ha->pi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PM8001_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for (i = 0; i < pm8001_ha->max_q_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pm8001_ha->inbnd_q_tbl[i].base_virt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pm8001_ha->inbnd_q_tbl[i].total_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pm8001_ha->memoryMap.region[ib_offset + i].total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pm8001_ha->inbnd_q_tbl[i].ci_virt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) offsetib = i * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) get_pci_bar_index(pm8001_mr32(addressib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (offsetib + 0x14)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pm8001_ha->inbnd_q_tbl[i].pi_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pm8001_mr32(addressib, (offsetib + 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < pm8001_ha->max_q_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pm8001_ha->outbnd_q_tbl[i].base_virt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pm8001_ha->outbnd_q_tbl[i].total_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pm8001_ha->memoryMap.region[ob_offset + i].total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0 | (10 << 16) | (i << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pm8001_ha->outbnd_q_tbl[i].pi_virt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) offsetob = i * 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) get_pci_bar_index(pm8001_mr32(addressob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) offsetob + 0x14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pm8001_ha->outbnd_q_tbl[i].ci_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pm8001_mr32(addressob, (offsetob + 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * update_main_config_table - update the main default table to the HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pm8001_mw32(address, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pm8001_mw32(address, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pm8001_mw32(address, 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pm8001_mw32(address, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pm8001_mw32(address, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pm8001_mw32(address, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) outbound_tgt_ITNexus_event_pid0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pm8001_mw32(address, 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) outbound_tgt_ITNexus_event_pid4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pm8001_mw32(address, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outbound_tgt_ssp_event_pid0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pm8001_mw32(address, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) outbound_tgt_ssp_event_pid4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pm8001_mw32(address, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) outbound_tgt_smp_event_pid0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pm8001_mw32(address, 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pm8001_ha->main_cfg_tbl.pm8001_tbl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) outbound_tgt_smp_event_pid4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pm8001_mw32(address, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pm8001_mw32(address, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pm8001_mw32(address, 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pm8001_mw32(address, 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pm8001_mw32(address, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pm8001_mw32(address, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pm8001_mw32(address, 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pm8001_mw32(address, 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pm8001_mw32(address, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * update_inbnd_queue_table - update the inbound queue table to the HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @number: entry in the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 offset = number * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm8001_mw32(address, offset + 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pm8001_mw32(address, offset + 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pm8001_mw32(address, offset + 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pm8001_mw32(address, offset + 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pm8001_mw32(address, offset + 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * update_outbnd_queue_table - update the outbound queue table to the HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @number: entry in the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 offset = number * 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pm8001_mw32(address, offset + 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pm8001_mw32(address, offset + 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pm8001_mw32(address, offset + 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pm8001_mw32(address, offset + 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pm8001_mw32(address, offset + 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pm8001_mw32(address, offset + 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * pm8001_bar4_shift - function is called to shift BAR base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @pm8001_ha : our hba card infomation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @shiftValue : shifting value in memory bar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 regVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* program the inbound AXI translation Lower Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* confirm the setting is written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) start = jiffies + HZ; /* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } while ((regVal != shiftValue) && time_before(jiffies, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (regVal != shiftValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * mpi_set_phys_g3_with_ssc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 SSCbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 value, offset, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PHY_G3_WITH_SSC_BIT_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SNW3_PHY_CAPABILITIES_PARITY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (-1 == pm8001_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (-1 == pm8001_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) for (i = 4; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) Change the SSC upspreading value to 0x0 so that upspreading is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) Device MABC SMOD0 Controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) Address: (via MEMBASE-III):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) Using shifted destination address 0x0_0000: with Offset 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 31:28 R/W Reserved Do not change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 27:24 R/W SAS_SMOD_SPRDUP 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 23:20 R/W SAS_SMOD_SPRDDN 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 19:0 R/W Reserved Do not change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) Upon power-up this register will read as 0x8990c016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) so that the written value will be 0x8090c016.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) This will ensure only down-spreading SSC is enabled on the SPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) value = pm8001_cr32(pm8001_ha, 2, 0xd8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*set the shifted destination address to 0x0 to avoid error operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pm8001_bar4_shift(pm8001_ha, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * mpi_set_open_retry_interval_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (-1 == pm8001_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pm8001_cw32(pm8001_ha, 2, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (-1 == pm8001_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i = 4; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pm8001_cw32(pm8001_ha, 2, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*set the shifted destination address to 0x0 to avoid error operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pm8001_bar4_shift(pm8001_ha, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * mpi_init_check - check firmware initialization status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 max_wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 gst_len_mpistate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) table is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* wait until Inbound DoorBell Clear Register toggled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) max_wait_count = 1 * 1000 * 1000;/* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) value &= SPC_MSGU_CFG_TABLE_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } while ((value != 0) && (--max_wait_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!max_wait_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* check the MPI-State for initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) gst_len_mpistate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GST_GSTLEN_MPIS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* check MPI Initialization error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) gst_len_mpistate = gst_len_mpistate >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (0x0000 != gst_len_mpistate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 value, value1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 max_wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* check error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* check AAP error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* check IOP error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* bit 4-31 of scratch pad1 should be zeros if it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) in error state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (value & SCRATCH_PAD1_STATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* error case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) in error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (value1 & SCRATCH_PAD2_STATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* error case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* wait until scratch pad 1 and 2 registers in ready state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) & SCRATCH_PAD1_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) & SCRATCH_PAD2_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if ((--max_wait_count) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 pcibar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 pcilogic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) value = pm8001_cr32(pm8001_ha, 0, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) offset = value & 0x03FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pcilogic = (value & 0xFC000000) >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pcibar = get_pci_bar_index(pcilogic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pm8001_ha->main_cfg_tbl_addr = base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pm8001_ha->general_stat_tbl_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pm8001_ha->inbnd_q_tbl_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pm8001_ha->outbnd_q_tbl_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u16 deviceid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* 8081 controllers need BAR shift to access MPI space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * as this is shared with BIOS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (deviceid == 0x8081 || deviceid == 0x0042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GSM_SM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* check the firmware status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (-1 == check_fw_ready(pm8001_ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Initialize pci space address eg: mpi offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) init_pci_device_addresses(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) init_default_table_values(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) read_main_config_table(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) read_general_status_table(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) read_inbnd_queue_table(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) read_outbnd_queue_table(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* update main config table ,inbound table and outbound table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) update_main_config_table(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) for (i = 0; i < pm8001_ha->max_q_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) update_inbnd_queue_table(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < pm8001_ha->max_q_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) update_outbnd_queue_table(pm8001_ha, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* 8081 controller donot require these operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (deviceid != 0x8081 && deviceid != 0x0042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* 7->130ms, 34->500ms, 119->1.5s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mpi_set_open_retry_interval_reg(pm8001_ha, 119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* notify firmware update finished and check initialization status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (0 == mpi_init_check(pm8001_ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*This register is a 16-bit timer with a resolution of 1us. This is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) timer used for interrupt delay/coalescing in the PCIe Application Layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) Zero is not a valid value. A value of 1 in the register will cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) interrupts to be normal. A value greater than 1 will cause coalescing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) delays.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 max_wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 gst_len_mpistate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u16 deviceid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (deviceid == 0x8081 || deviceid == 0x0042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GSM_SM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) init_pci_device_addresses(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) table is stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* wait until Inbound DoorBell Clear Register toggled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) max_wait_count = 1 * 1000 * 1000;/* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) value &= SPC_MSGU_CFG_TABLE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) } while ((value != 0) && (--max_wait_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!max_wait_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* check the MPI-State for termination in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* wait until Inbound DoorBell Clear Register toggled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) max_wait_count = 1 * 1000 * 1000; /* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) gst_len_mpistate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GST_GSTLEN_MPIS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (GST_MPI_STATE_UNINIT ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (gst_len_mpistate & GST_MPI_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } while (--max_wait_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!max_wait_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gst_len_mpistate & GST_MPI_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * soft_reset_ready_check - Function to check FW is ready for soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 regVal, regVal1, regVal2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (mpi_uninit_check(pm8001_ha) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* read the scratch pad 2 register bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) & SCRATCH_PAD2_FWRDY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (regVal == SCRATCH_PAD2_FWRDY_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Trigger NMI twice via RB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) RB6_ACCESS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RB6_MAGIC_NUMBER_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* wait for 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) SCRATCH_PAD2_FWRDY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (regVal != SCRATCH_PAD2_FWRDY_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regVal1, regVal2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "SCRATCH_PAD0 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "SCRATCH_PAD3 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * the FW register status to the originated status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 regVal, toggleVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 max_wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 regVal1, regVal2, regVal3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 signature = 0x252acbcd; /* for host scratch pad0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* step1: Check FW is ready for soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (soft_reset_ready_check(pm8001_ha) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* step 2: clear NMI status register on AAP1 and IOP, write the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) value to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* map 0x60000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MBIC_AAP1_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* map 0x70000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MBIC_IOP_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* read the scratch pad 1 register bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) & SCRATCH_PAD1_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) toggleVal = regVal ^ SCRATCH_PAD1_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* set signature in host scratch pad0 register to tell SPC that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) host performs the soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* read required registers for confirmming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* map 0x0700000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) GSM_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* step 3: host read GSM Configuration and Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Put those bits to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* GSM XCBI offset = 0x70 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) 0x00 Bit 13 COM_SLV_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) 0x00 Bit 12 QSSP_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 0x00 Bit 11 RAAE_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) 0x00 Bit 9 RB_1_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) 0x00 Bit 8 SM_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) regVal &= ~(0x00003b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* host write GSM Configuration and Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* step 4: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* disable GSM - Read Address Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) regVal1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* disable GSM - Write Address Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) regVal2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* disable GSM - Write Data Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) regVal3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* step 5: delay 10 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* step 5-b: set GPIO-0 output control to tristate anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GPIO_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* set GPIO-0 output control to tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) regVal &= 0xFFFFFFFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Step 6: Reset the IOP and AAP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* map 0x00000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SPC_TOP_LEVEL_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* step 7: Reset the BDMA/OSSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* step 8: delay 10 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* step 9: bring the BDMA and OSSP out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* step 10: delay 10 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* step 11: reads and sets the GSM Configuration and Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* map 0x0700000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GSM_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Put those bits to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* GSM XCBI offset = 0x70 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) 0x00 Bit 13 COM_SLV_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) 0x00 Bit 12 QSSP_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) 0x00 Bit 11 RAAE_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) 0x00 Bit 9 RB_1_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) 0x00 Bit 8 SM_SW_RSTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) regVal |= (GSM_CONFIG_RESET_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* step 12: Restore GSM - Read Address Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* just for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Restore GSM - Write Address Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Restore GSM - Write Data Parity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "GSM 0x700048 - Write Data Parity Check Enableis set to = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* step 13: bring the IOP and AAP1 out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* map 0x00000 to BAR4(0x20), BAR2(win) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) SPC_TOP_LEVEL_ADDR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* step 14: delay 10 usec - Normal Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* check Soft Reset Normal mode or Soft Reset HDA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (signature == SPC_SOFT_RESET_SIGNATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* step 15 (Normal Mode): wait until scratch pad1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bit 2 toggled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) max_wait_count = 2 * 1000 * 1000;/* 2 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SCRATCH_PAD1_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) } while ((regVal != toggleVal) && (--max_wait_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!max_wait_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) regVal = pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MSGU_SCRATCH_PAD_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) toggleVal, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "SCRATCH_PAD0 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) MSGU_SCRATCH_PAD_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "SCRATCH_PAD2 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) MSGU_SCRATCH_PAD_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "SCRATCH_PAD3 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MSGU_SCRATCH_PAD_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* step 16 (Normal) - Clear ODMR and ODCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* step 17 (Normal Mode): wait for the FW and IOP to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ready - 1 sec timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Wait for the SPC Configuration Table to be ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (check_fw_ready(pm8001_ha) == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* return error if MPI Configuration Table not ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "FW not ready SCRATCH_PAD1 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* return error if MPI Configuration Table not ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "FW not ready SCRATCH_PAD2 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "SCRATCH_PAD0 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) MSGU_SCRATCH_PAD_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pm8001_dbg(pm8001_ha, INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "SCRATCH_PAD3 value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pm8001_cr32(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) MSGU_SCRATCH_PAD_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pm8001_bar4_shift(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) u32 regVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* do SPC chip reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) regVal &= ~(SPC_REG_RESET_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* delay 10 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* bring chip reset out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) regVal |= SPC_REG_RESET_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* delay 10 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* wait for 20 msec until the firmware gets reloaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) i = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) } while ((--i) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * pm8001_chip_iounmap - which maped when initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) s8 bar, logical = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ** logical BARs for SPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ** bar 0 and 1 - logical BAR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ** bar 2 and 3 - logical BAR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ** bar4 - logical BAR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ** bar5 - logical BAR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ** Skip the appropriate assignments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if ((bar == 1) || (bar == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (pm8001_ha->io_mem[logical].memvirtaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) logical++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #ifndef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * @int_vec_idx: interrupt number to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u32 int_vec_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u32 msi_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) msi_index += MSIX_TABLE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) value = (1 << int_vec_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * @int_vec_idx: interrupt number to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u32 int_vec_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) u32 msi_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) msi_index += MSIX_TABLE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * @vec: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) pm8001_chip_intx_interrupt_enable(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * @vec: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) pm8001_chip_intx_interrupt_disable(pm8001_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * pm8001_mpi_msg_free_get - get the free message buffer for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * inbound queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * @circularQ: the inbound queue we want to transfer to HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * @messageSize: the message size of this transfer, normally it is 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * @messagePtr: the pointer to message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u16 messageSize, void **messagePtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u32 offset, consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct mpi_msg_hdr *msgHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u8 bcCount = 1; /* only support single buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Checks is the requested message size can be allocated in this queue*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (messageSize > IOMB_SIZE_SPCV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) *messagePtr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Stores the new consumer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) consumer_index = pm8001_read_32(circularQ->ci_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) circularQ->consumer_index = cpu_to_le32(consumer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) le32_to_cpu(circularQ->consumer_index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) *messagePtr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* get memory IOMB buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) offset = circularQ->producer_idx * messageSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* increment to next bcCount element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) circularQ->producer_idx = (circularQ->producer_idx + bcCount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) % PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* Adds that distance to the base of the region virtual address plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) the message header size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * FW to tell the fw to get this message from IOMB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * @circularQ: the inbound queue we want to transfer to HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * @opCode: the operation code represents commands which LLDD and fw recognized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * @payload: the command payload of each operation command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * @nb: size in bytes of the command payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * @responseQueue: queue to interrupt on w/ command response (if any)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct inbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u32 opCode, void *payload, size_t nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) u32 responseQueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) void *pMessage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int rv = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (WARN_ON(q_index >= pm8001_ha->max_q_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) spin_lock_irqsave(&circularQ->iq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &pMessage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) rv = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) memcpy(pMessage, payload, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) memset(pMessage + nb, 0, pm8001_ha->iomb_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) (nb + sizeof(struct mpi_msg_hdr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*Build the header*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) | ((responseQueue & 0x3F) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) | ((category & 0xF) << 12) | (opCode & 0xFFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*Update the PI to the firmware*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) circularQ->pi_offset, circularQ->producer_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) responseQueue, opCode, circularQ->producer_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) circularQ->consumer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) spin_unlock_irqrestore(&circularQ->iq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct outbound_queue_table *circularQ, u8 bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) u32 producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct mpi_msg_hdr *msgHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct mpi_msg_hdr *pOutBoundMsgHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) circularQ->consumer_idx * pm8001_ha->iomb_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (pOutBoundMsgHeader != msgHeader) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) "consumer_idx = %d msgHeader = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) circularQ->consumer_idx, msgHeader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* Update the producer index from SPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) producer_index = pm8001_read_32(circularQ->pi_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) circularQ->producer_index = cpu_to_le32(producer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) circularQ->consumer_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) circularQ->producer_index, msgHeader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* free the circular queue buffer elements associated with the message*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) circularQ->consumer_idx = (circularQ->consumer_idx + bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) % PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* update the CI of outbound queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) circularQ->consumer_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Update the producer index from SPC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) producer_index = pm8001_read_32(circularQ->pi_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) circularQ->producer_index = cpu_to_le32(producer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) circularQ->consumer_idx, circularQ->producer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * pm8001_mpi_msg_consume- get the MPI message from outbound queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * message table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * @circularQ: the outbound queue table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * @messagePtr1: the message contents of this outbound message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * @pBC: the message size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct outbound_queue_table *circularQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) void **messagePtr1, u8 *pBC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct mpi_msg_hdr *msgHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) __le32 msgHeader_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 header_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* If there are not-yet-delivered messages ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (le32_to_cpu(circularQ->producer_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) != circularQ->consumer_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /*Get the pointer to the circular queue buffer element*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) msgHeader = (struct mpi_msg_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) (circularQ->base_virt +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) circularQ->consumer_idx * pm8001_ha->iomb_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* read header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) header_tmp = pm8001_read_32(msgHeader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) msgHeader_tmp = cpu_to_le32(header_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) "outbound opcode msgheader:%x ci=%d pi=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) msgHeader_tmp, circularQ->consumer_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) circularQ->producer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (OPC_OUB_SKIP_ENTRY !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) *messagePtr1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ((u8 *)msgHeader) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) sizeof(struct mpi_msg_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) >> 24) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ": CI=%d PI=%d msgHeader=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) circularQ->consumer_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) circularQ->producer_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) msgHeader_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return MPI_IO_STATUS_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) circularQ->consumer_idx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) (circularQ->consumer_idx +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ((le32_to_cpu(msgHeader_tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) >> 24) & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) % PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) msgHeader_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) pm8001_write_32(msgHeader, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* update the CI of outbound queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) pm8001_cw32(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) circularQ->ci_pci_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) circularQ->ci_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) circularQ->consumer_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) circularQ->consumer_idx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) (circularQ->consumer_idx +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ((le32_to_cpu(msgHeader_tmp) >> 24) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) 0x1f)) % PM8001_MPI_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) msgHeader_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pm8001_write_32(msgHeader, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* update the CI of outbound queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) circularQ->ci_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) circularQ->consumer_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return MPI_IO_STATUS_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u32 producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) void *pi_virt = circularQ->pi_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* spurious interrupt during setup if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * kexec-ing and driver doing a doorbell access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * with the pre-kexec oq interrupt setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!pi_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* Update the producer index from SPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) producer_index = pm8001_read_32(pi_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) circularQ->producer_index = cpu_to_le32(producer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) } while (le32_to_cpu(circularQ->producer_index) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) circularQ->consumer_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* while we don't have any more not-yet-delivered message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* report empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return MPI_IO_STATUS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) void pm8001_work_fn(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct domain_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * So far, all users of this stash an associated structure here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * If we get here, and this pointer is null, then the action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * was cancelled. This nullification happens when the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * goes away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pm8001_dev = pw->data; /* Most stash device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if ((pm8001_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) || ((pw->handler != IO_XFER_ERROR_BREAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) kfree(pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) switch (pw->handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { /* This one stashes the sas_task instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct sas_task *t = (struct sas_task *)pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) unsigned long flags, flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) break; /* Task still on lu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) spin_lock_irqsave(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break; /* Task got completed by another */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* Search for a possible ccb that matches the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ccb = &pm8001_ha->ccb_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) tag = ccb->ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if ((tag != 0xFFFFFFFF) && (ccb->task == t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (!ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) break; /* Task got freed by another */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Force the midlayer to retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) spin_lock_irqsave(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) t, pw->handler, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) mb();/* in order to force CPU ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) t->task_done(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) } break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) { /* This one stashes the sas_task instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct sas_task *t = (struct sas_task *)pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) unsigned long flags, flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ret = pm8001_query_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (ret == TMF_RESP_FUNC_SUCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) else if (ret == TMF_RESP_FUNC_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) spin_lock_irqsave(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) (void)pm8001_abort_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) break; /* Task got completed by another */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) spin_unlock_irqrestore(&t->task_state_lock, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Search for a possible ccb that matches the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) ccb = &pm8001_ha->ccb_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) tag = ccb->ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if ((tag != 0xFFFFFFFF) && (ccb->task == t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) (void)pm8001_abort_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) break; /* Task got freed by another */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) case TMF_RESP_FUNC_SUCC: /* task on lu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ccb->open_retry = 1; /* Snub completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ret = pm8001_abort_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ccb->open_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) case TMF_RESP_FUNC_SUCC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) case TMF_RESP_FUNC_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) default: /* device misbehavior */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ret = TMF_RESP_FUNC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pm8001_I_T_nexus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Do we need to abort the task locally? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) default: /* device misbehavior */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = TMF_RESP_FUNC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pm8001_I_T_nexus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (ret == TMF_RESP_FUNC_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pm8001_dbg(pm8001_ha, IO, "...Complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) } break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) pm8001_I_T_nexus_event_handler(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pm8001_I_T_nexus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case IO_DS_IN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pm8001_I_T_nexus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) case IO_DS_NON_OPERATIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pm8001_I_T_nexus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) kfree(pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) int handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct pm8001_work *pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (pw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) pw->pm8001_ha = pm8001_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) pw->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) pw->handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) INIT_WORK(&pw->work, pm8001_work_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) queue_work(pm8001_wq, &pw->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct pm8001_device *pm8001_ha_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u32 ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct sas_task *task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct task_abort_req task_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u32 opc = OPC_INB_SATA_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (!pm8001_ha_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) task = sas_alloc_slow_task(GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (!task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) task->task_done = pm8001_task_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ccb = &pm8001_ha->ccb_info[ccb_tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ccb->device = pm8001_ha_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ccb->ccb_tag = ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ccb->task = task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ccb->n_elem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) memset(&task_abort, 0, sizeof(task_abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) task_abort.abort_all = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) task_abort.tag = cpu_to_le32(ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) sizeof(task_abort), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) pm8001_tag_free(pm8001_ha, ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct pm8001_device *pm8001_ha_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct sata_start_req sata_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) u32 ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct sas_task *task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct host_to_dev_fis fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct domain_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u32 opc = OPC_INB_SATA_HOST_OPSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) task = sas_alloc_slow_task(GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (!task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) task->task_done = pm8001_task_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) sas_free_task(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* allocate domain device by ourselves as libsas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * is not going to provide any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) sas_free_task(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pm8001_tag_free(pm8001_ha, ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) "Domain device cannot be allocated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) task->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) task->dev->lldd_dev = pm8001_ha_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ccb = &pm8001_ha->ccb_info[ccb_tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ccb->device = pm8001_ha_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ccb->ccb_tag = ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ccb->task = task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ccb->n_elem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) memset(&sata_cmd, 0, sizeof(sata_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* construct read log FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) memset(&fis, 0, sizeof(struct host_to_dev_fis));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) fis.fis_type = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) fis.flags = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) fis.command = ATA_CMD_READ_LOG_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) fis.lbal = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) fis.sector_count = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) sata_cmd.tag = cpu_to_le32(ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) sizeof(sata_cmd), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) sas_free_task(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) pm8001_tag_free(pm8001_ha, ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * mpi_ssp_completion- process the event that FW response to the SSP request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * @piomb: the message contents of this outbound message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * When FW has completed a ssp request for example a IO request, after it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * filled the SG data with the data, it will trigger this event represent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * that he has finished the job,please check the coresponding buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * So we will tell the caller who maybe waiting the result to tell upper layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * that the task has been finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) struct ssp_completion_resp *psspPayload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct ssp_response_iu *iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) psspPayload = (struct ssp_completion_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) status = le32_to_cpu(psspPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) tag = le32_to_cpu(psspPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if ((status == IO_ABORTED) && ccb->open_retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* Being completed by another */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ccb->open_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) param = le32_to_cpu(psspPayload->param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (status && status != IO_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (unlikely(!t || !t->lldd_task || !t->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* Print sas address of IO failed device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) (status != IO_UNDERFLOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) SAS_ADDR(t->dev->sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) pm8001_dbg(pm8001_ha, IOERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "status:0x%x, tag:0x%x, task:0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) status, tag, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) case IO_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (param == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ts->stat = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ts->stat = SAS_PROTO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ts->residual = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) iu = &psspPayload->ssp_resp_iu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) sas_ssp_task_response(pm8001_ha->dev, t, iu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) case IO_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ts->stat = SAS_ABORTED_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) case IO_UNDERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* SSP Completion with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ts->stat = SAS_DATA_UNDERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ts->residual = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) case IO_NO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ts->stat = SAS_PHY_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* Force the midlayer to retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) case IO_XFER_ERROR_PHY_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ts->open_rej_reason = SAS_OREJ_EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) case IO_OPEN_CNX_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (!t->uldd_task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ts->open_rej_reason = SAS_OREJ_BAD_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ts->open_rej_reason = SAS_OREJ_CONN_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) case IO_XFER_ERROR_NAK_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) case IO_XFER_ERROR_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) case IO_XFER_ERROR_OFFSET_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case IO_PORT_IN_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) case IO_DS_NON_OPERATIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (!t->uldd_task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) IO_DS_NON_OPERATIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) case IO_DS_IN_RECOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case IO_TM_TAG_NOT_FOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* not allowed case. Therefore, return failed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) psspPayload->ssp_resp_iu.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) t, status, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) mb();/* in order to force CPU ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) t->task_done(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /*See the comments for mpi_ssp_completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct ssp_event_resp *psspPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) (struct ssp_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) u32 event = le32_to_cpu(psspPayload->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) u32 tag = le32_to_cpu(psspPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) u32 port_id = le32_to_cpu(psspPayload->port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) u32 dev_id = le32_to_cpu(psspPayload->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (unlikely(!t || !t->lldd_task || !t->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) port_id, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) case IO_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ts->residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case IO_XFER_ERROR_PHY_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ts->open_rej_reason = SAS_OREJ_EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) case IO_OPEN_CNX_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (!t->uldd_task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ts->open_rej_reason = SAS_OREJ_BAD_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ts->open_rej_reason = SAS_OREJ_CONN_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) case IO_XFER_ERROR_NAK_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) case IO_XFER_ERROR_UNEXPECTED_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) case IO_XFER_ERROR_XFER_RDY_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) case IO_XFER_ERROR_OFFSET_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) case IO_XFER_CMD_FRAME_ISSUED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* not allowed case. Therefore, return failed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) t, event, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) mb();/* in order to force CPU ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) t->task_done(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /*See the comments for mpi_ssp_completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) u8 sata_addr_low[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) u32 temp_sata_addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) u8 sata_addr_hi[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) u32 temp_sata_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct sata_completion_resp *psataPayload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct ata_task_resp *resp ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) u32 *sata_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) psataPayload = (struct sata_completion_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) status = le32_to_cpu(psataPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) tag = le32_to_cpu(psataPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (!tag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) param = le32_to_cpu(psataPayload->param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (t->dev && (t->dev->lldd_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) pm8001_dev = t->dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) pm8001_dbg(pm8001_ha, FAIL, "task null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) && unlikely(!t || !t->lldd_task || !t->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (!ts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) pm8001_dbg(pm8001_ha, IOERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) "status:0x%x, tag:0x%x, task::0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) status, tag, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* Print sas address of IO failed device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) (status != IO_UNDERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (!((t->dev->parent) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) (dev_is_expander(t->dev->parent->dev_type)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) sata_addr_low[i] = pm8001_ha->sas_addr[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) sata_addr_hi[i] = pm8001_ha->sas_addr[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) memcpy(&temp_sata_addr_low, sata_addr_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) sizeof(sata_addr_low));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) memcpy(&temp_sata_addr_hi, sata_addr_hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) sizeof(sata_addr_hi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) |((temp_sata_addr_hi << 8) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) 0xff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ((temp_sata_addr_hi >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) & 0xff00) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ((temp_sata_addr_hi << 24) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) 0xff000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) & 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ((temp_sata_addr_low << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) & 0xff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ((temp_sata_addr_low >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) & 0xff00) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ((temp_sata_addr_low << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) & 0xff000000)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) pm8001_dev->attached_phy +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) "SAS Address of IO Failure Drive:%08x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) temp_sata_addr_hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) temp_sata_addr_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) "SAS Address of IO Failure Drive:%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) SAS_ADDR(t->dev->sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) case IO_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (param == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ts->stat = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /* check if response is for SEND READ LOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if (pm8001_dev &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* set new bit for abort_all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* clear bit for read log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) pm8001_send_abort_all(pm8001_ha, pm8001_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* Free the tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) sas_free_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ts->stat = SAS_PROTO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ts->residual = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) "SAS_PROTO_RESPONSE len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) sata_resp = &psataPayload->sata_resp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) resp = (struct ata_task_resp *)ts->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (t->ata_task.dma_xfer == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) t->data_dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) len = sizeof(struct pio_setup_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) "PIO read len = %d\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) } else if (t->ata_task.use_ncq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) t->data_dir != DMA_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) len = sizeof(struct set_dev_bits_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) len = sizeof(struct dev_to_host_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) resp->frame_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) memcpy(&resp->ending_fis[0], sata_resp, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ts->buf_valid_size = sizeof(*resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) "response too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) case IO_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ts->stat = SAS_ABORTED_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /* following cases are to do cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case IO_UNDERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* SATA Completion with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ts->stat = SAS_DATA_UNDERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) ts->residual = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) case IO_NO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ts->stat = SAS_PHY_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ts->stat = SAS_INTERRUPTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) case IO_XFER_ERROR_PHY_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ts->open_rej_reason = SAS_OREJ_EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case IO_OPEN_CNX_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ts->open_rej_reason = SAS_OREJ_BAD_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) ts->open_rej_reason = SAS_OREJ_CONN_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) case IO_XFER_ERROR_NAK_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) case IO_XFER_ERROR_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ts->stat = SAS_ABORTED_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) case IO_XFER_ERROR_REJECTED_NCQ_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ts->stat = SAS_DATA_UNDERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) case IO_PORT_IN_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) case IO_DS_NON_OPERATIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) pm8001_handle_event(pm8001_ha, pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) IO_DS_NON_OPERATIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) case IO_DS_IN_RECOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) case IO_DS_IN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) pm8001_handle_event(pm8001_ha, pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) IO_DS_IN_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* not allowed case. Therefore, return failed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) t, status, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /*See the comments for mpi_ssp_completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct sata_event_resp *psataPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) (struct sata_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) u32 event = le32_to_cpu(psataPayload->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) u32 tag = le32_to_cpu(psataPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) u32 port_id = le32_to_cpu(psataPayload->port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) u32 dev_id = le32_to_cpu(psataPayload->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) if (ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) /* Check if this is NCQ error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* find device using device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /* send read log extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) pm8001_send_read_log(pm8001_ha, pm8001_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (unlikely(!t || !t->lldd_task || !t->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) port_id, dev_id, tag, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) case IO_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) ts->residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ts->stat = SAS_INTERRUPTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) case IO_XFER_ERROR_PHY_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ts->open_rej_reason = SAS_OREJ_EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) case IO_OPEN_CNX_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (!t->uldd_task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) ts->resp = SAS_TASK_UNDELIVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ts->open_rej_reason = SAS_OREJ_BAD_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) ts->open_rej_reason = SAS_OREJ_CONN_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) case IO_XFER_ERROR_NAK_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) case IO_XFER_ERROR_PEER_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ts->stat = SAS_NAK_R_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) case IO_XFER_ERROR_REJECTED_NCQ_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ts->stat = SAS_DATA_UNDERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) case IO_XFER_ERROR_UNEXPECTED_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) case IO_XFER_ERROR_XFER_RDY_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) case IO_XFER_ERROR_OFFSET_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) case IO_XFER_CMD_FRAME_ISSUED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) case IO_XFER_PIO_SETUP_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /* not allowed case. Therefore, return failed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ts->stat = SAS_OPEN_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) t, event, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) /*See the comments for mpi_ssp_completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) struct smp_completion_resp *psmpPayload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) psmpPayload = (struct smp_completion_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) status = le32_to_cpu(psmpPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) tag = le32_to_cpu(psmpPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) pm8001_dbg(pm8001_ha, IOERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) "status:0x%x, tag:0x%x, task:0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) status, tag, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (unlikely(!t || !t->lldd_task || !t->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) case IO_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) ts->stat = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) case IO_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) ts->stat = SAS_ABORTED_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) case IO_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) ts->stat = SAS_DATA_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) ts->residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) if (pm8001_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) atomic_dec(&pm8001_dev->running_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) case IO_NO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ts->stat = SAS_PHY_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) case IO_ERROR_HW_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ts->stat = SAM_STAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) case IO_XFER_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) ts->stat = SAM_STAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) case IO_XFER_ERROR_PHY_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) ts->stat = SAM_STAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) case IO_OPEN_CNX_ERROR_BREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) ts->open_rej_reason = SAS_OREJ_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) pm8001_handle_event(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) pm8001_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) ts->open_rej_reason = SAS_OREJ_BAD_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ts->open_rej_reason = SAS_OREJ_CONN_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) case IO_XFER_ERROR_RX_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) case IO_XFER_OPEN_RETRY_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) case IO_ERROR_INTERNAL_SMP_RESOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) ts->stat = SAS_QUEUE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) case IO_PORT_IN_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) case IO_DS_NON_OPERATIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) case IO_DS_IN_RECOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) pm8001_dbg(pm8001_ha, IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) ts->stat = SAS_OPEN_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) ts->stat = SAS_DEV_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) /* not allowed case. Therefore, return failed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) t, status, ts->resp, ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) mb();/* in order to force CPU ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) t->task_done(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) struct set_dev_state_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) (struct set_dev_state_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) u32 tag = le32_to_cpu(pPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) struct pm8001_device *pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) u32 status = le32_to_cpu(pPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) u32 device_id = le32_to_cpu(pPayload->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) device_id, pds, nds, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) complete(pm8001_dev->setds_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) ccb->task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) ccb->ccb_tag = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) struct get_nvm_data_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) (struct get_nvm_data_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) u32 tag = le32_to_cpu(pPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) complete(pm8001_ha->nvmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if ((dlen_status & NVMD_STAT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) ccb->task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) ccb->ccb_tag = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) struct fw_control_ex *fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) struct get_nvm_data_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) (struct get_nvm_data_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) u32 tag = le32_to_cpu(pPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) u32 ir_tds_bn_dps_das_nvm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) fw_control_context = ccb->fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) if ((dlen_status & NVMD_STAT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) complete(pm8001_ha->nvmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) if (ir_tds_bn_dps_das_nvm & IPMode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) /* indirect mode - IR bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) memcpy(pm8001_ha->sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) ((u8 *)virt_addr + 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* Should not be happened*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) "(IR=1)Wrong Device type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) ir_tds_bn_dps_das_nvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) } else /* direct mode */{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) "Get NVMD success, IR=0, dataLen=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) (dlen_status & NVMD_LEN) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) /* Though fw_control_context is freed below, usrAddr still needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) * to be updated as this holds the response to the request function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) memcpy(fw_control_context->usrAddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) pm8001_ha->memoryMap.region[NVMD].virt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) fw_control_context->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) kfree(ccb->fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* To avoid race condition, complete should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) * called after the message is copied to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) * fw_control_context->usrAddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) complete(pm8001_ha->nvmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) ccb->task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) ccb->ccb_tag = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) struct local_phy_ctl_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) (struct local_phy_ctl_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) u32 status = le32_to_cpu(pPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) tag = le32_to_cpu(pPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) "%x phy execute %x phy op failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) phy_id, phy_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) "%x phy execute %x phy op success!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) phy_id, phy_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) pm8001_ha->phy[phy_id].reset_success = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) if (pm8001_ha->phy[phy_id].enable_completion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) complete(pm8001_ha->phy[phy_id].enable_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) pm8001_ha->phy[phy_id].enable_completion = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) * pm8001_bytes_dmaed - one of the interface function communication with libsas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * @i: which phy that received the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) * when HBA driver received the identify done event or initiate FIS received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * event(for SATA), it will invoke this function to notify the sas layer that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) * the sas toplogy has formed, please discover the the whole sas domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) * while receive a broadcast(change) primitive just tell the sas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) * layer to discover the changed domain rather than the whole domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) struct pm8001_phy *phy = &pm8001_ha->phy[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) struct asd_sas_phy *sas_phy = &phy->sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (!phy->phy_attached)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (sas_phy->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) struct sas_phy *sphy = sas_phy->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) sphy->negotiated_linkrate = sas_phy->linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) sphy->minimum_linkrate = phy->minimum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) sphy->maximum_linkrate = phy->maximum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) sphy->maximum_linkrate_hw = phy->maximum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (phy->phy_type & PORT_TYPE_SAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) struct sas_identify_frame *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) id = (struct sas_identify_frame *)phy->frame_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) id->dev_type = phy->identify.device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) id->initiator_bits = SAS_PROTOCOL_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) id->target_bits = phy->identify.target_port_protocols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) } else if (phy->phy_type & PORT_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) /*Nothing*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /* Get the link rate speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) struct sas_phy *sas_phy = phy->sas_phy.phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) switch (link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) case PHY_SPEED_120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) case PHY_SPEED_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) case PHY_SPEED_30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) case PHY_SPEED_15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * asd_get_attached_sas_addr -- extract/generate attached SAS address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) * @phy: pointer to asd_phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) * @sas_addr: pointer to buffer where the SAS address is to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) * This function extracts the SAS address from an IDENTIFY frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) * received. If OOB is SATA, then a SAS address is generated from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) * HA tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) * buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) u8 *sas_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) if (phy->sas_phy.frame_rcvd[0] == 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) /* FIS device-to-host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) addr += phy->sas_phy.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) *(__be64 *)sas_addr = cpu_to_be64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) struct sas_identify_frame *idframe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) (void *) phy->sas_phy.frame_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) * @Qnum: the outbound queue message number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) * @SEA: source of event to ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) * @port_id: port id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) * @phyId: phy id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) * @param0: parameter 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) * @param1: parameter 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) struct hw_event_ack_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) memset((u8 *)&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) payload.tag = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ((phyId & 0x0F) << 4) | (port_id & 0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) payload.param0 = cpu_to_le32(param0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) payload.param1 = cpu_to_le32(param1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) u32 phyId, u32 phy_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) * hw_event_sas_phy_up -FW tells me a SAS phy up event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) struct hw_event_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) (struct hw_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) u32 lr_evt_status_phyid_portid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) u8 link_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) u8 phy_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) u8 portstate = (u8)(npip_portstate & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) struct pm8001_port *port = &pm8001_ha->port[port_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) u8 deviceType = pPayload->sas_identify.dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) port->port_state = portstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) phy->phy_state = PHY_STATE_LINK_UP_SPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) port_id, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) switch (deviceType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) case SAS_PHY_UNUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) case SAS_END_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) pm8001_dbg(pm8001_ha, MSG, "end device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) PHY_NOTIFY_ENABLE_SPINUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) port->port_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) pm8001_get_lrate_mode(phy, link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) case SAS_EDGE_EXPANDER_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) port->port_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) pm8001_get_lrate_mode(phy, link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) case SAS_FANOUT_EXPANDER_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) port->port_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) pm8001_get_lrate_mode(phy, link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) deviceType);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) phy->phy_type |= PORT_TYPE_SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) phy->identify.device_type = deviceType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) phy->phy_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (phy->identify.device_type == SAS_END_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) else if (phy->identify.device_type != SAS_PHY_UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) phy->sas_phy.oob_mode = SAS_OOB_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) memcpy(phy->frame_rcvd, &pPayload->sas_identify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) sizeof(struct sas_identify_frame)-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) if (pm8001_ha->flags == PM8001F_RUN_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) mdelay(200);/*delay a moment to wait disk to spinup*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) pm8001_bytes_dmaed(pm8001_ha, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) * hw_event_sata_phy_up -FW tells me a SATA phy up event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) struct hw_event_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) (struct hw_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) u32 lr_evt_status_phyid_portid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) u8 link_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) u8 phy_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) u8 portstate = (u8)(npip_portstate & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) struct pm8001_port *port = &pm8001_ha->port[port_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) port_id, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) port->port_state = portstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) phy->phy_state = PHY_STATE_LINK_UP_SPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) port->port_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) pm8001_get_lrate_mode(phy, link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) phy->phy_type |= PORT_TYPE_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) phy->phy_attached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) phy->sas_phy.oob_mode = SATA_OOB_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) sizeof(struct dev_to_host_fis));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) phy->identify.device_type = SAS_SATA_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) pm8001_bytes_dmaed(pm8001_ha, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) * hw_event_phy_down -we should notify the libsas the phy is down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) struct hw_event_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) (struct hw_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) u32 lr_evt_status_phyid_portid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) u8 phy_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) u8 portstate = (u8)(npip_portstate & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) struct pm8001_port *port = &pm8001_ha->port[port_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) port->port_state = portstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) phy->phy_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) phy->identify.device_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) switch (portstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) case PORT_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) case PORT_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) " Last phy Down and port invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) port->port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) case PORT_IN_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) case PORT_NOT_ESTABLISHED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) " phy Down and PORT_NOT_ESTABLISHED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) port->port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) case PORT_LOSTCOMM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) " Last phy Down and port invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) port->port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) port->port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) portstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) * pm8001_mpi_reg_resp -process register device ID response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) * when sas layer find a device it will notify LLDD, then the driver register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) * the domain device to FW, this event is the return device ID which the FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) * has assigned, from now,inter-communication with FW is no longer using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) * SAS address, use device ID which FW assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) u32 htag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) struct dev_reg_resp *registerRespPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) (struct dev_reg_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) htag = le32_to_cpu(registerRespPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) ccb = &pm8001_ha->ccb_info[htag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) pm8001_dev = ccb->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) status = le32_to_cpu(registerRespPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) device_id = le32_to_cpu(registerRespPayload->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) case DEVREG_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) pm8001_dev->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) case DEVREG_FAILURE_OUT_OF_RESOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) case DEVREG_FAILURE_INVALID_PHY_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) complete(pm8001_dev->dcompletion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ccb->task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) ccb->ccb_tag = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) pm8001_tag_free(pm8001_ha, htag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) struct dev_reg_resp *registerRespPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) (struct dev_reg_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) status = le32_to_cpu(registerRespPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) device_id = le32_to_cpu(registerRespPayload->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) " deregister device failed ,status = %x, device_id = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) status, device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) * fw_flash_update_resp - Response from FW for flash update command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) struct fw_flash_Update_resp *ppayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) (struct fw_flash_Update_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) u32 tag = le32_to_cpu(ppayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) status = le32_to_cpu(ppayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) case FLASH_UPDATE_IN_PROGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) case FLASH_UPDATE_HDR_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) case FLASH_UPDATE_OFFSET_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) case FLASH_UPDATE_CRC_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) case FLASH_UPDATE_LENGTH_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) case FLASH_UPDATE_HW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) case FLASH_UPDATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) kfree(ccb->fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) ccb->task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) ccb->ccb_tag = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) complete(pm8001_ha->nvmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) struct general_event_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) (struct general_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) status = le32_to_cpu(pPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) pPayload->inb_IOMB_payload[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) struct sas_task *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) u32 status ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) u32 tag, scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) struct pm8001_device *pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) struct task_abort_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) (struct task_abort_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) status = le32_to_cpu(pPayload->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) tag = le32_to_cpu(pPayload->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) if (!tag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) scp = le32_to_cpu(pPayload->scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) t = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) pm8001_dev = ccb->device; /* retrieve device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) if (!t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) ts = &t->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) status, tag, scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) case IO_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) ts->stat = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) case IO_NOT_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) ts->resp = TMF_RESP_FUNC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) spin_lock_irqsave(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) t->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) spin_unlock_irqrestore(&t->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) sas_free_task(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) /* clear the flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) pm8001_dev->id &= 0xBFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) t->task_done(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) * mpi_hw_event -The hw event has come.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) struct hw_event_resp *pPayload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) (struct hw_event_resp *)(piomb + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) u32 lr_evt_status_phyid_portid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) u8 phy_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) u16 eventType =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) u8 status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) struct sas_ha_struct *sas_ha = pm8001_ha->sas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) port_id, phy_id, eventType, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) switch (eventType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) case HW_EVENT_PHY_START_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) phy->phy_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) if (pm8001_ha->flags == PM8001F_RUN_TIME &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) phy->enable_completion != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) complete(phy->enable_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) phy->enable_completion = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) case HW_EVENT_SAS_PHY_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) hw_event_sas_phy_up(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) case HW_EVENT_SATA_PHY_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) hw_event_sata_phy_up(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) case HW_EVENT_PHY_STOP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) phy->phy_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) case HW_EVENT_SATA_SPINUP_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) case HW_EVENT_PHY_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) phy->phy_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) hw_event_phy_down(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) case HW_EVENT_PORT_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) /* the broadcast change primitive received, tell the LIBSAS this event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) to revalidate the sas domain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) case HW_EVENT_BROADCAST_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) port_id, phy_id, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) case HW_EVENT_PHY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) sas_phy_disconnected(&phy->sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) case HW_EVENT_BROADCAST_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) case HW_EVENT_LINK_ERR_INVALID_DWORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) HW_EVENT_LINK_ERR_DISPARITY_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) case HW_EVENT_LINK_ERR_CODE_VIOLATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) HW_EVENT_LINK_ERR_CODE_VIOLATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) case HW_EVENT_MALFUNCTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) case HW_EVENT_BROADCAST_SES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) case HW_EVENT_INBOUND_CRC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) HW_EVENT_INBOUND_CRC_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) case HW_EVENT_HARD_RESET_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) case HW_EVENT_ID_FRAME_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) pm8001_hw_event_ack_req(pm8001_ha, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) port_id, phy_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) case HW_EVENT_PORT_RESET_TIMER_TMO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) sas_phy_disconnected(sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) phy->phy_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) case HW_EVENT_PORT_RECOVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) case HW_EVENT_PORT_RESET_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) case EVENT_BROADCAST_ASYNCH_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) eventType);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) * process_one_iomb - process one outbound Queue memory block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) * @pm8001_ha: our hba card information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) * @piomb: IO message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) __le32 pHeader = *(__le32 *)piomb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) switch (opc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) case OPC_OUB_ECHO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) case OPC_OUB_HW_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) mpi_hw_event(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) case OPC_OUB_SSP_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) mpi_ssp_completion(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) case OPC_OUB_SMP_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) mpi_smp_completion(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) case OPC_OUB_LOCAL_PHY_CNTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) case OPC_OUB_DEV_REGIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) pm8001_mpi_reg_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) case OPC_OUB_DEREG_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) pm8001_mpi_dereg_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) case OPC_OUB_GET_DEV_HANDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) case OPC_OUB_SATA_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) mpi_sata_completion(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) case OPC_OUB_SATA_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) mpi_sata_event(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) case OPC_OUB_SSP_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) mpi_ssp_event(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) case OPC_OUB_DEV_HANDLE_ARRIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) /*This is for target*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) case OPC_OUB_SSP_RECV_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) /*This is for target*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) case OPC_OUB_DEV_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) case OPC_OUB_FW_FLASH_UPDATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) case OPC_OUB_GPIO_RESPONSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) case OPC_OUB_GPIO_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) case OPC_OUB_GENERAL_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) pm8001_mpi_general_event(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) case OPC_OUB_SSP_ABORT_RSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) case OPC_OUB_SATA_ABORT_RSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) case OPC_OUB_SAS_DIAG_MODE_START_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) pm8001_dbg(pm8001_ha, MSG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) "OPC_OUB_SAS_DIAG_MODE_START_END\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) case OPC_OUB_SAS_DIAG_EXECUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) case OPC_OUB_GET_TIME_STAMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) case OPC_OUB_SAS_HW_EVENT_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) case OPC_OUB_PORT_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) case OPC_OUB_SMP_ABORT_RSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) case OPC_OUB_GET_NVMD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) case OPC_OUB_SET_NVMD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) case OPC_OUB_DEVICE_HANDLE_REMOVAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) case OPC_OUB_SET_DEVICE_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) case OPC_OUB_GET_DEVICE_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) case OPC_OUB_SET_DEV_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) case OPC_OUB_SAS_RE_INITIALIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) "Unknown outbound Queue IOMB OPC = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) struct outbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) void *pMsg1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) u8 bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) u32 ret = MPI_IO_STATUS_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) spin_lock_irqsave(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) circularQ = &pm8001_ha->outbnd_q_tbl[vec];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) if (MPI_IO_STATUS_SUCCESS == ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) /* process the outbound message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) /* free the message from the outbound circular buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) circularQ, bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) if (MPI_IO_STATUS_BUSY == ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) /* Update the producer index from SPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) circularQ->producer_index =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) if (le32_to_cpu(circularQ->producer_index) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) circularQ->consumer_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) /* OQ is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) spin_unlock_irqrestore(&pm8001_ha->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) /* DMA_... to our direction translation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) static const u8 data_dir_flags[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) struct pm8001_prd *buf_prd = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) for_each_sg(scatter, sg, nr, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) buf_prd->im_len.e = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) buf_prd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) psmp_cmd->tag = hTag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) psmp_cmd->device_id = cpu_to_le32(deviceID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) * pm8001_chip_smp_req - send a SMP task to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) * @ccb: the ccb information this request used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) struct pm8001_ccb_info *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) int elem, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) struct sas_task *task = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) struct domain_device *dev = task->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) struct pm8001_device *pm8001_dev = dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) struct scatterlist *sg_req, *sg_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) u32 req_len, resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) struct smp_req smp_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) u32 opc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) memset(&smp_cmd, 0, sizeof(smp_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) * DMA-map SMP request, response buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) sg_req = &task->smp_task.smp_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) if (!elem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) req_len = sg_dma_len(sg_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) sg_resp = &task->smp_task.smp_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) if (!elem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) resp_len = sg_dma_len(sg_resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) /* must be in dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) if ((req_len & 0x3) || (resp_len & 0x3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) goto err_out_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) opc = OPC_INB_SMP_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) smp_cmd.long_smp_req.long_req_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) smp_cmd.long_smp_req.long_req_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) smp_cmd.long_smp_req.long_resp_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) smp_cmd.long_smp_req.long_resp_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) &smp_cmd, sizeof(smp_cmd), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) goto err_out_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) err_out_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) * pm8001_chip_ssp_io_req - send a SSP task to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) * @ccb: the ccb information this request used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) struct pm8001_ccb_info *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) struct sas_task *task = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) struct domain_device *dev = task->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) struct pm8001_device *pm8001_dev = dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) struct ssp_ini_io_start_req ssp_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) u32 tag = ccb->ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) u64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) u32 opc = OPC_INB_SSPINIIOSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) memset(&ssp_cmd, 0, sizeof(ssp_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) ssp_cmd.dir_m_tlr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) SAS 1.1 compatible TLR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) ssp_cmd.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) if (task->ssp_task.enable_first_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) task->ssp_task.cmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) /* fill in PRD (scatter/gather) table, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) if (task->num_scatter > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) phys_addr = ccb->ccb_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) ssp_cmd.esgl = cpu_to_le32(1<<31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) } else if (task->num_scatter == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) u64 dma_addr = sg_dma_address(task->scatter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) ssp_cmd.esgl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) } else if (task->num_scatter == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) ssp_cmd.addr_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) ssp_cmd.addr_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) ssp_cmd.esgl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) sizeof(ssp_cmd), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) struct pm8001_ccb_info *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) struct sas_task *task = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) struct domain_device *dev = task->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) u32 tag = ccb->ccb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) struct sata_start_req sata_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) u32 hdr_tag, ncg_tag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) u64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) u32 ATAP = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) u32 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) u32 opc = OPC_INB_SATA_HOST_OPSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) memset(&sata_cmd, 0, sizeof(sata_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) ATAP = 0x04; /* no data*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) pm8001_dbg(pm8001_ha, IO, "no data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) } else if (likely(!task->ata_task.device_control_reg_update)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) if (task->ata_task.use_ncq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) dev->sata_dev.class != ATA_DEV_ATAPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) ATAP = 0x07; /* FPDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) } else if (task->ata_task.dma_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) ATAP = 0x06; /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) pm8001_dbg(pm8001_ha, IO, "DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) ATAP = 0x05; /* PIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) pm8001_dbg(pm8001_ha, IO, "PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) ncg_tag = hdr_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) dir = data_dir_flags[task->data_dir] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) sata_cmd.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) sata_cmd.ncqtag_atap_dir_m =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) sata_cmd.sata_fis = task->ata_task.fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) if (likely(!task->ata_task.device_control_reg_update))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) /* fill in PRD (scatter/gather) table, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) if (task->num_scatter > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) phys_addr = ccb->ccb_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) sata_cmd.addr_low = lower_32_bits(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) sata_cmd.addr_high = upper_32_bits(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) sata_cmd.esgl = cpu_to_le32(1 << 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) } else if (task->num_scatter == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) u64 dma_addr = sg_dma_address(task->scatter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) sata_cmd.addr_low = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) sata_cmd.addr_high = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) sata_cmd.len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) sata_cmd.esgl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) } else if (task->num_scatter == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) sata_cmd.addr_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) sata_cmd.addr_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) sata_cmd.len = cpu_to_le32(task->total_xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) sata_cmd.esgl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) /* Check for read log for failed drive and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) if (sata_cmd.sata_fis.command == 0x2f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) struct task_status_struct *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) pm8001_ha_dev->id &= 0xDFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) ts = &task->task_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) spin_lock_irqsave(&task->task_state_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) ts->resp = SAS_TASK_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) ts->stat = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) task->task_state_flags |= SAS_TASK_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) if (unlikely((task->task_state_flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) SAS_TASK_STATE_ABORTED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) spin_unlock_irqrestore(&task->task_state_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) pm8001_dbg(pm8001_ha, FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) task, ts->resp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) ts->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) spin_unlock_irqrestore(&task->task_state_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) pm8001_ccb_task_free_done(pm8001_ha, task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) ccb, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) sizeof(sata_cmd), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) * @phy_id: the phy id which we wanted to start up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) struct phy_start_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) u32 tag = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) u32 opcode = OPC_INB_PHYSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) ** [0:7] PHY Identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) ** [8:11] link rate 1.5G, 3G, 6G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) ** [14] 0b disable spin up hold; 1b enable spin up hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) LINKMODE_AUTO | LINKRATE_15 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) LINKRATE_30 | LINKRATE_60 | phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) payload.sas_identify.dev_type = SAS_END_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) memcpy(payload.sas_identify.sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) pm8001_ha->sas_addr, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) payload.sas_identify.phy_id = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) * @phy_id: the phy id which we wanted to start up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) u8 phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) struct phy_stop_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) u32 tag = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) u32 opcode = OPC_INB_PHYSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) payload.phy_id = cpu_to_le32(phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) * see comments on pm8001_mpi_reg_resp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) struct pm8001_device *pm8001_dev, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) struct reg_dev_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) u32 opc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) u32 stp_sspsmp_sata = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) u32 linkrate, phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) int rc, tag = 0xdeadbeef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) u8 retryFlag = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) u16 firstBurstSize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) u16 ITNT = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) struct domain_device *dev = pm8001_dev->sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) struct domain_device *parent_dev = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) ccb->device = pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) if (flag == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) stp_sspsmp_sata = 0x02; /*direct attached sata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) if (pm8001_dev->dev_type == SAS_SATA_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) stp_sspsmp_sata = 0x00; /* stp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) stp_sspsmp_sata = 0x01; /*ssp or smp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) if (parent_dev && dev_is_expander(parent_dev->dev_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) phy_id = parent_dev->ex_dev.ex_phy->phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) phy_id = pm8001_dev->attached_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) opc = OPC_INB_REG_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) pm8001_dev->sas_device->linkrate : dev->port->linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) payload.phyid_portid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) ((phy_id & 0x0F) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) ((linkrate & 0x0F) * 0x1000000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) ((stp_sspsmp_sata & 0x03) * 0x10000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) payload.firstburstsize_ITNexustimeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) * see comments on pm8001_mpi_reg_resp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) u32 device_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) struct dereg_dev_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) u32 opc = OPC_INB_DEREG_DEV_HANDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) payload.tag = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) payload.device_id = cpu_to_le32(device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) * pm8001_chip_phy_ctl_req - support the local phy operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) * @phyId: the phy id which we wanted to operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) * @phy_op: the phy operation to request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) u32 phyId, u32 phy_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) struct local_phy_ctl_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) payload.tag = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) payload.phyop_phyid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) #ifdef PM8001_USE_MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) * pm8001_chip_isr - PM8001 isr handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) * @vec: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) pm8001_chip_interrupt_disable(pm8001_ha, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) "irq vec %d, ODMR:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) vec, pm8001_cr32(pm8001_ha, 0, 0x30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) process_oq(pm8001_ha, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) pm8001_chip_interrupt_enable(pm8001_ha, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) struct task_abort_req task_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) memset(&task_abort, 0, sizeof(task_abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) if (ABORT_SINGLE == (flag & ABORT_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) task_abort.abort_all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) task_abort.device_id = cpu_to_le32(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) task_abort.tag_to_abort = cpu_to_le32(task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) task_abort.tag = cpu_to_le32(cmd_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) } else if (ABORT_ALL == (flag & ABORT_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) task_abort.abort_all = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) task_abort.device_id = cpu_to_le32(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) task_abort.tag = cpu_to_le32(cmd_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) sizeof(task_abort), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) * pm8001_chip_abort_task - SAS abort task when error or exception happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) u32 opc, device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) int rc = TMF_RESP_FUNC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) cmd_tag, task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) if (pm8001_dev->dev_type == SAS_END_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) opc = OPC_INB_SSP_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) else if (pm8001_dev->dev_type == SAS_SATA_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) opc = OPC_INB_SATA_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) opc = OPC_INB_SMP_ABORT;/* SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) device_id = pm8001_dev->device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) rc = send_task_abort(pm8001_ha, opc, device_id, flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) task_tag, cmd_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) if (rc != TMF_RESP_FUNC_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) * pm8001_chip_ssp_tm_req - built the task management command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) * @ccb: the ccb information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) * @tmf: task management function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) struct sas_task *task = ccb->task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) struct domain_device *dev = task->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) struct pm8001_device *pm8001_dev = dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) u32 opc = OPC_INB_SSPINITMSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) struct ssp_ini_tm_start_req sspTMCmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) memset(&sspTMCmd, 0, sizeof(sspTMCmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) if (pm8001_ha->chip_id != chip_8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) sizeof(sspTMCmd), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) void *payload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) u32 opc = OPC_INB_GET_NVMD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) u32 nvmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) struct get_nvm_data_req nvmd_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) struct fw_control_ex *fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) struct pm8001_ioctl_payload *ioctl_payload = payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) nvmd_type = ioctl_payload->minor_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) if (!fw_control_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) fw_control_context->len = ioctl_payload->rd_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) memset(&nvmd_req, 0, sizeof(nvmd_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) kfree(fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) ccb->fw_control_context = fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) nvmd_req.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) switch (nvmd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) case TWI_DEVICE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) u32 twi_addr, twi_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) twi_addr = 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) twi_page_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) twi_page_size << 8 | TWI_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) case C_SEEPROM: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) case VPD_FLASH: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) case EXPAN_ROM: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) case IOP_RDUMP: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) sizeof(nvmd_req), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) kfree(fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) void *payload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) u32 opc = OPC_INB_SET_NVMD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) u32 nvmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) struct set_nvm_data_req nvmd_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) struct fw_control_ex *fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) struct pm8001_ioctl_payload *ioctl_payload = payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) nvmd_type = ioctl_payload->minor_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) if (!fw_control_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) &ioctl_payload->func_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) ioctl_payload->wr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) memset(&nvmd_req, 0, sizeof(nvmd_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) kfree(fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) ccb->fw_control_context = fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) nvmd_req.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) switch (nvmd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) case TWI_DEVICE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) u32 twi_addr, twi_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) twi_addr = 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) twi_page_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) twi_page_size << 8 | TWI_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) case C_SEEPROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) case VPD_FLASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) case EXPAN_ROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) nvmd_req.resp_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) nvmd_req.resp_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) sizeof(nvmd_req), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) kfree(fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) * pm8001_chip_fw_flash_update_build - support the firmware update operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) * @pm8001_ha: our hba card information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) * @fw_flash_updata_info: firmware flash update param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) * @tag: Tag to apply to the payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) void *fw_flash_updata_info, u32 tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) struct fw_flash_Update_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) struct fw_flash_updata_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) u32 opc = OPC_INB_FW_FLASH_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) memset(&payload, 0, sizeof(struct fw_flash_Update_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) info = fw_flash_updata_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) payload.cur_image_len = cpu_to_le32(info->cur_image_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) payload.total_image_len = cpu_to_le32(info->total_image_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) payload.len = info->sgl.im_len.len ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) payload.sgl_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) payload.sgl_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) void *payload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) struct fw_flash_updata_info flash_update_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) struct fw_control_info *fw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) struct fw_control_ex *fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) struct pm8001_ioctl_payload *ioctl_payload = payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) if (!fw_control_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) pm8001_dbg(pm8001_ha, DEVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) "dma fw_control context input length :%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) fw_control->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) memcpy(buffer, fw_control->buffer, fw_control->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) flash_update_info.sgl.im_len.e = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) flash_update_info.cur_image_offset = fw_control->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) flash_update_info.cur_image_len = fw_control->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) flash_update_info.total_image_len = fw_control->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) fw_control_context->fw_control = fw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) fw_control_context->virtAddr = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) fw_control_context->phys_addr = phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) fw_control_context->len = fw_control->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) kfree(fw_control_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) ccb->fw_control_context = fw_control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) u32 value, rem, offset = 0, bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) u32 index, work_offset, dw_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) u32 shift_value, gsm_base, gsm_dump_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) char *direct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) struct Scsi_Host *shost = class_to_shost(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) direct_data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) /* check max is 1 Mbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) if ((length > 0x100000) || (gsm_dump_offset & 3) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) ((gsm_dump_offset + length) > 0x1000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) if (pm8001_ha->chip_id == chip_8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) bar = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) bar = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) work_offset = gsm_dump_offset & 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) offset = gsm_dump_offset & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) gsm_dump_offset = work_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) /* adjust length to dword boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) rem = length & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) dw_length = length >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) for (index = 0; index < dw_length; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) if ((work_offset + offset) & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) if (pm8001_ha->chip_id == chip_8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) shift_value = ((gsm_dump_offset + offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) SHIFT_REG_64K_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) shift_value = (((gsm_dump_offset + offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) SHIFT_REG_64K_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) SHIFT_REG_BIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) if (pm8001_ha->chip_id == chip_8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) gsm_base = GSM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) if (-1 == pm8001_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) (gsm_base + shift_value)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) gsm_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) if (-1 == pm80xx_bar4_shift(pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) (gsm_base + shift_value)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) gsm_dump_offset = (gsm_dump_offset + offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) work_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) offset = offset & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) direct_data += sprintf(direct_data, "%08x ", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) if (rem != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) /* xfr for non_dw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) direct_data += sprintf(direct_data, "%08x ", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) /* Shift back to BAR4 original address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) pm8001_ha->fatal_forensic_shift_offset += 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) pm8001_ha->fatal_forensic_shift_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) return direct_data - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) struct pm8001_device *pm8001_dev, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) struct set_dev_state_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) u32 opc = OPC_INB_SET_DEVICE_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) ccb->device = pm8001_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) payload.device_id = cpu_to_le32(pm8001_dev->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) payload.nds = cpu_to_le32(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) struct sas_re_initialization_req payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) struct inbound_queue_table *circularQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) struct pm8001_ccb_info *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) u32 opc = OPC_INB_SAS_RE_INITIALIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) memset(&payload, 0, sizeof(payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) rc = pm8001_tag_alloc(pm8001_ha, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) ccb = &pm8001_ha->ccb_info[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) ccb->ccb_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) circularQ = &pm8001_ha->inbnd_q_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) payload.tag = cpu_to_le32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) payload.SSAHOLT = cpu_to_le32(0xd << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) payload.sata_hol_tmo = cpu_to_le32(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) sizeof(payload), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) pm8001_tag_free(pm8001_ha, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) const struct pm8001_dispatch pm8001_8001_dispatch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) .name = "pmc8001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) .chip_init = pm8001_chip_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) .chip_soft_rst = pm8001_chip_soft_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) .chip_rst = pm8001_hw_chip_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) .chip_iounmap = pm8001_chip_iounmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) .isr = pm8001_chip_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) .is_our_interrupt = pm8001_chip_is_our_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) .isr_process_oq = process_oq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) .interrupt_enable = pm8001_chip_interrupt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) .interrupt_disable = pm8001_chip_interrupt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) .make_prd = pm8001_chip_make_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) .smp_req = pm8001_chip_smp_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) .ssp_io_req = pm8001_chip_ssp_io_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) .sata_req = pm8001_chip_sata_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) .phy_start_req = pm8001_chip_phy_start_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) .phy_stop_req = pm8001_chip_phy_stop_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) .reg_dev_req = pm8001_chip_reg_dev_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) .dereg_dev_req = pm8001_chip_dereg_dev_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) .phy_ctl_req = pm8001_chip_phy_ctl_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) .task_abort = pm8001_chip_abort_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) .ssp_tm_req = pm8001_chip_ssp_tm_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) .get_nvmd_req = pm8001_chip_get_nvmd_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) .set_nvmd_req = pm8001_chip_set_nvmd_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) .set_dev_state_req = pm8001_chip_set_dev_state_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) .sas_re_init_req = pm8001_chip_sas_re_initialization,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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