Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*=======================================================/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)   Header file for nsp_cs.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)       By: YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Ver.1.0 : Cut unused lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     Ver 0.1 : Initial version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     the GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) =========================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifndef  __nsp_cs__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define  __nsp_cs__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) //#define NSP_DEBUG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Some useful macros...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* SCSI initiator must be ID 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define NSP_INITIATOR_ID  7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define NSP_SELTIMEOUT 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * base register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  ========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	IRQCONTROL	0x00  /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #  define IRQCONTROL_RESELECT_CLEAR     BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #  define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #  define IRQCONTROL_TIMER_CLEAR        BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #  define IRQCONTROL_FIFO_CLEAR         BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #  define IRQCONTROL_ALLMASK            0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #  define IRQCONTROL_ALLCLEAR           (IRQCONTROL_RESELECT_CLEAR     | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					 IRQCONTROL_PHASE_CHANGE_CLEAR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					 IRQCONTROL_TIMER_CLEAR        | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					 IRQCONTROL_FIFO_CLEAR          )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #  define IRQCONTROL_IRQDISABLE         0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	IRQSTATUS	0x00  /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #  define IRQSTATUS_SCSI  BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #  define IRQSTATUS_TIMER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #  define IRQSTATUS_FIFO  BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #  define IRQSTATUS_MASK  0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	IFSELECT	0x01 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #  define IF_IFSEL    BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #  define IF_REGSEL   BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	FIFOSTATUS	0x01 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #  define FIFOSTATUS_CHIP_REVISION_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #  define FIFOSTATUS_CHIP_ID_MASK       0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #  define FIFOSTATUS_FULL_EMPTY         BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	INDEXREG	0x02 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	DATAREG		0x03 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	FIFODATA	0x04 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	FIFODATA1	0x05 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	FIFODATA2	0x06 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	FIFODATA3	0x07 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * indexed register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  ====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EXTBUSCTRL	0x10 /* R/W,deleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLOCKDIV	0x11 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #  define CLOCK_40M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #  define CLOCK_20M 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #  define FAST_20   BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TERMPWRCTRL	0x13 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #  define POWER_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCSIIRQMODE	0x15 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #  define SCSI_PHASE_CHANGE_EI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #  define RESELECT_EI          BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #  define FIFO_IRQ_EI          BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #  define SCSI_RESET_IRQ_EI    BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IRQPHASESENCE	0x16 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #  define LATCHED_MSG      BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #  define LATCHED_IO       BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #  define LATCHED_CD       BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #  define LATCHED_BUS_FREE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #  define PHASE_CHANGE_IRQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #  define RESELECT_IRQ     BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #  define FIFO_IRQ         BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #  define SCSI_RESET_IRQ   BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TIMERCOUNT	0x17 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCSIBUSCTRL	0x18 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #  define SCSI_SEL         BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #  define SCSI_RST         BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #  define SCSI_DATAOUT_ENB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #  define SCSI_ATN         BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #  define SCSI_ACK         BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #  define SCSI_BSY         BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #  define AUTODIRECTION    BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #  define ACKENB           BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCSIBUSMON	0x19 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SETARBIT	0x1A /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #  define ARBIT_GO         BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #  define ARBIT_FLAG_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ARBITSTATUS	0x1A /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*#  define ARBIT_GO        BIT(0)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #  define ARBIT_WIN        BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #  define ARBIT_FAIL       BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #  define RESELECT_FLAG    BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PARITYCTRL	0x1B  /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PARITYSTATUS	0x1B  /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define COMMANDCTRL	0x1C  /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #  define CLEAR_COMMAND_POINTER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #  define AUTO_COMMAND_GO       BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RESELECTID	0x1C  /* R   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define COMMANDDATA	0x1D  /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define POINTERCLR	0x1E  /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #  define POINTER_CLEAR      BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #  define ACK_COUNTER_CLEAR  BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #  define REQ_COUNTER_CLEAR  BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #  define HOST_COUNTER_CLEAR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #  define READ_SOURCE        (BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #    define ACK_COUNTER        (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #    define REQ_COUNTER        (BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #    define HOST_COUNTER       (BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TRANSFERCOUNT	0x1E  /* R   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TRANSFERMODE	0x20  /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #  define MODE_MEM8   BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #  define MODE_MEM32  BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #  define MODE_ADR24  BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #  define MODE_ADR32  BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #  define MODE_IO8    BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #  define MODE_IO32   BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #  define TRANSFER_GO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #  define BRAIND      BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SYNCREG		0x21 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #  define SYNCREG_OFFSET_MASK  0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #  define SYNCREG_PERIOD_MASK  0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #  define SYNCREG_PERIOD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SCSIDATALATCH	0x22 /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SCSIDATAIN	0x22 /* R   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SCSIDATAWITHACK	0x23 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SCAMCONTROL	0x24 /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SCAMSTATUS	0x24 /* R   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SCAMDATA	0x25 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OTHERCONTROL	0x26 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #  define TPL_ROM_WRITE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #  define TPWR_OUT         BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #  define TPWR_SENSE       BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #  define RA8_CONTROL      BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ACKWIDTH	0x27 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLRTESTPNT	0x28 /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ACKCNTLD	0x29 /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REQCNTLD	0x2A /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HSTCNTLD	0x2B /*   W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CHECKSUM	0x2C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * Input status bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define S_MESSAGE	BIT(0)    /* Message line from SCSI bus      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define S_IO		BIT(1)    /* Input/Output line from SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define S_CD		BIT(2)    /* Command/Data line from SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define S_BUSY		BIT(3)    /* Busy line from SCSI bus         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define S_ACK		BIT(4)    /* Acknowledge line from SCSI bus  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define S_REQUEST	BIT(5)    /* Request line from SCSI bus      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define S_SELECT	BIT(6)	  /*                                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define S_ATN		BIT(7)	  /*                                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * Useful Bus Monitor status combinations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BUSMON_SEL         S_SELECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BUSMON_BSY         S_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BUSMON_REQ         S_REQUEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BUSMON_IO          S_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BUSMON_ACK         S_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BUSMON_BUS_FREE    0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BUSMON_COMMAND     ( S_BUSY | S_CD |                    S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BUSMON_MESSAGE_IN  ( S_BUSY | S_CD | S_IO | S_MESSAGE | S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BUSMON_MESSAGE_OUT ( S_BUSY | S_CD |        S_MESSAGE | S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BUSMON_DATA_IN     ( S_BUSY |        S_IO |             S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BUSMON_DATA_OUT    ( S_BUSY |                           S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BUSMON_STATUS      ( S_BUSY | S_CD | S_IO |             S_REQUEST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BUSMON_SELECT      (                 S_IO |                        S_SELECT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BUSMON_RESELECT    (                 S_IO |                        S_SELECT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BUSMON_PHASE_MASK  (          S_CD | S_IO | S_MESSAGE |            S_SELECT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BUSPHASE_SELECT      ( BUSMON_SELECT      & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BUSPHASE_COMMAND     ( BUSMON_COMMAND     & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BUSPHASE_MESSAGE_IN  ( BUSMON_MESSAGE_IN  & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BUSPHASE_DATA_IN     ( BUSMON_DATA_IN     & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BUSPHASE_DATA_OUT    ( BUSMON_DATA_OUT    & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BUSPHASE_STATUS      ( BUSMON_STATUS      & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) typedef struct scsi_info_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct pcmcia_device	*p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct Scsi_Host      *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int                    stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } scsi_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* synchronous transfer negotiation data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) typedef struct _sync_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned int SyncNegotiation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SYNC_NOT_YET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SYNC_OK      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SYNC_NG      2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	unsigned int  SyncPeriod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned int  SyncOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	unsigned char SyncRegister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned char AckWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } sync_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) typedef struct _nsp_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned int  BaseAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned int  NumAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	unsigned int  IrqNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned long MmioAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define NSP_MMIO_OFFSET 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned long MmioLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	unsigned char ScsiClockDiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	unsigned char TransferMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int           TimerCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int           SelectionTimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct scsi_cmnd *CurrentSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	//int           CurrnetTarget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int           FifoCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MSGBUF_SIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	unsigned char MsgBuffer[MSGBUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int MsgLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define N_TARGET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	sync_data     Sync[N_TARGET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	char nspinfo[110];     /* description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	spinlock_t Lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	scsi_info_t   *ScsiInfo; /* attach <-> detect glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef NSP_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int CmdId; /* Accepted command serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		      Used for debugging.             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } nsp_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Card service functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void        nsp_cs_detach (struct pcmcia_device *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void        nsp_cs_release(struct pcmcia_device *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int        nsp_cs_config (struct pcmcia_device *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Linux SCSI subsystem specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct Scsi_Host *nsp_detect     (struct scsi_host_template *sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const  char      *nsp_info       (struct Scsi_Host *shpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static        int        nsp_show_info  (struct seq_file *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	                                 struct Scsi_Host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int nsp_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*static int nsp_eh_abort       (struct scsi_cmnd *SCpnt);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*static int nsp_eh_device_reset(struct scsi_cmnd *SCpnt);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int nsp_eh_bus_reset    (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int nsp_eh_host_reset   (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int nsp_bus_reset       (nsp_hw_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int  nsphw_init           (nsp_hw_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int  nsphw_start_selection(struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void nsp_start_timer      (struct scsi_cmnd *SCpnt, int time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int  nsp_fifo_count       (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void nsp_pio_read         (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void nsp_pio_write        (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int  nsp_nexus            (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void nsp_scsi_done        (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int  nsp_analyze_sdtr     (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int  nsp_negate_signal    (struct scsi_cmnd *SCpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				  unsigned char mask, char *str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int  nsp_expect_signal    (struct scsi_cmnd *SCpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				  unsigned char current_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				  unsigned char  mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int  nsp_xfer             (struct scsi_cmnd *SCpnt, int phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int  nsp_dataphase_bypass (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int  nsp_reselected       (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct Scsi_Host *nsp_detect(struct scsi_host_template *sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) //static irqreturn_t nspintr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifdef NSP_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void show_command (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void show_phase   (struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void show_busphase(unsigned char stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void show_message (nsp_hw_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) # define show_command(ptr)   /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) # define show_phase(SCpnt)   /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) # define show_busphase(stat) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) # define show_message(data)  /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  * SCSI phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) enum _scsi_phase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	PH_UNDETERMINED ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	PH_ARBSTART     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	PH_SELSTART     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	PH_SELECTED     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	PH_COMMAND      ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	PH_DATA         ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	PH_STATUS       ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	PH_MSG_IN       ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	PH_MSG_OUT      ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	PH_DISCONNECT   ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	PH_RESELECT     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	PH_ABORT        ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	PH_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) enum _data_in_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	IO_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	IO_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	IO_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum _burst_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	BURST_IO8   = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	BURST_IO32  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	BURST_MEM32 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * SCSI messaage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MSG_COMMAND_COMPLETE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MSG_EXTENDED         0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MSG_ABORT            0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MSG_NO_OPERATION     0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MSG_BUS_DEVICE_RESET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MSG_EXT_SDTR         0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* scatter-gather table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #  define BUFFER_ADDR ((char *)((sg_virt(SCpnt->SCp.buffer))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif  /*__nsp_cs__*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* end */