^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Basic data header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _NSP32_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _NSP32_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define NSP32_DEBUG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * VENDOR/DEVICE ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCI_VENDOR_ID_IODATA 0x10fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_VENDOR_ID_WORKBIT 0x1145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * MODEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODEL_IODATA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODEL_KME = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODEL_WORKBIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODEL_LOGITEC = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODEL_PCI_WORKBIT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODEL_PCI_LOGITEC = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODEL_PCI_MELCO = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static char * nsp32_model[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "I-O DATA CBSC-II CardBus card",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "KME SCSI CardBus card",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "Workbit duo SCSI CardBus card",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "Logitec CardBus card with external ROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "Workbit / I-O DATA PCI card",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "Logitec PCI card with external ROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "Melco CardBus/PCI card with external ROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * SCSI Generic Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXTENDED_SDTR_LEN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) typedef u32 u32_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) typedef u16 u16_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * BASIC Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifndef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifndef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ASSERT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NEGATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* normal register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Don't access below register with Double Word:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IRQ_STATUS 0x00 /* BASE+00, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define IRQSTATUS_LATCHED_MSG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define IRQSTATUS_LATCHED_IO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define IRQSTATUS_LATCHED_CD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define IRQSTATUS_RESELECT_OCCUER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define IRQSTATUS_TIMER_IRQ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define IRQSTATUS_PCI_IRQ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define PCI_IRQ_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define TIMER_IRQ_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define FIFO_IRQ_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define SCSI_IRQ_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) TIMER_IRQ_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FIFO_IRQ_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SCSI_IRQ_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IRQSTATUS_PHASE_CHANGE_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IRQSTATUS_SCSIRESET_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) IRQSTATUS_TIMER_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IRQSTATUS_FIFO_SHLD_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) IRQSTATUS_PCI_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IRQSTATUS_BMCNTERR_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) IRQSTATUS_AUTOSCSI_IRQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define CB_MMIO_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define CB_IO_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define BM_TEST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define BM_TEST_DIR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define DUAL_EDGE_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define NO_TRANSFER_TO_HOST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define TRANSFER_GO BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define BLIEND_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define BM_START BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define ADVANCED_BM_WRITE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define BM_SINGLE_MODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define FIFO_TRUE_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define FIFO_TRUE_EMPTY BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define ALL_COUNTER_CLR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define FIFOTEST BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TIMER_SET 0x06 /* BASE+06, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define TIMER_CNT_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define TIMER_STOP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define FIFO_REST_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define FIFO_EMPTY_SHLD_FLAG BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define FIFO_FULL_SHLD_FLAG BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define SREQSMPLRATE_RATE0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define SREQSMPLRATE_RATE1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define SAMPLING_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define BUSCTL_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define BUSCTL_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define BUSCTL_DATAOUT_ENB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define BUSCTL_ATN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # define BUSCTL_ACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define BUSCTL_BSY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define AUTODIRECTION BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define ACKENB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLR_COUNTER 0x12 /* BASE+12, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define ACK_COUNTER_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define SREQ_COUNTER_CLR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) # define FIFO_HOST_POINTER_CLR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define FIFO_REST_COUNT_CLR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define BM_COUNTER_CLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define SAVED_ACK_CLR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SREQ_COUNTER_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FIFO_HOST_POINTER_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FIFO_REST_COUNT_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BM_COUNTER_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SAVED_ACK_CLR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define BUSMON_MSG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) # define BUSMON_IO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) # define BUSMON_CD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define BUSMON_BSY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define BUSMON_ACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define BUSMON_REQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define BUSMON_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) # define BUSMON_ATN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define PARITY_CHECK_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # define PARITY_ERROR_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PARITY_STATUS 0x16 /* BASE+16, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) //# define PARITY_CHECK_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define PARITY_ERROR_NORMAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define PARITY_ERROR_LSB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) # define PARITY_ERROR_MSB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RESELECT_ID 0x18 /* BASE+18, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define CLEAR_CDB_FIFO_POINTER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define AUTO_COMMAND_PHASE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) # define AUTOSCSI_START BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) # define AUTOSCSI_RESTART BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) # define AUTO_PARAMETER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) # define AUTO_ATN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) # define AUTO_MSGIN_00_OR_04 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) # define AUTO_MSGIN_02 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # define AUTO_MSGIN_03 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SET_ARBIT 0x1a /* BASE+1a, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define ARBIT_GO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) # define ARBIT_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) //# define ARBIT_GO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) # define ARBIT_WIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) # define ARBIT_FAIL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) # define AUTO_PARAMETER_VALID BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) # define SGT_VALID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SCAM_STATUS 0x24 /* BASE+24, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) # define SCAM_MSG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define SCAM_IO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define SCAM_CD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define SCAM_BSY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define SCAM_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) # define SCAM_XFEROK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) # define SD0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define SD1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define SD2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define SD3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define SD4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define SD5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define SD6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define SD7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BM_CNT 0x38 /* BASE+38, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define BM_COUNT_MASK 0x0001ffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) # define SGTEND BIT(31) /* Last SGT marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define WAIT_REG 0x40 /* Bi only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # define COMMAND_PHASE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define DATA_IN_PHASE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) # define DATA_OUT_PHASE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) # define MSGOUT_PHASE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) # define STATUS_PHASE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) # define ILLEGAL_PHASE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) # define BUS_FREE_OCCUER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) # define MSG_IN_OCCUER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) # define MSG_OUT_OCCUER BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) # define SELECTION_TIMEOUT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) # define MSGIN_00_VALID BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) # define MSGIN_02_VALID BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) # define MSGIN_03_VALID BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) # define MSGIN_04_VALID BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) # define AUTOSCSI_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) # define MV_VALID BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* indexed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) # define CLOCK_2 BIT(0) /* MCLK/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) # define CLOCK_4 BIT(1) /* MCLK/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) # define PCICLK BIT(7) /* PCICLK (33MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define BPWR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # define SENSE BIT(1) /* Read Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) # define LED_ON (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # define LED_OFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) # define IRQSELECT_RESELECT_IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) # define IRQSELECT_SCSIRESET_IRQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) # define IRQSELECT_TIMER_IRQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) # define IRQSELECT_SERR_IRQ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) # define IRQSELECT_PERR_IRQ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) # define IRQSELECT_BMCNTERR_IRQ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) # define OLD_MSG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) # define OLD_IO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) # define OLD_CD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) # define OLD_BUSY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) # define ROM_WRITE_ENB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) # define IO_ACCESS_ENB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) # define ROM_ADR_CLEAR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) # define OEM1 BIT(2) /* OEM select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) # define OPTB BIT(3) /* KME mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) # define OPTC BIT(4) /* KME mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) # define OPTD BIT(5) /* KME mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) # define OPTE BIT(6) /* KME mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) # define OPTF BIT(7) /* Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MISC_RD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) # define DELAYED_BMSTART BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) # define MASTER_TERMINATION_SELECT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) # define BMREQ_NEGATE_TIMING_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) # define AUTOSEL_TIMING_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) # define MISC_MABORT_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) # define BM_CYCLE0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) # define BM_CYCLE1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) # define BM_FRAME_ASSERT_TIMING BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) # define BM_IRDY_ASSERT_TIMING BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) # define BM_SINGLE_BUS_MASTER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) # define MEMRD_CMD0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) # define MEMRD_CMD1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) # define SREQ_EDGH_SELECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) # define REQCNT_UP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) # define ACKCNT_UP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) # define BMADR_UP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) # define BMCNT_UP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) # define SGT_CNT_UP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) # define SCL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) # define ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) # define SDA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Useful Bus Monitor status combinations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define BUSMON_BUS_FREE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * structure for DMA/Scatter Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define NSP32_SG_SIZE SG_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) typedef struct _nsp32_sgtable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* values must be little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32_le addr; /* transfer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32_le len; /* transfer length. BIT(31) is for SGT_END mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } __attribute__ ((packed)) nsp32_sgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) typedef struct _nsp32_sglun {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } __attribute__ ((packed)) nsp32_sglun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Auto parameter mode memory map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* All values must be little endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) typedef struct _nsp32_autoparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 cdb[4 * 0x10]; /* SCSI Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32_le msgout; /* outgoing messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 syncreg; /* sync register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 ackwidth; /* ack width register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 target_id; /* target/host device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 sample_reg; /* hazard killer sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u16_le command_control; /* command control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u16_le transfer_control; /* transfer control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32_le sgt_pointer; /* SG table physical address for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32_le dummy[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * host data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* message in/out buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MSGOUTBUF_MAX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MSGINBUF_MAX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* flag for trans_method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define NSP32_TRANSFER_BUSMASTER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * structure for connected LUN dynamic data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * one SCSI command and one state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) typedef struct _nsp32_lunt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int msgin03; /* auto msg in 03 flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int sg_num; /* Total number of SG entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int cur_entry; /* Current SG entry number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) nsp32_sglun *sglun; /* sg table per lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dma_addr_t sglun_paddr; /* sglun physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } nsp32_lunt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * SCSI TARGET/LUN definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MAX_TARGET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) typedef struct _nsp32_sync_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned char period_num; /* period number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned char ackwidth; /* ack width designated by period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned char start_period; /* search range - start period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned char end_period; /* search range - end period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned char sample_rate; /* hazard killer parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } nsp32_sync_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * structure for target device static data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* flag for nsp32_target.sync_flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SDTR_TARGET BIT(1) /* sending SDTR from target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* syncronous period value for nsp32_target.config_max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define FAST5M 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define FAST10M 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ULTRA20M 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* flag for nsp32_target.{sync_offset}, period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define ASYNC_OFFSET 0 /* asynchronous transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SYNC_OFFSET 0xf /* synchronous transfer max offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* syncreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) bit:07 06 05 04 03 02 01 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ---PERIOD-- ---OFFSET-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) typedef struct _nsp32_target {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned char syncreg; /* value for SYNCREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned char ackwidth; /* value for ACKWIDTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned char period; /* sync period (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned char offset; /* sync offset (0-15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int sync_flag; /* SDTR_*, 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int limit_entry; /* max speed limit entry designated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) by EEPROM configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned char sample_reg; /* SREQ hazard killer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } nsp32_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) typedef struct _nsp32_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int IrqNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int BaseAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int NumAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void __iomem *MmioAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define NSP32_MMIO_OFFSET 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned long MmioLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct scsi_cmnd *CurrentSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct pci_dev *Pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const struct pci_device_id *pci_devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct Scsi_Host *Host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) spinlock_t Lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) char info_str[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* allocated memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) nsp32_sglun *sg_list; /* sglist virtuxal address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dma_addr_t sg_paddr; /* physical address of hw_sg_table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) nsp32_autoparam *autoparam; /* auto parameter transfer region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dma_addr_t auto_paddr; /* physical address of autoparam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int cur_entry; /* current sgt entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* target/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) nsp32_lunt *cur_lunt; /* Current connected LUN table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) nsp32_target *cur_target; /* Current connected SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) nsp32_target target[MAX_TARGET]; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int cur_id; /* Current connected target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int cur_lun; /* Current connected target LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* behavior setting parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int trans_method; /* transfer method flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int resettime; /* Reset time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int clock; /* clock dividing flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) nsp32_sync_table *synct; /* sync_table determined by clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int syncnum; /* the max number of synct element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* message buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) char msgout_len; /* msgoutbuf length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) char msgin_len; /* msginbuf length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } nsp32_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * TIME definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) minimum is 25us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) (25.6us/1unit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define ARBIT_TIMEOUT_TIME 100 /* 100us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) or negation, 10000us == 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif /* _NSP32_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* end */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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