^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** Device driver for the PCI-SCSI NCR538XX controller family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** Copyright (C) 1994 Wolfgang Stanglmeier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** and is currently maintained by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** Gerard Roudier <groudier@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** Being given that this driver originates from the FreeBSD version, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** in order to keep synergy on both, any suggested enhancements and corrections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** received on Linux are automatically a potential candidate for the FreeBSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** The original driver has been written for 386bsd and FreeBSD by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** Wolfgang Stanglmeier <wolf@cologne.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** Stefan Esser <se@mi.Uni-Koeln.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** And has been ported to NetBSD by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** NVRAM detection and reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ** Added support for MIPS big endian systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** Added support for HP PARISC big endian systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef NCR53C8XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NCR53C8XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ** If you want a driver as small as possible, donnot define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ** following options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCSI_NCR_DEBUG_INFO_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ** To disable integrity checking, do not define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ** following option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ** Take into account kernel configured parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ** Most of these options can be overridden at startup by a command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ** ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * For Ultra2 and Ultra3 SCSI support option, use special features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Value (default) means:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * bit 0 : all features enabled, except:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * bit 1 : PCI Write And Invalidate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * bit 2 : Data Phase Mismatch handling from SCRIPTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * enabled by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCSI_NCR_MAX_SYNC (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Allow tags from 2 to 256, default 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCSI_NCR_MAX_TAGS (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCSI_NCR_MAX_TAGS (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCSI_NCR_MAX_TAGS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Allow tagged command queuing support if configured with default number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * of tags set to max (see above).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Immediate arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCSI_NCR_IARB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Sync transfer frequency at startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Allow from 5Mhz to 80Mhz default 20 Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #undef CONFIG_SCSI_NCR53C8XX_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Disallow disconnections at boot-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SCSI_NCR_SETUP_DISCONNECTION (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SCSI_NCR_SETUP_DISCONNECTION (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Force synchronous negotiation for all targets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Disable master parity checking (flawed hardwares need that)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SCSI_NCR_SETUP_MASTER_PARITY (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SCSI_NCR_SETUP_MASTER_PARITY (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Disable scsi parity checking (flawed devices may need that)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SCSI_NCR_SETUP_SCSI_PARITY (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SCSI_NCR_SETUP_SCSI_PARITY (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Settle time after reset at boot-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SCSI_NCR_SETUP_SETTLE_TIME (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ** Bridge quirks work-around option defaulted to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ** Work-around common bridge misbehaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ** - Do not flush posted writes in the opposite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ** direction on read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ** - May reorder DMA writes to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ** This option should not affect performances
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ** significantly, so it is the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ** Same as option 1, but also deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ** misconfigured interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ** - Edge triggered instead of level sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ** - No interrupt line connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ** - IRQ number misconfigured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ** If no interrupt is delivered, the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ** catch the interrupt conditions 10 times per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ** second. No need to say that this option is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ** not recommended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCSI_NCR_PCIQ_BROKEN_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ** Some bridge designers decided to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ** everything prior to deliver the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ** This option tries to deal with such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ** behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SCSI_NCR_PCIQ_SYNC_ON_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ** Other parameters not configurable with "make config"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ** Avoid to change these constants, unless you know what you are doing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SCSI_NCR_ALWAYS_SIMPLE_TAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SCSI_NCR_MAX_SCATTER (127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SCSI_NCR_MAX_TARGET (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ** Compute some desirable value for CAN_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ** and CMD_PER_LUN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ** The driver will use lower values if these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ** ones appear to be too large.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SCSI_NCR_TIMER_INTERVAL (HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SCSI_NCR_MAX_LUN (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * IO functions definition for big/little endian CPU support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * For now, the NCR is only supported in little endian addressing mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define inw_l2b inw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define inl_l2b inl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define outw_b2l outw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define outl_b2l outl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define readb_raw readb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define writeb_raw writeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #if defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define readw_l2b __raw_readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define readl_l2b __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define writew_b2l __raw_writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define writel_b2l __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define readw_raw __raw_readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define readl_raw __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define writew_raw __raw_writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define writel_raw __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #else /* Other big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define readw_l2b readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define readl_l2b readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define writew_b2l writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define writel_b2l writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define readw_raw readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define readl_raw readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define writew_raw writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define writel_raw writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else /* little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define inw_raw inw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define inl_raw inl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define outw_raw outw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define outl_raw outl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define readb_raw readb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define readw_raw readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define readl_raw readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define writeb_raw writeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define writew_raw writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define writel_raw writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #if !defined(__hppa__) && !defined(__mips__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MEMORY_BARRIER() mb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * If the NCR uses big endian addressing mode over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * PCI, actual io register addresses for byte and word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * accesses must be changed according to lane routing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Btw, ncr_offb() and ncr_offw() macros only apply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * constants and so donnot generate bloated code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #if defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ncr_offb(o) (o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ncr_offw(o) (o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * If the CPU and the NCR use same endian-ness addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * no byte reordering is needed for script patching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Macro cpu_to_scr() is to be used for script patching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Macro scr_to_cpu() is to be used for getting a DWORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * from the script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define cpu_to_scr(dw) cpu_to_le32(dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define scr_to_cpu(dw) le32_to_cpu(dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define cpu_to_scr(dw) cpu_to_be32(dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define scr_to_cpu(dw) be32_to_cpu(dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define cpu_to_scr(dw) (dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define scr_to_cpu(dw) (dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Access to the controller chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * If the CPU and the NCR use same endian-ness addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * no byte reordering is needed for accessing chip io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * registers. Functions suffixed by '_raw' are assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * to access the chip over the PCI without doing byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * reordering. Functions suffixed by '_l2b' are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * assumed to perform little-endian to big-endian byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * reordering, those suffixed by '_b2l' blah, blah,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * blah, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * MEMORY mapped IO input / output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Only 8 or 32 bit transfers allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Only 8 or 32 bit transfers allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Set bit field ON, OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define OUTONB(r, m) OUTB(r, INB(r) | (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define OUTONW(r, m) OUTW(r, INW(r) | (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define OUTONL(r, m) OUTL(r, INL(r) | (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * We normally want the chip to have a consistent view
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * of driver internal data structures when we restart it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Thus these macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define OUTL_DSP(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MEMORY_BARRIER(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) OUTL (nc_dsp, (v)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define OUTONB_STD() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MEMORY_BARRIER(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) OUTONB (nc_dcntl, (STD|NOCOM)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ** NCR53C8XX devices features table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct ncr_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned short revision_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned char burst_max; /* log-base-2 of max burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned char offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned char nr_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define FE_LED0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define FE_WIDE (1<<1) /* Wide data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define FE_DBLR (1<<4) /* Clock doubler present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FE_QUAD (1<<5) /* Clock quadrupler present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define FE_ERL (1<<6) /* Enable read line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define FE_CLSE (1<<7) /* Cache line size enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FE_WRIE (1<<8) /* Write & Invalidate enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define FE_ERMP (1<<9) /* Enable read multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define FE_BOF (1<<10) /* Burst opcode fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define FE_DFS (1<<11) /* DMA fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define FE_PFEN (1<<12) /* Prefetch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define FE_LDSTR (1<<13) /* Load/Store supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define FE_RAM (1<<14) /* On chip RAM present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define FE_VARCLK (1<<15) /* SCSI clock may vary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FE_LEDC (1<<20) /* Hardware control of LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define FE_DIFF (1<<21) /* Support Differential SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define FE_EHP (1<<27) /* 720: Even host parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FE_MUX (1<<28) /* 720: Multiplexed bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FE_EA (1<<29) /* 720: Enable Ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ** Driver setup structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ** This structure is initialized from linux config options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ** It can be overridden at boot-up by the boot command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SCSI_NCR_MAX_EXCLUDES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct ncr_driver_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 master_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 scsi_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 disconnection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 special_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 force_sync_nego;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 reverse_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 pci_fix_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 use_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 default_tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u16 default_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u16 debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 burst_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 led_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u8 max_wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 settle_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u8 diff_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 irqm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 bus_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 optimize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 host_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u16 iarb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 excludes[SCSI_NCR_MAX_EXCLUDES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) char tag_ctrl[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ** Initial setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ** Can be overridden at startup by a command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SCSI_NCR_DRIVER_SETUP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SCSI_NCR_SETUP_MASTER_PARITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SCSI_NCR_SETUP_SCSI_PARITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SCSI_NCR_SETUP_DISCONNECTION, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SCSI_NCR_SETUP_SPECIAL_FEATURES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SCSI_NCR_SETUP_DEFAULT_TAGS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SCSI_NCR_SETUP_DEFAULT_SYNC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x00, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SCSI_NCR_SETUP_SETTLE_TIME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 255, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x00 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ** Boot fail safe setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ** Override initial setup from boot command line:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ** ncr53c8xx=safe:y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SCSI_NCR_DRIVER_SAFE_SETUP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 255, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0x00, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 255, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 255 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ** The ncr 53c810 register structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) **-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct ncr_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*01*/ u8 nc_scntl1; /* no reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define ISCON 0x10 /* connected to scsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define CRST 0x08 /* force reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define IARB 0x02 /* immediate arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*02*/ u8 nc_scntl2; /* no disconnect expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SDU 0x80 /* cmd: disconnect will raise error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define CHM 0x40 /* sta: chained mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define WSS 0x08 /* sta: wide scsi send [W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define WSR 0x01 /* sta: wide scsi received [W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define EWS 0x08 /* cmd: enable wide scsi [W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ULTRA 0x80 /* cmd: ULTRA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* bits 0-2, 7 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define RRE 0x40 /* r/w:e enable response to resel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SRE 0x20 /* r/w:e enable response to select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* bits 6-7 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*06*/ u8 nc_sdid; /* ### Destination-ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*08*/ u8 nc_sfbr; /* ### First byte in phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*09*/ u8 nc_socl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define CREQ 0x80 /* r/w: SCSI-REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define CACK 0x40 /* r/w: SCSI-ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define CBSY 0x20 /* r/w: SCSI-BSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define CSEL 0x10 /* r/w: SCSI-SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define CATN 0x08 /* r/w: SCSI-ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CMSG 0x04 /* r/w: SCSI-MSG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define CC_D 0x02 /* r/w: SCSI-C_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define CI_O 0x01 /* r/w: SCSI-I_O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*0a*/ u8 nc_ssid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*0b*/ u8 nc_sbcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*0c*/ u8 nc_dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DFE 0x80 /* sta: dma fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define MDPE 0x40 /* int: master data parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define BF 0x20 /* int: script: bus fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define ABRT 0x10 /* int: script: command aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SSI 0x08 /* int: script: single step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SIR 0x04 /* int: script: interrupt instruct. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define IID 0x01 /* int: script: illegal instruct. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*0d*/ u8 nc_sstat0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define ILF 0x80 /* sta: data in SIDL register lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define ORF 0x40 /* sta: data in SODR register lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define OLF 0x20 /* sta: data in SODL register lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define AIP 0x10 /* sta: arbitration in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define LOA 0x08 /* sta: arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define WOA 0x04 /* sta: arbitration won */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define IRST 0x02 /* sta: scsi reset signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SDP 0x01 /* sta: scsi parity signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*0e*/ u8 nc_sstat1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*0f*/ u8 nc_sstat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define LDSC 0x02 /* sta: disconnect & reconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*10*/ u8 nc_dsa; /* --> Base page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*11*/ u8 nc_dsa1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*12*/ u8 nc_dsa2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*13*/ u8 nc_dsa3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*14*/ u8 nc_istat; /* --> Main Command and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define CABRT 0x80 /* cmd: abort current operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SRST 0x40 /* mod: reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SIGP 0x20 /* r/w: message from host to ncr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define SEM 0x10 /* r/w: message between host + ncr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define CON 0x08 /* sta: connected to scsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SIP 0x02 /* sta: scsi-interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define DIP 0x01 /* sta: host/script interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*15*/ u8 nc_istat1; /* 896 and later cores only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define FLSH 0x04 /* sta: chip is flushing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define SRUN 0x02 /* sta: scripts are running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define SIRQD 0x01 /* r/w: disable INT pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*16*/ u8 nc_mbox0; /* 896 and later cores only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*17*/ u8 nc_mbox1; /* 896 and later cores only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*18*/ u8 nc_ctest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define EHP 0x04 /* 720 even host parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*19*/ u8 nc_ctest1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*1a*/ u8 nc_ctest2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define CSIGP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* bits 0-2,7 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*1b*/ u8 nc_ctest3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define FLF 0x08 /* cmd: flush dma fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define CLF 0x04 /* cmd: clear dma fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define FM 0x02 /* mod: fetch pin mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define WRIE 0x01 /* mod: write and invalidate enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* bits 4-7 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*1c*/ u32 nc_temp; /* ### Temporary stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*20*/ u8 nc_dfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*21*/ u8 nc_ctest4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define MUX 0x80 /* 720 host bus multiplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define BDIS 0x80 /* mod: burst disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define MPEE 0x08 /* mod: master parity error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*22*/ u8 nc_ctest5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define DFS 0x20 /* mod: dma fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* bits 0-1, 3-7 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*23*/ u8 nc_ctest6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*24*/ u32 nc_dbc; /* ### Byte count and command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*28*/ u32 nc_dnad; /* ### Next command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*2c*/ u32 nc_dsp; /* --> Script Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*34*/ u8 nc_scratcha; /* Temporary register a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*35*/ u8 nc_scratcha1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*36*/ u8 nc_scratcha2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*37*/ u8 nc_scratcha3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /*38*/ u8 nc_dmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define BL_2 0x80 /* mod: burst length shift value +2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define BL_1 0x40 /* mod: burst length shift value +1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define ERL 0x08 /* mod: enable read line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define ERMP 0x04 /* mod: enable read multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define BOF 0x02 /* mod: burst op code fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*39*/ u8 nc_dien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*3a*/ u8 nc_sbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*3b*/ u8 nc_dcntl; /* --> Script execution control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define CLSE 0x80 /* mod: cache line size enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define PFF 0x40 /* cmd: pre-fetch flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define PFEN 0x20 /* mod: pre-fetch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define EA 0x20 /* mod: 720 enable-ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SSM 0x10 /* mod: single step mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define STD 0x04 /* cmd: start dma mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define IRQD 0x02 /* mod: irq disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* bits 0-1 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*3c*/ u32 nc_adder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*40*/ u16 nc_sien; /* -->: interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*42*/ u16 nc_sist; /* <--: interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define STO 0x0400/* sta: timeout (select) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define GEN 0x0200/* sta: timeout (general) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define HTH 0x0100/* sta: timeout (handshake) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MA 0x80 /* sta: phase mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define CMP 0x40 /* sta: arbitration complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define SEL 0x20 /* sta: selected by another device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define RSL 0x10 /* sta: reselected by another device*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SGE 0x08 /* sta: gross error (over/underflow)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define UDC 0x04 /* sta: unexpected disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define RST 0x02 /* sta: scsi bus reset detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define PAR 0x01 /* sta: scsi parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*44*/ u8 nc_slpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*45*/ u8 nc_swide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*46*/ u8 nc_macntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*47*/ u8 nc_gpcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*4c*/ u8 nc_stest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*4d*/ u8 nc_stest1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define DBLEN 0x08 /* clock doubler running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DBLSEL 0x04 /* clock doubler selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*4e*/ u8 nc_stest2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define ROF 0x40 /* reset scsi offset (after gross error!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define DIF 0x20 /* 720 SCSI differential mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define EXT 0x02 /* extended filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*4f*/ u8 nc_stest3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define TE 0x80 /* c: tolerAnt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define HSC 0x20 /* c: Halt SCSI Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define CSF 0x02 /* c: clear scsi fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /*52*/ u8 nc_stest4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SMODE_HVD 0x40 /* High Voltage Differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SMODE_SE 0x80 /* Single Ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SMODE_LVD 0xc0 /* Low Voltage Differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* bits 0-5 rsvd for C1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*53*/ u8 nc_53_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define ENNDJ 0x20 /* Enable Non Data PM Jump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DISFC 0x10 /* Disable Auto FIFO Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DILS 0x02 /* Disable Internal Load/Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DPR 0x01 /* Disable Pipe Req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define ZMOD 0x80 /* High Impedance Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define DIC 0x10 /* Disable Internal Cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define DDAC 0x08 /* Disable Dual Address Cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /*5a*/ u16 nc_5a_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*5c*/ u8 nc_scr0; /* Working register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*5d*/ u8 nc_scr1; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*5e*/ u8 nc_scr2; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*5f*/ u8 nc_scr3; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*60*/ u8 nc_scrx[64]; /* Working register C-R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*ac*/ u32 nc_drs; /* DSA Relative Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*bc*/ u16 nc_scntl4; /* C1010 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define U3EN 0x80 /* Enable Ultra 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define AIPEN 0x40 /* Allow check upper byte lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) transfer edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) transfer edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*c9*/ u8 nc_rbc1; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*ca*/ u8 nc_rbc2; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*cb*/ u8 nc_rbc3; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /*cc*/ u8 nc_ua; /* Updated Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*cd*/ u8 nc_ua1; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*ce*/ u8 nc_ua2; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*cf*/ u8 nc_ua3; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*d0*/ u32 nc_esa; /* Entry Storage Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*d4*/ u8 nc_ia; /* Instruction Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*d5*/ u8 nc_ia1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /*d6*/ u8 nc_ia2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*d7*/ u8 nc_ia3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Following for C1010 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*e0*/ u16 nc_crcpad; /* CRC Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*e2*/ u8 nc_crccntl0; /* CRC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SNDCRC 0x10 /* Send CRC Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*e3*/ u8 nc_crccntl1; /* CRC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /*e4*/ u32 nc_crcdata; /* CRC data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*e8*/ u32 nc_e8_; /* rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*ec*/ u32 nc_ec_; /* rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ** Utility macros for the script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define REG(r) REGJ (nc_, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) typedef u32 ncrcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ** SCSI phases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ** DT phases illegal for ncr driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define SCR_DATA_OUT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define SCR_DATA_IN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SCR_COMMAND 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define SCR_STATUS 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define SCR_DT_DATA_OUT 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define SCR_DT_DATA_IN 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define SCR_MSG_OUT 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define SCR_MSG_IN 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define SCR_ILG_OUT 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SCR_ILG_IN 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ** Data transfer via SCSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ** MOVE_ABS (LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ** <<start address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ** MOVE_IND (LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ** <<dnad_offset>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ** MOVE_TBL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ** <<dnad_offset>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define OPC_MOVE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define SCR_CHMOV_TBL (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct scr_tblmove {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ** Selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ** <<alternate_address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ** <<alternate_address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define SCR_SEL_ABS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define SCR_SEL_ABS_ATN 0x41000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define SCR_SEL_TBL 0x42000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define SCR_SEL_TBL_ATN 0x43000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct scr_tblsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u8 sel_scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 sel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u8 sel_sxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u8 sel_scntl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct scr_tblsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u8 sel_scntl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u8 sel_sxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 sel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u8 sel_scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define SCR_JMP_REL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define SCR_ID(id) (((u32)(id)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ** Waiting for Disconnect or Reselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ** WAIT_DISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ** dummy: <<alternate_address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ** WAIT_RESEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ** <<alternate_address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define SCR_WAIT_DISC 0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define SCR_WAIT_RESEL 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ** Bit Set / Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ** SET (flags {|.. })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ** CLR (flags {|.. })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define SCR_SET(f) (0x58000000 | (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define SCR_CLR(f) (0x60000000 | (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define SCR_CARRY 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define SCR_TRG 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define SCR_ACK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define SCR_ATN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ** Memory to memory move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ** COPY (bytecount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ** << source_address >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ** << destination_address >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ** SCR_COPY sets the NO FLUSH option by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ** SCR_COPY_F does not set this option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ** For chips which do not support this option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ** ncr_copy_and_bind() will remove this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define SCR_NO_FLUSH 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SCR_COPY_F(n) (0xc0000000 | (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ** Register move and binary operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ** SFBR_REG (reg, op, data) reg = SFBR op data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ** REG_SFBR (reg, op, data) SFBR = reg op data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ** REG_REG (reg, op, data) reg = reg op data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ** On 810A, 860, 825A, 875, 895 and 896 chips the content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ** of SFBR register can be used as data (SCR_SFBR_DATA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ** The 896 has additional IO registers starting at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ** offset 0x80. Bit 7 of register offset is stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ** bit 7 of the SCRIPTS instruction first DWORD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define SCR_SFBR_REG(reg,op,data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SCR_REG_SFBR(reg,op,data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SCR_REG_REG(reg,op,data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SCR_LOAD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define SCR_SHL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define SCR_OR 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define SCR_XOR 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define SCR_AND 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define SCR_SHR 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define SCR_ADD 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define SCR_ADDC 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ** FROM_REG (reg) SFBR = reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ** TO_REG (reg) reg = SFBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ** LOAD_REG (reg, data) reg = <data>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ** LOAD_SFBR(data) SFBR = <data>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ** << 0 >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define SCR_FROM_REG(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) SCR_REG_SFBR(reg,SCR_OR,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define SCR_TO_REG(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SCR_SFBR_REG(reg,SCR_OR,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define SCR_LOAD_REG(reg,data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) SCR_REG_REG(reg,SCR_LOAD,data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define SCR_LOAD_SFBR(data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ** LOAD from memory to register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ** STORE from register to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ** Only supported by 810A, 860, 825A, 875, 895 and 896.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ** LOAD_ABS (LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ** <<start address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ** LOAD_REL (LEN) (DSA relative)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ** <<dsa_offset>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SCR_NO_FLUSH2 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SCR_DSA_REL2 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SCR_LOAD_R(reg, how, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SCR_STORE_R(reg, how, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ** Waiting for Disconnect or Reselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ** <<address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ** <<distance>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ** <<address>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ** <<distance>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ** <<dummy>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ** INT [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ** <<ident>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ** <<ident>>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ** Conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ** WHEN (phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ** IF (phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ** CARRYSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ** DATA (data, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define SCR_NO_OP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define SCR_JUMP 0x80080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define SCR_JUMP64 0x80480000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define SCR_JUMPR 0x80880000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define SCR_CALL 0x88080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define SCR_CALLR 0x88880000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define SCR_RETURN 0x90080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define SCR_INT 0x98080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define SCR_INT_FLY 0x98180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define IFFALSE(arg) (0x00080000 | (arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define IFTRUE(arg) (0x00000000 | (arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define WHEN(phase) (0x00030000 | (phase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define IF(phase) (0x00020000 | (phase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define DATA(D) (0x00040000 | ((D) & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define CARRYSET (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ** SCSI constants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ** Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define S_GOOD (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define S_CHECK_COND (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define S_COND_MET (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define S_BUSY (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define S_INT (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define S_INT_COND_MET (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define S_CONFLICT (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define S_TERMINATED (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define S_QUEUE_FULL (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define S_ILLEGAL (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define S_SENSE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * End of ncrreg from FreeBSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) Build a scatter/gather entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) implementation ;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define ncr_build_sge(np, data, badd, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) (data)->addr = cpu_to_scr(badd); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) (data)->size = cpu_to_scr(len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ** Structures used by the detection routine to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ** device configuration to the attach function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct ncr_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) u_long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u_long base_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u_long base_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u_long base_2_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) void __iomem *base_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) void __iomem *base_2_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* port and reg fields to use INB, OUTB macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) volatile struct ncr_reg __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ** Structure used by detection routine to save data on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ** each detected board for attach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct ncr_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct ncr_slot slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct ncr_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) u_char host_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u8 differential;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) extern void ncr53c8xx_release(struct Scsi_Host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) irqreturn_t ncr53c8xx_intr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) extern int ncr53c8xx_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) extern void ncr53c8xx_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #endif /* NCR53C8XX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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