^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** Device driver for the PCI-SCSI NCR538XX controller family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** Copyright (C) 1994 Wolfgang Stanglmeier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) **-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** and is currently maintained by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** Gerard Roudier <groudier@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** Being given that this driver originates from the FreeBSD version, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** in order to keep synergy on both, any suggested enhancements and corrections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** received on Linux are automatically a potential candidate for the FreeBSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** The original driver has been written for 386bsd and FreeBSD by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** Wolfgang Stanglmeier <wolf@cologne.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** Stefan Esser <se@mi.Uni-Koeln.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** And has been ported to NetBSD by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) **-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ** Brief history
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ** December 10 1995 by Gerard Roudier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** Initial port to Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** June 23 1996 by Gerard Roudier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** Support for 64 bits architectures (Alpha).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** November 30 1996 by Gerard Roudier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** Support for Fast-20 scsi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ** Support for large DMA fifo and 128 dwords bursting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ** February 27 1997 by Gerard Roudier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ** Support for Fast-40 scsi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ** Support for on-Board RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ** May 3 1997 by Gerard Roudier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ** Full support for scsi scripts instructions pre-fetching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ** May 19 1997 by Richard Waltham <dormouse@farsrobt.demon.co.uk>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ** Support for NvRAM detection and reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ** August 18 1997 by Cort <cort@cs.nmt.edu>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ** Support for Power/PC (Big Endian).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ** June 20 1998 by Gerard Roudier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ** Support for up to 64 tags per lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ** O(1) everywhere (C and SCRIPTS) for normal cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ** Low PCI traffic for command handling when on-chip RAM is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ** Aggressive SCSI SCRIPTS optimizations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ** 2005 by Matthew Wilcox and James Bottomley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ** PCI-ectomy. This driver now supports only the 720 chip (see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ** NCR_Q720 and zalon drivers for the bus probe logic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ** Supported SCSI-II features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ** Synchronous negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ** Wide negotiation (depends on the NCR Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ** Enable disconnection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ** Tagged command queuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ** Parity checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ** Etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ** Supported NCR/SYMBIOS chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ** 53C720 (Wide, Fast SCSI-2, intfly problems)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Name and version of the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCSI_NCR_DRIVER_NAME "ncr53c8xx-3.4.3g"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCSI_NCR_DEBUG_FLAGS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #include <scsi/scsi_dbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #include <scsi/scsi_transport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #include <scsi/scsi_transport_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #include "ncr53c8xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NAME53C8XX "ncr53c8xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ** Debugging tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DEBUG_ALLOC (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DEBUG_PHASE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DEBUG_QUEUE (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DEBUG_RESULT (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DEBUG_POINTER (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DEBUG_SCRIPT (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DEBUG_TINY (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DEBUG_TIMING (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DEBUG_NEGO (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DEBUG_TAGS (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DEBUG_SCATTER (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DEBUG_IC (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ** Enable/Disable debug messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ** Can be changed at runtime too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef SCSI_NCR_DEBUG_INFO_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ncr_debug = SCSI_NCR_DEBUG_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DEBUG_FLAGS ncr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DEBUG_FLAGS SCSI_NCR_DEBUG_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline struct list_head *ncr_list_pop(struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!list_empty(head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct list_head *elem = head->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) list_del(elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ** Simple power of two buddy-like allocator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ** This simple code is not intended to be fast, but to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ** provide power of 2 aligned memory allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ** Since the SCRIPTS processor only supplies 8 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ** arithmetic, this allocator allows simple and fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ** address calculations from the SCRIPTS code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ** In addition, cache line alignment is guaranteed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ** power of 2 cache line size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ** Enhanced in linux-2.3.44 to provide a memory pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ** per pcidev to support dynamic dma mapping. (I would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ** have preferred a real bus abstraction, btw).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #if PAGE_SIZE >= 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MEMO_PAGE_ORDER 1 /* 2 PAGES maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MEMO_FREE_UNUSED /* Free unused pages immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MEMO_WARN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MEMO_GFP_FLAGS GFP_ATOMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) typedef struct device *m_bush_t; /* Something that addresses DMAable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) typedef struct m_link { /* Link between free memory chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct m_link *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } m_link_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) typedef struct m_vtob { /* Virtual to Bus address translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct m_vtob *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) m_addr_t vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) m_addr_t baddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } m_vtob_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define VTOB_HASH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define VTOB_HASH_CODE(m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) typedef struct m_pool { /* Memory pool of a given kind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) m_bush_t bush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) m_addr_t (*getp)(struct m_pool *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void (*freep)(struct m_pool *, m_addr_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) m_vtob_s *(vtob[VTOB_HASH_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct m_pool *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct m_link h[PAGE_SHIFT-MEMO_SHIFT+MEMO_PAGE_ORDER+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } m_pool_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void *___m_alloc(m_pool_s *mp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int s = (1 << MEMO_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) m_addr_t a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) m_link_s *h = mp->h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) while (size > s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) s <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) j = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) while (!h[j].next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) h[j].next = (m_link_s *)mp->getp(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (h[j].next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) h[j].next->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ++j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) s <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) a = (m_addr_t) h[j].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) h[j].next = h[j].next->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) while (j > i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) j -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) s >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) h[j].next = (m_link_s *) (a+s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) h[j].next->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) printk("___m_alloc(%d) = %p\n", size, (void *) a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return (void *) a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void ___m_free(m_pool_s *mp, void *ptr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int s = (1 << MEMO_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) m_link_s *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) m_addr_t a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) m_link_s *h = mp->h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) printk("___m_free(%p, %d)\n", ptr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (size > s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) s <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) a = (m_addr_t) ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #ifdef MEMO_FREE_UNUSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mp->freep(mp, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) b = a ^ s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) q = &h[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) while (q->next && q->next != (m_link_s *) b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) q = q->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!q->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ((m_link_s *) a)->next = h[i].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) h[i].next = (m_link_s *) a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) q->next = q->next->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) a = a & b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) s <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static DEFINE_SPINLOCK(ncr53c8xx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void *__m_calloc2(m_pool_s *mp, int size, char *name, int uflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) p = ___m_alloc(mp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (DEBUG_FLAGS & DEBUG_ALLOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) printk ("new %-10s[%4d] @%p.\n", name, size, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) memset(p, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (uflags & MEMO_WARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) printk (NAME53C8XX ": failed to allocate %s[%d]\n", name, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define __m_calloc(mp, s, n) __m_calloc2(mp, s, n, MEMO_WARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void __m_free(m_pool_s *mp, void *ptr, int size, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (DEBUG_FLAGS & DEBUG_ALLOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) printk ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ___m_free(mp, ptr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * With pci bus iommu support, we use a default pool of unmapped memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * for memory we donnot need to DMA from/to and one pool per pcidev for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * memory accessed by the PCI chip. `mp0' is the default not DMAable pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static m_addr_t ___mp0_getp(m_pool_s *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) m_addr_t m = __get_free_pages(MEMO_GFP_FLAGS, MEMO_PAGE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ++mp->nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) free_pages(m, MEMO_PAGE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) --mp->nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static m_pool_s mp0 = {NULL, ___mp0_getp, ___mp0_freep};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * DMAable pools.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * With pci bus iommu support, we maintain one pool per pcidev and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * hashed reverse table for virtual to bus physical address translations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static m_addr_t ___dma_getp(m_pool_s *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) m_addr_t vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) m_vtob_s *vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) vbp = __m_calloc(&mp0, sizeof(*vbp), "VTOB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (vbp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dma_addr_t daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) vp = (m_addr_t) dma_alloc_coherent(mp->bush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PAGE_SIZE<<MEMO_PAGE_ORDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) &daddr, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int hc = VTOB_HASH_CODE(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) vbp->vaddr = vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) vbp->baddr = daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) vbp->next = mp->vtob[hc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mp->vtob[hc] = vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ++mp->nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (vbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void ___dma_freep(m_pool_s *mp, m_addr_t m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) m_vtob_s **vbpp, *vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int hc = VTOB_HASH_CODE(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) vbpp = &mp->vtob[hc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) while (*vbpp && (*vbpp)->vaddr != m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) vbpp = &(*vbpp)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (*vbpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) vbp = *vbpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *vbpp = (*vbpp)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dma_free_coherent(mp->bush, PAGE_SIZE<<MEMO_PAGE_ORDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) --mp->nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static inline m_pool_s *___get_dma_pool(m_bush_t bush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) m_pool_s *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (mp = mp0.next; mp && mp->bush != bush; mp = mp->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static m_pool_s *___cre_dma_pool(m_bush_t bush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) m_pool_s *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mp = __m_calloc(&mp0, sizeof(*mp), "MPOOL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (mp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) memset(mp, 0, sizeof(*mp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mp->bush = bush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mp->getp = ___dma_getp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mp->freep = ___dma_freep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mp->next = mp0.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mp0.next = mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void ___del_dma_pool(m_pool_s *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct m_pool **pp = &mp0.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) while (*pp && *pp != p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pp = &(*pp)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (*pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *pp = (*pp)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __m_free(&mp0, p, sizeof(*p), "MPOOL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void *__m_calloc_dma(m_bush_t bush, int size, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct m_pool *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) void *m = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) spin_lock_irqsave(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mp = ___get_dma_pool(bush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mp = ___cre_dma_pool(bush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) m = __m_calloc(mp, size, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (mp && !mp->nump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ___del_dma_pool(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void __m_free_dma(m_bush_t bush, void *m, int size, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct m_pool *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spin_lock_irqsave(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mp = ___get_dma_pool(bush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __m_free(mp, m, size, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (mp && !mp->nump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ___del_dma_pool(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static m_addr_t __vtobus(m_bush_t bush, void *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) m_pool_s *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int hc = VTOB_HASH_CODE(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) m_vtob_s *vp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) spin_lock_irqsave(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) mp = ___get_dma_pool(bush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (mp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vp = mp->vtob[hc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) while (vp && (m_addr_t) vp->vaddr != a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) vp = vp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define _m_calloc_dma(np, s, n) __m_calloc_dma(np->dev, s, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define _m_free_dma(np, p, s, n) __m_free_dma(np->dev, p, s, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define m_calloc_dma(s, n) _m_calloc_dma(np, s, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define m_free_dma(p, s, n) _m_free_dma(np, p, s, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define _vtobus(np, p) __vtobus(np->dev, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define vtobus(p) _vtobus(np, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Deal with DMA mapping/unmapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* To keep track of the dma mapping (sg/single) that has been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define __data_mapped SCp.phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define __data_mapping SCp.have_data_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void __unmap_scsi_data(struct device *dev, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) switch(cmd->__data_mapped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cmd->__data_mapped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int __map_scsi_sg_data(struct device *dev, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) use_sg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!use_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cmd->__data_mapped = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cmd->__data_mapping = use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define unmap_scsi_data(np, cmd) __unmap_scsi_data(np->dev, cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define map_scsi_sg_data(np, cmd) __map_scsi_sg_data(np->dev, cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ** Driver setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ** This structure is initialized from linux config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ** options. It can be overridden at boot-up by the boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ** command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct ncr_driver_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) driver_setup = SCSI_NCR_DRIVER_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct ncr_driver_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) driver_safe_setup __initdata = SCSI_NCR_DRIVER_SAFE_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #endif /* !MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define initverbose (driver_setup.verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define bootverbose (np->verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*===================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ** Driver setup from the boot command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) **===================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ARG_SEP ' '
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define ARG_SEP ','
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define OPT_TAGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define OPT_MASTER_PARITY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define OPT_SCSI_PARITY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define OPT_DISCONNECTION 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define OPT_SPECIAL_FEATURES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define OPT_UNUSED_1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define OPT_FORCE_SYNC_NEGO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define OPT_REVERSE_PROBE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define OPT_DEFAULT_SYNC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define OPT_VERBOSE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define OPT_DEBUG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define OPT_BURST_MAX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define OPT_LED_PIN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define OPT_MAX_WIDE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define OPT_SETTLE_DELAY 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define OPT_DIFF_SUPPORT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define OPT_IRQM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define OPT_PCI_FIX_UP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define OPT_BUS_CHECK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define OPT_OPTIMIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define OPT_RECOVERY 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define OPT_SAFE_SETUP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define OPT_USE_NVRAM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define OPT_EXCLUDE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define OPT_HOST_ID 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef SCSI_NCR_IARB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define OPT_IARB 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define ARG_SEP ' '
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define ARG_SEP ','
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static char setup_token[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "tags:" "mpar:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "spar:" "disc:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "specf:" "ultra:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "fsn:" "revprob:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "sync:" "verb:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "debug:" "burst:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "led:" "wide:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "settle:" "diff:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "irqm:" "pcifix:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "buschk:" "optim:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "recovery:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "safe:" "nvram:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "excl:" "hostid:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #ifdef SCSI_NCR_IARB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "iarb:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ; /* DONNOT REMOVE THIS ';' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int __init get_setup_token(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) char *cur = setup_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) char *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ++pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!strncmp(p, cur, pc - cur))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cur = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int __init sym53c8xx__setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) char *cur = str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) char *pc, *pv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int i, val, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int xi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) char *pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pv = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) c = *++pv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (c == 'n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else if (c == 'y')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val = (int) simple_strtoul(pv, &pe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (get_setup_token(cur)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case OPT_TAGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) driver_setup.default_tags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (pe && *pe == '/') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) while (*pe && *pe != ARG_SEP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) i < sizeof(driver_setup.tag_ctrl)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) driver_setup.tag_ctrl[i++] = *pe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) driver_setup.tag_ctrl[i] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case OPT_MASTER_PARITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) driver_setup.master_parity = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case OPT_SCSI_PARITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) driver_setup.scsi_parity = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case OPT_DISCONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) driver_setup.disconnection = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case OPT_SPECIAL_FEATURES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) driver_setup.special_features = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case OPT_FORCE_SYNC_NEGO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) driver_setup.force_sync_nego = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case OPT_REVERSE_PROBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) driver_setup.reverse_probe = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case OPT_DEFAULT_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) driver_setup.default_sync = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case OPT_VERBOSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) driver_setup.verbose = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case OPT_DEBUG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) driver_setup.debug = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case OPT_BURST_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) driver_setup.burst_max = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case OPT_LED_PIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) driver_setup.led_pin = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case OPT_MAX_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) driver_setup.max_wide = val? 1:0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case OPT_SETTLE_DELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) driver_setup.settle_delay = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case OPT_DIFF_SUPPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) driver_setup.diff_support = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case OPT_IRQM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) driver_setup.irqm = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case OPT_PCI_FIX_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) driver_setup.pci_fix_up = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case OPT_BUS_CHECK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) driver_setup.bus_check = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case OPT_OPTIMIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) driver_setup.optimize = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case OPT_RECOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) driver_setup.recovery = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case OPT_USE_NVRAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) driver_setup.use_nvram = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case OPT_SAFE_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) memcpy(&driver_setup, &driver_safe_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) sizeof(driver_setup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case OPT_EXCLUDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (xi < SCSI_NCR_MAX_EXCLUDES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) driver_setup.excludes[xi++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case OPT_HOST_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) driver_setup.host_id = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #ifdef SCSI_NCR_IARB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case OPT_IARB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) driver_setup.iarb = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) printk("sym53c8xx_setup: unexpected boot option '%.*s' ignored\n", (int)(pc-cur+1), cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if ((cur = strchr(cur, ARG_SEP)) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ++cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #endif /* SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #endif /* !MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*===================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ** Get device queue depth from boot command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) **===================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define DEF_DEPTH (driver_setup.default_tags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define ALL_TARGETS -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define NO_TARGET -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define ALL_LUNS -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define NO_LUN -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int device_queue_depth(int unit, int target, int lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int c, h, t, u, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) char *p = driver_setup.tag_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) char *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) h = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) t = NO_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u = NO_LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) while ((c = *p++) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) v = simple_strtoul(p, &ep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) switch(c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case '/':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ++h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) t = ALL_TARGETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u = ALL_LUNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case 't':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (t != target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) t = (target == v) ? v : NO_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u = ALL_LUNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case 'u':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (u != lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u = (lun == v) ? v : NO_LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case 'q':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (h == unit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) (t == ALL_TARGETS || t == target) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) (u == ALL_LUNS || u == lun))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case '-':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) t = ALL_TARGETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u = ALL_LUNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) p = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return DEF_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ** The CCB done queue uses an array of CCB virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ** addresses. Empty entries are flagged using the bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ** virtual address 0xffffffff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ** Since PCI ensures that only aligned DWORDs are accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ** atomically, 64 bit little-endian architecture requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ** to test the high order DWORD of the entry to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ** if it is empty or valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ** BTW, I will make things differently as soon as I will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ** have a better idea, but this is simple and should work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define MAX_DONE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define CCB_DONE_EMPTY 0xffffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* All 32 bit architectures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #if BITS_PER_LONG == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define CCB_DONE_VALID(cp) (((u_long) cp) != CCB_DONE_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* All > 32 bit (64 bit) architectures regardless endian-ness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define CCB_DONE_VALID(cp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ((((u_long) cp) & 0xffffffff00000000ul) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (((u_long) cp) & 0xfffffffful) != CCB_DONE_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #endif /* SCSI_NCR_CCB_DONE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ** Configuration and Debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ** SCSI address of this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ** The boot routines should have set it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ** If not, use this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #ifndef SCSI_NCR_MYADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SCSI_NCR_MYADDR (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ** The maximum number of tags per logic unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ** Used only for disk devices that support tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #ifndef SCSI_NCR_MAX_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SCSI_NCR_MAX_TAGS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ** TAGS are actually limited to 64 tags/lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ** We need to deal with power of 2, for alignment constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #if SCSI_NCR_MAX_TAGS > 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MAX_TAGS (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MAX_TAGS SCSI_NCR_MAX_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define NO_TAG (255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ** Choose appropriate type for tag bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #if MAX_TAGS > 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) typedef u64 tagmap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) typedef u32 tagmap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ** Number of targets supported by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ** n permits target numbers 0..n-1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ** Default is 16, meaning targets #0..#15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ** #7 .. is myself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #ifdef SCSI_NCR_MAX_TARGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define MAX_TARGET (SCSI_NCR_MAX_TARGET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define MAX_TARGET (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ** Number of logic units supported by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ** n enables logic unit numbers 0..n-1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ** The common SCSI devices require only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ** one lun, so take 1 as the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #ifdef SCSI_NCR_MAX_LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define MAX_LUN SCSI_NCR_MAX_LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define MAX_LUN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ** Asynchronous pre-scaler (ns). Shall be 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #ifndef SCSI_NCR_MIN_ASYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SCSI_NCR_MIN_ASYNC (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ** The maximum number of jobs scheduled for starting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ** There should be one slot per target, and one slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ** for each tag of each target in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ** The calculation below is actually quite silly ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #ifdef SCSI_NCR_CAN_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define MAX_START (SCSI_NCR_CAN_QUEUE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define MAX_START (MAX_TARGET + 7 * MAX_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ** We limit the max number of pending IO to 250.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ** since we donnot want to allocate more than 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ** PAGE for 'scripth'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #if MAX_START > 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #undef MAX_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define MAX_START 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ** The maximum number of segments a transfer is split into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ** We support up to 127 segments for both read and write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ** The data scripts are broken into 2 sub-scripts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ** 80 (MAX_SCATTERL) segments are moved from a sub-script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ** in on-chip RAM. This makes data transfers shorter than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ** 80k (assuming 1k fs) as fast as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define MAX_SCATTER (SCSI_NCR_MAX_SCATTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #if (MAX_SCATTER > 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define MAX_SCATTERL 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define MAX_SCATTERH (MAX_SCATTER - MAX_SCATTERL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define MAX_SCATTERL (MAX_SCATTER-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define MAX_SCATTERH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ** other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define NCR_SNOOP_TIMEOUT (1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ** Other definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define ScsiResult(host_code, scsi_code) (((host_code) << 16) + ((scsi_code) & 0x7f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define initverbose (driver_setup.verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define bootverbose (np->verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ** Command control block states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define HS_IDLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define HS_BUSY (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define HS_NEGOTIATE (2) /* sync/wide data transfer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define HS_DISCONNECT (3) /* Disconnected by target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define HS_DONEMASK (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define HS_COMPLETE (4|HS_DONEMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define HS_RESET (6|HS_DONEMASK) /* SCSI reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define HS_ABORTED (7|HS_DONEMASK) /* Transfer aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define HS_TIMEOUT (8|HS_DONEMASK) /* Software timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define HS_FAIL (9|HS_DONEMASK) /* SCSI or PCI bus errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define HS_UNEXPECTED (10|HS_DONEMASK)/* Unexpected disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ** Invalid host status values used by the SCRIPTS processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ** when the nexus is not fully identified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ** Shall never appear in a CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define HS_INVALMASK (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define HS_SELECTING (0|HS_INVALMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define HS_IN_RESELECT (1|HS_INVALMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define HS_STARTING (2|HS_INVALMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ** Flags set by the SCRIPT processor for commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ** that have been skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define HS_SKIPMASK (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ** Software Interrupt Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define SIR_BAD_STATUS (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define SIR_XXXXXXXXXX (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define SIR_NEGO_SYNC (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define SIR_NEGO_WIDE (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define SIR_NEGO_FAILED (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define SIR_NEGO_PROTO (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define SIR_REJECT_RECEIVED (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define SIR_REJECT_SENT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SIR_IGN_RESIDUE (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SIR_MISSING_SAVE (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define SIR_RESEL_NO_MSG_IN (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define SIR_RESEL_NO_IDENTIFY (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define SIR_RESEL_BAD_LUN (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SIR_RESEL_BAD_TARGET (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define SIR_RESEL_BAD_I_T_L (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define SIR_RESEL_BAD_I_T_L_Q (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define SIR_DONE_OVERFLOW (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define SIR_INTFLY (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define SIR_MAX (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ** Extended error codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ** xerr_status field of struct ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define XE_OK (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define XE_EXTRA_DATA (1) /* unexpected data phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define XE_BAD_PHASE (2) /* illegal phase (4/5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ** Negotiation status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ** nego_status field of struct ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define NS_NOCHANGE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define NS_SYNC (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define NS_WIDE (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define NS_PPR (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ** Misc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define CCB_MAGIC (0xf2691ad2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ** Declaration of structs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static struct scsi_transport_template *ncr53c8xx_transport_template = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct lcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct script;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ncrcmd l_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ncrcmd l_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct usrcmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u_long target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u_long lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u_long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u_long cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define UC_SETSYNC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define UC_SETTAGS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define UC_SETDEBUG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define UC_SETORDER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define UC_SETWIDE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define UC_SETFLAG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define UC_SETVERBOSE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define UF_TRACE (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define UF_NODISC (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define UF_NOSCAN (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ** Declaration of structs: target control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct tcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ** During reselection the ncr jumps to this point with SFBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ** set to the encoded target number with bit 7 set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ** if it's not this target, jump to the next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ** JUMP IF (SFBR != #target#), @(next tcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct link jump_tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ** Load the actual values for the sxfer and the scntl3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ** register (sync/wide mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ** SCR_COPY (1), @(sval field of this tcb), @(sxfer register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ** SCR_COPY (1), @(wval field of this tcb), @(scntl3 register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ncrcmd getscr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ** Get the IDENTIFY message and load the LUN to SFBR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ** CALL, <RESEL_LUN>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct link call_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ** Now look for the right lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ** For i = 0 to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ** SCR_JUMP ^ IFTRUE(MASK(i, 3)), @(first lcb mod. i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ** Recent chips will prefetch the 4 JUMPS using only 1 burst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ** It is kind of hashcoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct link jump_lcb[4]; /* JUMPs for reselection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct lcb * lp[MAX_LUN]; /* The lcb's of this tcb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ** Pointer to the ccb used for negotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ** Prevent from starting a negotiation for all queued commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ** when tagged command queuing is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct ccb * nego_cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ** statistical data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) u_long transfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u_long bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ** negotiation of wide and synch transfer and device quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*0*/ u16 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*2*/ u_char sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*3*/ u_char minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*0*/ u_char wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*1*/ u_char widedone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*2*/ u_char quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /*3*/ u_char maxoffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /*0*/ u_char minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /*1*/ u_char sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*2*/ u16 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /*0*/ u_char maxoffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*1*/ u_char quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*2*/ u_char widedone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*3*/ u_char wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* User settable limits and options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u_char usrsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u_char usrwide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u_char usrtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u_char usrflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct scsi_target *starget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ** Declaration of structs: lun control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct lcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ** During reselection the ncr jumps to this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ** with SFBR set to the "Identify" message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ** if it's not this lun, jump to the next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ** JUMP IF (SFBR != #lun#), @(next lcb of this target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ** It is this lun. Load TEMP with the nexus jumps table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ** address and jump to RESEL_TAG (or RESEL_NOTAG).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ** SCR_COPY (4), p_jump_ccb, TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ** SCR_JUMP, <RESEL_TAG>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct link jump_lcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ncrcmd load_jump_ccb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct link jump_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ncrcmd p_jump_ccb; /* Jump table bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ** Jump table used by the script processor to directly jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ** to the CCB corresponding to the reselected nexus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ** Address is allocated on 256 bytes boundary in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ** allow 8 bit calculation of the tag jump entry for up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ** 64 possible tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) u32 jump_ccb_0; /* Default table if no tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 *jump_ccb; /* Virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ** CCB queue management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct list_head free_ccbq; /* Queue of available CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct list_head busy_ccbq; /* Queue of busy CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct list_head wait_ccbq; /* Queue of waiting for IO CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct list_head skip_ccbq; /* Queue of skipped CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u_char actccbs; /* Number of allocated CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u_char busyccbs; /* CCBs busy for this lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u_char queuedccbs; /* CCBs queued to the controller*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u_char queuedepth; /* Queue depth for this lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u_char scdev_depth; /* SCSI device queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) u_char maxnxs; /* Max possible nexuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ** Control of tagged command queuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ** Tags allocation is performed using a circular buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ** This avoids using a loop for tag allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) u_char ia_tag; /* Allocation index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) u_char if_tag; /* Freeing index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u_char cb_tags[MAX_TAGS]; /* Circular tags buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u_char usetags; /* Command queuing is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u_char maxtags; /* Max nr of tags asked by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) u_char numtags; /* Current number of tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ** QUEUE FULL control and ORDERED tag control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ** QUEUE FULL and ORDERED tag control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u16 num_good; /* Nr of GOOD since QUEUE FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) tagmap_t tags_umap; /* Used tags bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) tagmap_t tags_smap; /* Tags in use at 'tag_stime' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u_long tags_stime; /* Last time we set smap=umap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct ccb * held_ccb; /* CCB held for QUEUE FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ** Declaration of structs: the launch script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ** It is part of the CCB and is called by the scripts processor to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ** start or restart the data structure (nexus).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ** This 6 DWORDs mini script makes use of prefetching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct launch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ** SCR_COPY(4), @(p_phys), @(dsa register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ** SCR_JUMP, @(scheduler_point)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ncrcmd setup_dsa[3]; /* Copy 'phys' address to dsa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct link schedule; /* Jump to scheduler point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ncrcmd p_phys; /* 'phys' header bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ** Declaration of structs: global HEADER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ** This substructure is copied from the ccb to a global address after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ** selection (or reselection) and copied back before disconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ** These fields are accessible to the script processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct head {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ** Saved data pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ** Points to the position in the script responsible for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ** actual transfer transfer of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ** It's written after reception of a SAVE_DATA_POINTER message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ** The goalpointer points after the last transfer command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 savep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 lastp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u32 goalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ** Alternate data pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ** They are copied back to savep/lastp/goalp by the SCRIPTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ** when the direction is unknown and the device claims data out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 wlastp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) u32 wgoalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ** The virtual address of the ccb containing this header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct ccb * cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ** Status fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u_char scr_st[4]; /* script status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u_char status[4]; /* host status. must be the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* last DWORD of the header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ** The status bytes are used by the host and the script processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ** The byte corresponding to the host_status must be stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ** last DWORD of the CCB header since it is used for command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ** completion (ncr_wakeup()). Doing so, we are sure that the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ** has been entirely copied back to the CCB when the host_status is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ** seen complete by the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ** The last four bytes (status[4]) are copied to the scratchb register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ** and copied back just after disconnecting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ** Inside the script the XX_REG are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ** The first four bytes (scr_st[4]) are used inside the script by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ** "COPY" commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ** Because source and destination must have the same alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ** in a DWORD, the fields HAVE to be at the chosen offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ** xerr_st 0 (0x34) scratcha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ** sync_st 1 (0x05) sxfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ** wide_st 3 (0x03) scntl3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ** Last four bytes (script)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define QU_REG scr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define HS_REG scr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define HS_PRT nc_scr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define SS_REG scr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define SS_PRT nc_scr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define PS_REG scr3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ** Last four bytes (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define actualquirks phys.header.status[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define host_status phys.header.status[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define scsi_status phys.header.status[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define parity_status phys.header.status[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define actualquirks phys.header.status[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define host_status phys.header.status[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define scsi_status phys.header.status[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define parity_status phys.header.status[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ** First four bytes (script)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define xerr_st header.scr_st[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define sync_st header.scr_st[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define nego_st header.scr_st[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define wide_st header.scr_st[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ** First four bytes (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define xerr_status phys.xerr_st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define nego_status phys.nego_st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define sync_status phys.sync_st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define wide_status phys.wide_st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ** Declaration of structs: Data structure block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ** During execution of a ccb by the script processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ** the DSA (data structure address) register points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ** to this substructure of the ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ** This substructure contains the header with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ** the script-processor-changeable data and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ** data blocks for the indirect move commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct dsb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ** Header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct head header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ** Table data for Script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct scr_tblsel select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct scr_tblmove smsg ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct scr_tblmove cmd ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct scr_tblmove sense ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct scr_tblmove data[MAX_SCATTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ** Declaration of structs: Command control block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct ccb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ** This is the data structure which is pointed by the DSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ** register when it is executed by the script processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ** It must be the first entry because it contains the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ** as first entry that must be cache line aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct dsb phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ** Mini-script used at CCB execution start-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ** Load the DSA with the data structure address (phys) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ** jump to SELECT. Jump to CANCEL if CCB is to be canceled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct launch start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ** Mini-script used at CCB relection to restart the nexus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ** Load the DSA with the data structure address (phys) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ** jump to RESEL_DSA. Jump to ABORT if CCB is to be aborted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct launch restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ** If a data transfer phase is terminated too early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ** (after reception of a message (i.e. DISCONNECT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ** we have to prepare a mini script to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ** the rest of the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ncrcmd patch[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) ** The general SCSI driver provides a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ** pointer to a control block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct scsi_cmnd *cmd; /* SCSI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) u_char cdb_buf[16]; /* Copy of CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u_char sense_buf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) int data_len; /* Total data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ** Message areas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ** We prepare a message to be sent after selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ** We may use a second one if the command is rescheduled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ** due to GETCC or QFULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ** Contents are IDENTIFY and SIMPLE_TAG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ** While negotiating sync or wide transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ** a SDTR or WDTR message is appended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) u_char scsi_smsg [8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u_char scsi_smsg2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ** Other fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) u_long p_ccb; /* BUS address of this CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) u_char sensecmd[6]; /* Sense command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) u_char tag; /* Tag for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* 255 means no tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u_char target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) u_char lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u_char queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) u_char auto_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct ccb * link_ccb; /* Host adapter CCB chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) struct list_head link_ccbq; /* Link to unit CCB queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) u32 startp; /* Initial data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u_long magic; /* Free / busy CCB flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define CCB_PHYS(cp,lbl) (cp->p_ccb + offsetof(struct ccb, lbl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /*========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ** Declaration of structs: NCR device descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) **========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct ncb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ** The global header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ** It is accessible to both the host and the script processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ** Must be cache line size aligned (32 for x86) in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ** allow cache line bursting when it is copied to/from CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct head header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ** CCBs management queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct scsi_cmnd *waiting_list; /* Commands waiting for a CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* when lcb is not allocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct scsi_cmnd *done_list; /* Commands waiting for done() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* callback to be invoked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) spinlock_t smp_lock; /* Lock for SMP threading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ** Chip and controller identification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int unit; /* Unit number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) char inst_name[16]; /* ncb instance name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ** Initial value of some IO register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ** These values are assumed to have been set by BIOS, and may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ** be used for probing adapter implementation differences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest0, sv_ctest3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) sv_ctest4, sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ** Actual initial value of IO register bits used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) ** driver. They are loaded at initialisation according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ** features that are to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest0, rv_ctest3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) rv_ctest4, rv_ctest5, rv_stest2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ** Targets management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ** During reselection the ncr jumps to jump_tcb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ** The SFBR register is loaded with the encoded target id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ** For i = 0 to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ** SCR_JUMP ^ IFTRUE(MASK(i, 3)), @(next tcb mod. i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ** Recent chips will prefetch the 4 JUMPS using only 1 burst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ** It is kind of hashcoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct link jump_tcb[4]; /* JUMPs for reselection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct tcb target[MAX_TARGET]; /* Target data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ** Virtual and physical bus addresses of the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) void __iomem *vaddr; /* Virtual and bus address of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) unsigned long paddr; /* chip's IO registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) unsigned long paddr2; /* On-chip RAM bus address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) volatile /* Pointer to volatile for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct ncr_reg __iomem *reg; /* memory mapped IO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ** SCRIPTS virtual and physical bus addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ** 'script' is loaded in the on-chip RAM if present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ** 'scripth' stays in main memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct script *script0; /* Copies of script and scripth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct scripth *scripth0; /* relocated for this ncb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct scripth *scripth; /* Actual scripth virt. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) u_long p_script; /* Actual script and scripth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) u_long p_scripth; /* bus addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ** General controller parameters and configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u_char revision_id; /* PCI device revision id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u32 irq; /* IRQ level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u32 features; /* Chip features map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u_char myaddr; /* SCSI id of the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) u_char maxburst; /* log base 2 of dwords burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u_char maxwide; /* Maximum transfer width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u_char minsync; /* Minimum sync period factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u_char maxsync; /* Maximum sync period factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) u_char maxoffs; /* Max scsi offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u_char multiplier; /* Clock multiplier (1,2,4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u_char clock_divn; /* Number of clock divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u_long clock_khz; /* SCSI clock frequency in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ** Start queue management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ** It is filled up by the host processor and accessed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ** SCRIPTS processor in order to start SCSI commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u16 squeueput; /* Next free slot of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u16 actccbs; /* Number of allocated CCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) u16 queuedccbs; /* Number of CCBs in start queue*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) u16 queuedepth; /* Start queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ** Timeout handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct timer_list timer; /* Timer handler link header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u_long lasttime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u_long settle_time; /* Resetting the SCSI BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ** Debugging and profiling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct ncr_reg regdump; /* Register dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) u_long regtime; /* Time it has been done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ** Miscellaneous buffers accessed by the scripts-processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ** They shall be DWORD aligned, because they may be read or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ** written with a SCR_COPY script command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) u_char msgout[8]; /* Buffer for MESSAGE OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) u_char msgin [8]; /* Buffer for MESSAGE IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) u32 lastmsg; /* Last SCSI message sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u_char scratch; /* Scratch for SCSI receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ** Miscellaneous configuration and status parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) u_char disc; /* Disconnection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) u_char scsi_mode; /* Current SCSI BUS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) u_char order; /* Tag order to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) u_char verbose; /* Verbosity for this controller*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) int ncr_cache; /* Used for cache test at init. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u_long p_ncb; /* BUS address of this NCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ** Command completion handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct ccb *(ccb_done[MAX_DONE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) int ccb_done_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /*----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ** Fields that should be removed or changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) **----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct ccb *ccb; /* Global CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct usrcmd user; /* Command from user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) volatile u_char release_stage; /* Synchronisation stage on release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) ** Script for NCR-Processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ** Use ncr_script_fill() to create the variable parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ** Use ncr_script_copy_and_bind() to make a copy and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ** bind to physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ** We have to know the offsets of all labels before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ** we reach them (for forward jumps).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ** Therefore we declare a struct here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) ** If you make changes inside the script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) ** DONT FORGET TO CHANGE THE LENGTHS HERE!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ** For HP Zalon/53c720 systems, the Zalon interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ** between CPU and 53c720 does prefetches, which causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ** problems with self modifying scripts. The problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ** is overcome by calling a dummy subroutine after each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ** modification, to force a refetch of the script on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ** return from the subroutine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #ifdef CONFIG_NCR53C8XX_PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define PREFETCH_FLUSH_CNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define PREFETCH_FLUSH SCR_CALL, PADDRH (wait_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define PREFETCH_FLUSH_CNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ** Script fragments which are loaded into the on-chip RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ** of 825A, 875 and 895 chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct script {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ncrcmd start [ 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ncrcmd startpos [ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ncrcmd select [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ncrcmd select2 [ 9 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ncrcmd loadpos [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ncrcmd send_ident [ 9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ncrcmd prepare [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ncrcmd prepare2 [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ncrcmd command [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ncrcmd dispatch [ 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ncrcmd clrack [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ncrcmd no_data [ 17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ncrcmd status [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ncrcmd msg_in [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ncrcmd msg_in2 [ 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ncrcmd msg_bad [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ncrcmd setmsg [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ncrcmd cleanup [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ncrcmd complete [ 9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ncrcmd cleanup_ok [ 8 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ncrcmd cleanup0 [ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #ifndef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ncrcmd signal [ 12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ncrcmd signal [ 9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ncrcmd done_pos [ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ncrcmd done_plug [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ncrcmd done_end [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ncrcmd save_dp [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ncrcmd restore_dp [ 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ncrcmd disconnect [ 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ncrcmd msg_out [ 9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ncrcmd msg_out_done [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ncrcmd idle [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ncrcmd reselect [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ncrcmd reselected [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ncrcmd resel_dsa [ 6 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ncrcmd loadpos1 [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ncrcmd resel_lun [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ncrcmd resel_tag [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ncrcmd jump_to_nexus [ 4 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ncrcmd nexus_indirect [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ncrcmd resel_notag [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ncrcmd data_in [MAX_SCATTERL * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ncrcmd data_in2 [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ncrcmd data_out [MAX_SCATTERL * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ncrcmd data_out2 [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ** Script fragments which stay in main memory for all chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct scripth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ncrcmd tryloop [MAX_START*2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ncrcmd tryloop2 [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ncrcmd done_queue [MAX_DONE*5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) ncrcmd done_queue2 [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ncrcmd select_no_atn [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ncrcmd cancel [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) ncrcmd skip [ 9 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ncrcmd skip2 [ 19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) ncrcmd par_err_data_in [ 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ncrcmd par_err_other [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ncrcmd msg_reject [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ncrcmd msg_ign_residue [ 24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ncrcmd msg_extended [ 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ncrcmd msg_ext_2 [ 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ncrcmd msg_wdtr [ 14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ncrcmd send_wdtr [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ncrcmd msg_ext_3 [ 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ncrcmd msg_sdtr [ 14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ncrcmd send_sdtr [ 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ncrcmd nego_bad_phase [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ncrcmd msg_out_abort [ 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ncrcmd hdata_in [MAX_SCATTERH * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ncrcmd hdata_in2 [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ncrcmd hdata_out [MAX_SCATTERH * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ncrcmd hdata_out2 [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ncrcmd reset [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ncrcmd aborttag [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ncrcmd abort [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ncrcmd abort_resel [ 20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ncrcmd resend_ident [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ncrcmd clratn_go_on [ 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ncrcmd nxtdsp_go_on [ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ncrcmd sdata_in [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ncrcmd data_io [ 18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ncrcmd bad_identify [ 12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ncrcmd bad_i_t_l [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ncrcmd bad_i_t_l_q [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ncrcmd bad_target [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ncrcmd bad_status [ 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ncrcmd start_ram [ 4 + PREFETCH_FLUSH_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ncrcmd start_ram0 [ 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) ncrcmd sto_restart [ 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ncrcmd wait_dma [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ncrcmd snooptest [ 9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ncrcmd snoopend [ 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ** Function headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static void ncr_alloc_ccb (struct ncb *np, u_char tn, u_char ln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static void ncr_complete (struct ncb *np, struct ccb *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static void ncr_exception (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static void ncr_free_ccb (struct ncb *np, struct ccb *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static void ncr_init_ccb (struct ncb *np, struct ccb *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static void ncr_init_tcb (struct ncb *np, u_char tn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static struct lcb * ncr_alloc_lcb (struct ncb *np, u_char tn, u_char ln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static struct lcb * ncr_setup_lcb (struct ncb *np, struct scsi_device *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static void ncr_getclock (struct ncb *np, int mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static void ncr_selectclock (struct ncb *np, u_char scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static struct ccb *ncr_get_ccb (struct ncb *np, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void ncr_chip_reset (struct ncb *np, int delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static void ncr_init (struct ncb *np, int reset, char * msg, u_long code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static int ncr_int_sbmc (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static int ncr_int_par (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static void ncr_int_ma (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static void ncr_int_sir (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static void ncr_int_sto (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static void ncr_negotiate (struct ncb* np, struct tcb* tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static int ncr_prepare_nego(struct ncb *np, struct ccb *cp, u_char *msgptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) static void ncr_script_copy_and_bind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) (struct ncb *np, ncrcmd *src, ncrcmd *dst, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static void ncr_script_fill (struct script * scr, struct scripth * scripth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static int ncr_scatter (struct ncb *np, struct ccb *cp, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static void ncr_getsync (struct ncb *np, u_char sfac, u_char *fakp, u_char *scntl3p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static void ncr_setsync (struct ncb *np, struct ccb *cp, u_char scntl3, u_char sxfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static void ncr_setup_tags (struct ncb *np, struct scsi_device *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static void ncr_setwide (struct ncb *np, struct ccb *cp, u_char wide, u_char ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static int ncr_snooptest (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static void ncr_timeout (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static void ncr_wakeup (struct ncb *np, u_long code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static void ncr_wakeup_done (struct ncb *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static void ncr_start_next_ccb (struct ncb *np, struct lcb * lp, int maxn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static void ncr_put_start_queue(struct ncb *np, struct ccb *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static void insert_into_waiting_list(struct ncb *np, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void process_waiting_list(struct ncb *np, int sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define remove_from_waiting_list(np, cmd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) retrieve_from_waiting_list(1, (np), (cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define requeue_waiting_list(np) process_waiting_list((np), DID_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define reset_waiting_list(np) process_waiting_list((np), DID_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static inline char *ncr_name (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return np->inst_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ** Scripts for NCR-Processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ** Use ncr_script_bind for binding to physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ** NADDR generates a reference to a field of the controller data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ** PADDR generates a reference to another part of the script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ** RADDR generates a reference to a script processor register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ** FADDR generates a reference to a script processor register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ** with offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define RELOC_SOFTC 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define RELOC_LABEL 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define RELOC_REGISTER 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define RELOC_KVAR 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define RELOC_LABELH 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define RELOC_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define PADDR(label) (RELOC_LABEL | offsetof(struct script, label))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define RADDR(label) (RELOC_REGISTER | REG(label))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define KVAR(which) (RELOC_KVAR | (which))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define SCRIPT_KVAR_JIFFIES (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define SCRIPT_KVAR_FIRST SCRIPT_KVAR_JIFFIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define SCRIPT_KVAR_LAST SCRIPT_KVAR_JIFFIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * Kernel variables referenced in the scripts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static void *script_kvars[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) { (void *)&jiffies };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static struct script script0 __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /*--------------------------< START >-----------------------*/ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ** This NOP will be patched with LED ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) SCR_NO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ** Clear SIGP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) SCR_FROM_REG (ctest2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ** Then jump to a certain point in tryloop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ** Due to the lack of indirect addressing the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ** is self modifying here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }/*-------------------------< STARTPOS >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) PADDRH(tryloop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }/*-------------------------< SELECT >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ** DSA contains the address of a scheduled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ** data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ** SCRATCHA contains the address of the script,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ** which starts the next entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ** Set Initiator mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ** (Target mode is left as an exercise for the reader)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) SCR_CLR (SCR_TRG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) SCR_LOAD_REG (HS_REG, HS_SELECTING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ** And try to select this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) PADDR (reselect),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }/*-------------------------< SELECT2 >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ** Now there are 4 possibilities:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ** (1) The ncr loses arbitration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ** This is ok, because it will try again,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ** when the bus becomes idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ** (But beware of the timeout function!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ** (2) The ncr is reselected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ** Then the script processor takes the jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ** to the RESELECT label.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ** (3) The ncr wins arbitration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ** Then it will execute SCRIPTS instruction until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ** the next instruction that checks SCSI phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ** Then will stop and wait for selection to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ** complete or selection time-out to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ** As a result the SCRIPTS instructions until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ** LOADPOS + 2 should be executed in parallel with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ** the SCSI core performing selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ** The MESSAGE_REJECT problem seems to be due to a selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ** timing problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ** Wait immediately for the selection to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ** (2.5x behaves so)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ** Next time use the next slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) PADDR (startpos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ** The ncr doesn't have an indirect load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ** or store command. So we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ** copy part of the control block to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ** fixed place, where we can access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ** We patch the address part of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ** COPY command with the DSA-register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) RADDR (dsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) PADDR (loadpos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ** then we do the actual copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) SCR_COPY (sizeof (struct head)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ** continued after the next label ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }/*-------------------------< LOADPOS >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) NADDR (header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ** Wait for the next phase or the selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ** to complete or time-out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) PADDR (prepare),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }/*-------------------------< SEND_IDENT >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ** Selection complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ** Send the IDENTIFY and SIMPLE_TAG messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ** (and the EXTENDED_SDTR message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) SCR_MOVE_TBL ^ SCR_MSG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) offsetof (struct dsb, smsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) PADDRH (resend_ident),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) SCR_LOAD_REG (scratcha, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) NADDR (lastmsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }/*-------------------------< PREPARE >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ** load the savep (saved pointer) into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ** the TEMP register (actual pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) NADDR (header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ** Initialize the status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) NADDR (header.status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) RADDR (scr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }/*-------------------------< PREPARE2 >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ** Initialize the msgout buffer with a NOOP message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) SCR_LOAD_REG (scratcha, NOP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) NADDR (msgin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ** Anticipate the COMMAND phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ** This is the normal case for initial selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }/*-------------------------< COMMAND >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ** ... and send the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) SCR_MOVE_TBL ^ SCR_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) offsetof (struct dsb, cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ** If status is still HS_NEGOTIATE, negotiation failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ** We check this here, since we want to do that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ** only once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) SCR_FROM_REG (HS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) SIR_NEGO_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }/*-----------------------< DISPATCH >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ** MSG_IN is the only phase that shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ** entered at least once for each (re)selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ** So we test it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) PADDR (msg_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) SCR_RETURN ^ IFTRUE (IF (SCR_DATA_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ** Possible data corruption during Memory Write and Invalidate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ** This work-around resets the addressing logic prior to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ** start of the first MOVE of a DATA IN phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) ** (See Documentation/scsi/ncr53c8xx.rst for more information)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) PADDR (status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) PADDR (command),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) PADDR (msg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ** Discard one illegal phase byte, if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) SCR_LOAD_REG (scratcha, XE_BAD_PHASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) NADDR (xerr_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }/*-------------------------< CLRACK >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ** Terminate possible pending message phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }/*-------------------------< NO_DATA >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ** The target wants to tranfer too much data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ** or in the wrong direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ** Remember that in extended error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) SCR_LOAD_REG (scratcha, XE_EXTRA_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) NADDR (xerr_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ** Discard one data byte, if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) SCR_MOVE_ABS (1) ^ SCR_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ** .. and repeat as required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) PADDR (no_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }/*-------------------------< STATUS >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ** get the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) SCR_MOVE_ABS (1) ^ SCR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ** save status to scsi_status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ** mark as complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) SCR_TO_REG (SS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) SCR_LOAD_REG (HS_REG, HS_COMPLETE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }/*-------------------------< MSG_IN >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ** Get the first byte of the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ** and save it to SCRATCHA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ** The script processor doesn't negate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ** ACK signal after this transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) NADDR (msgin[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }/*-------------------------< MSG_IN2 >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ** Handle this message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) SCR_JUMP ^ IFTRUE (DATA (COMMAND_COMPLETE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) PADDR (complete),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) SCR_JUMP ^ IFTRUE (DATA (DISCONNECT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) PADDR (disconnect),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) SCR_JUMP ^ IFTRUE (DATA (SAVE_POINTERS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) PADDR (save_dp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) SCR_JUMP ^ IFTRUE (DATA (RESTORE_POINTERS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) PADDR (restore_dp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) SCR_JUMP ^ IFTRUE (DATA (EXTENDED_MESSAGE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) PADDRH (msg_extended),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) SCR_JUMP ^ IFTRUE (DATA (NOP)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) SCR_JUMP ^ IFTRUE (DATA (MESSAGE_REJECT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) PADDRH (msg_reject),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) SCR_JUMP ^ IFTRUE (DATA (IGNORE_WIDE_RESIDUE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) PADDRH (msg_ign_residue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ** Rest of the messages left as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ** an exercise ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) ** Unimplemented messages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ** fall through to MSG_BAD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) }/*-------------------------< MSG_BAD >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ** unimplemented message - reject it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) SIR_REJECT_SENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) SCR_LOAD_REG (scratcha, MESSAGE_REJECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }/*-------------------------< SETMSG >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) SCR_SET (SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }/*-------------------------< CLEANUP >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) ** dsa: Pointer to ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ** or xxxxxxFF (no ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ** HS_REG: Host-Status (<>0!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) SCR_FROM_REG (dsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) SCR_JUMP ^ IFTRUE (DATA (0xff)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ** dsa is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) ** complete the cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) PADDR (cleanup_ok),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }/*-------------------------< COMPLETE >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ** Complete message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ** Copy TEMP register to LASTP in header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) NADDR (header.lastp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ** When we terminate the cycle by clearing ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ** the target may disconnect immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ** We don't want to be told of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ** "unexpected disconnect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ** so we disable this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) SCR_REG_REG (scntl2, SCR_AND, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ** Terminate cycle ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) SCR_CLR (SCR_ACK|SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) ** ... and wait for the disconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) SCR_WAIT_DISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) }/*-------------------------< CLEANUP_OK >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ** Save host status to header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) RADDR (scr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) NADDR (header.status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ** and copy back the header to the ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) RADDR (dsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) PADDR (cleanup0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) SCR_COPY (sizeof (struct head)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) NADDR (header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }/*-------------------------< CLEANUP0 >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }/*-------------------------< SIGNAL >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ** if job not completed ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) SCR_FROM_REG (HS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ** ... start the next command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) SCR_JUMP ^ IFTRUE (MASK (0, (HS_DONEMASK|HS_SKIPMASK))),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) PADDR(start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ** If command resulted in not GOOD status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) ** call the C code if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) SCR_FROM_REG (SS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) PADDRH (bad_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #ifndef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ** ... signal completion to the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) SIR_INTFLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ** Auf zu neuen Schandtaten!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) PADDR(start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) #else /* defined SCSI_NCR_CCB_DONE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ** ... signal completion to the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) }/*------------------------< DONE_POS >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) PADDRH (done_queue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }/*------------------------< DONE_PLUG >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) SIR_DONE_OVERFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }/*------------------------< DONE_END >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) SIR_INTFLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) PADDR (done_pos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #endif /* SCSI_NCR_CCB_DONE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }/*-------------------------< SAVE_DP >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ** SAVE_DP message:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ** Copy TEMP register to SAVEP in header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) NADDR (header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }/*-------------------------< RESTORE_DP >---------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ** RESTORE_DP message:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) ** Copy SAVEP in header to TEMP register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) NADDR (header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }/*-------------------------< DISCONNECT >---------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) ** DISCONNECTing ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ** disable the "unexpected disconnect" feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) ** and remove the ACK signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) SCR_REG_REG (scntl2, SCR_AND, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) SCR_CLR (SCR_ACK|SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ** Wait for the disconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) SCR_WAIT_DISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ** Status is: DISCONNECTED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) PADDR (cleanup_ok),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }/*-------------------------< MSG_OUT >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ** The target requests a message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) NADDR (lastmsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ** If it was no ABORT message ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) SCR_JUMP ^ IFTRUE (DATA (ABORT_TASK_SET)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) PADDRH (msg_out_abort),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ** ... wait for the next phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) ** if it's a message out, send it again, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) PADDR (msg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) }/*-------------------------< MSG_OUT_DONE >--------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ** ... else clear the message ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) SCR_LOAD_REG (scratcha, NOP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ** ... and process the next phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) }/*-------------------------< IDLE >------------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ** Nothing to do?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) ** Wait for reselect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) ** This NOP will be patched with LED OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ** SCR_REG_REG (gpreg, SCR_OR, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) SCR_NO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }/*-------------------------< RESELECT >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ** make the DSA invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) SCR_LOAD_REG (dsa, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) SCR_CLR (SCR_TRG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) SCR_LOAD_REG (HS_REG, HS_IN_RESELECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ** Sleep waiting for a reselection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ** If SIGP is set, special treatment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ** Zu allem bereit ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) SCR_WAIT_RESEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) PADDR(start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }/*-------------------------< RESELECTED >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ** This NOP will be patched with LED ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) SCR_NO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ** ... zu nichts zu gebrauchen ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ** load the target id into the SFBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) ** and jump to the control block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ** Look at the declarations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) ** - struct ncb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ** - struct tcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ** - struct lcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ** - struct ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ** to understand what's going on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) SCR_TO_REG (sdid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) NADDR (jump_tcb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }/*-------------------------< RESEL_DSA >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) ** Ack the IDENTIFY or TAG previously received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ** The ncr doesn't have an indirect load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) ** or store command. So we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) ** copy part of the control block to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) ** fixed place, where we can access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ** We patch the address part of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ** COPY command with the DSA-register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) RADDR (dsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) PADDR (loadpos1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) ** then we do the actual copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) SCR_COPY (sizeof (struct head)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) ** continued after the next label ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }/*-------------------------< LOADPOS1 >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) NADDR (header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) ** The DSA contains the data structure address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) PADDR (prepare),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }/*-------------------------< RESEL_LUN >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ** come back to this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) ** to get an IDENTIFY message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) ** Wait for a msg_in phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) SIR_RESEL_NO_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) ** message phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) ** Read the data directly from the BUS DATA lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) ** This helps to support very old SCSI devices that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ** may reselect without sending an IDENTIFY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) SCR_FROM_REG (sbdl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) ** It should be an Identify message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }/*-------------------------< RESEL_TAG >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) ** Read IDENTIFY + SIMPLE + TAG using a single MOVE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) ** Aggressive optimization, is'nt it?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ** No need to test the SIMPLE TAG message, since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ** driver only supports conformant devices for tags. ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) SCR_MOVE_ABS (3) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) NADDR (msgin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) ** Read the TAG from the SIDL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) ** Still an aggressive optimization. ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) ** Compute the CCB indirect jump address which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) ** is (#TAG*2 & 0xfc) due to tag numbering using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ** 1,3,5..MAXTAGS*2+1 actual values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) SCR_REG_SFBR (sidl, SCR_SHL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) SCR_SFBR_REG (temp, SCR_AND, 0xfc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }/*-------------------------< JUMP_TO_NEXUS >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) PADDR (nexus_indirect),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }/*-------------------------< NEXUS_INDIRECT >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }/*-------------------------< RESEL_NOTAG >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) ** No tag expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ** Read an throw away the IDENTIFY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) NADDR (msgin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) PADDR (jump_to_nexus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }/*-------------------------< DATA_IN >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) ** #define MAX_SCATTERL parameter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ** it is filled in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ** ##===========< i=0; i<MAX_SCATTERL >=========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) ** || PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) ** || SCR_MOVE_TBL ^ SCR_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) ** || offsetof (struct dsb, data[ i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) ** ##==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) **---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) }/*-------------------------< DATA_IN2 >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) PADDR (no_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }/*-------------------------< DATA_OUT >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) ** #define MAX_SCATTERL parameter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) ** it is filled in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) ** ##===========< i=0; i<MAX_SCATTERL >=========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) ** || PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) ** || offsetof (struct dsb, data[ i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) ** ##==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) **---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) }/*-------------------------< DATA_OUT2 >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) PADDR (no_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) }/*--------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static struct scripth scripth0 __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /*-------------------------< TRYLOOP >---------------------*/{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ** Start the next entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) ** Called addresses point to the launch script in the CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ** They are patched by the main processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) ** #define MAX_START parameter, it is filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) ** in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) ** ##===========< I=0; i<MAX_START >===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) ** || SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) ** || PADDR (idle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) ** ##==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) }/*------------------------< TRYLOOP2 >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) PADDRH(tryloop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) }/*------------------------< DONE_QUEUE >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) ** Copy the CCB address to the next done entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) ** #define MAX_DONE parameter, it is filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) ** in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) ** ##===========< I=0; i<MAX_DONE >===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) ** || SCR_COPY (sizeof(struct ccb *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) ** || NADDR (header.cp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ** || NADDR (ccb_done[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) ** || SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) ** || PADDR (done_end),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) ** ##==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) **-----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }/*------------------------< DONE_QUEUE2 >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) PADDRH (done_queue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #endif /* SCSI_NCR_CCB_DONE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }/*------------------------< SELECT_NO_ATN >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) ** Set Initiator mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ** And try to select this target without ATN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) SCR_CLR (SCR_TRG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) SCR_LOAD_REG (HS_REG, HS_SELECTING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) SCR_SEL_TBL ^ offsetof (struct dsb, select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) PADDR (reselect),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) PADDR (select2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }/*-------------------------< CANCEL >------------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) SCR_LOAD_REG (scratcha, HS_ABORTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) SCR_JUMPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }/*-------------------------< SKIP >------------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) SCR_LOAD_REG (scratcha, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) ** This entry has been canceled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) ** Next time use the next slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) PADDR (startpos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) ** The ncr doesn't have an indirect load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) ** or store command. So we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) ** copy part of the control block to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ** fixed place, where we can access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) ** We patch the address part of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) ** COPY command with the DSA-register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) RADDR (dsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) PADDRH (skip2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) ** then we do the actual copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) SCR_COPY (sizeof (struct head)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) ** continued after the next label ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }/*-------------------------< SKIP2 >---------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) NADDR (header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) ** Initialize the status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) NADDR (header.status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) RADDR (scr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) ** Force host status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) SCR_FROM_REG (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) SCR_REG_REG (HS_REG, SCR_OR, HS_SKIPMASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) SCR_JUMPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) SCR_TO_REG (HS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) SCR_LOAD_REG (SS_REG, S_GOOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) PADDR (cleanup_ok),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) },/*-------------------------< PAR_ERR_DATA_IN >---------------*/{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) ** Ignore all data in byte, until next phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) PADDRH (par_err_other),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) NADDR (scratch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) SCR_JUMPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) -24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) },/*-------------------------< PAR_ERR_OTHER >------------------*/{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) ** count it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) SCR_REG_REG (PS_REG, SCR_ADD, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) ** jump to dispatcher.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) }/*-------------------------< MSG_REJECT >---------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) ** If a negotiation was in progress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) ** negotiation failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) ** Otherwise, let the C code print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) ** some message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) SCR_FROM_REG (HS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) SIR_REJECT_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) SIR_NEGO_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }/*-------------------------< MSG_IGN_RESIDUE >----------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ** Terminate cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) ** get residue size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) NADDR (msgin[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) ** Size is 0 .. ignore message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) SCR_JUMP ^ IFTRUE (DATA (0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ** Size is not 1 .. have to interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) SCR_JUMPR ^ IFFALSE (DATA (1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) ** Check for residue byte in swide register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) SCR_FROM_REG (scntl2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) ** There IS data in the swide register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) ** Discard it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) SCR_REG_REG (scntl2, SCR_OR, WSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) ** Load again the size to the sfbr register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) SCR_FROM_REG (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) SIR_IGN_RESIDUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) PADDR (clrack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }/*-------------------------< MSG_EXTENDED >-------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) ** Terminate cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) ** get length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) NADDR (msgin[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) SCR_JUMP ^ IFTRUE (DATA (3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) PADDRH (msg_ext_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) SCR_JUMP ^ IFFALSE (DATA (2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) PADDR (msg_bad),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) }/*-------------------------< MSG_EXT_2 >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) ** get extended message code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) NADDR (msgin[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) SCR_JUMP ^ IFTRUE (DATA (EXTENDED_WDTR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) PADDRH (msg_wdtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ** unknown extended message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) PADDR (msg_bad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }/*-------------------------< MSG_WDTR >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ** get data bus width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) NADDR (msgin[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) ** let the host do the real work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) SIR_NEGO_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) ** let the target fetch our answer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) SCR_SET (SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) PADDRH (nego_bad_phase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) }/*-------------------------< SEND_WDTR >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) ** Send the EXTENDED_WDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) NADDR (lastmsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) PADDR (msg_out_done),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) }/*-------------------------< MSG_EXT_3 >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) ** get extended message code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) NADDR (msgin[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) SCR_JUMP ^ IFTRUE (DATA (EXTENDED_SDTR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) PADDRH (msg_sdtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) ** unknown extended message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) PADDR (msg_bad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }/*-------------------------< MSG_SDTR >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) ** get period and offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) NADDR (msgin[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) ** let the host do the real work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) SIR_NEGO_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) ** let the target fetch our answer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) SCR_SET (SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) PADDRH (nego_bad_phase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }/*-------------------------< SEND_SDTR >-------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) ** Send the EXTENDED_SDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) NADDR (lastmsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) PADDR (msg_out_done),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) }/*-------------------------< NEGO_BAD_PHASE >------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) SIR_NEGO_PROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }/*-------------------------< MSG_OUT_ABORT >-------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) ** After ABORT message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) ** expect an immediate disconnect, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) SCR_REG_REG (scntl2, SCR_AND, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) SCR_CLR (SCR_ACK|SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) SCR_WAIT_DISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) ** ... and set the status to "ABORTED"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) SCR_LOAD_REG (HS_REG, HS_ABORTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) PADDR (cleanup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) }/*-------------------------< HDATA_IN >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) ** #define MAX_SCATTERH parameter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) ** it is filled in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) ** ##==< i=MAX_SCATTERL; i<MAX_SCATTERL+MAX_SCATTERH >==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) ** || PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) ** || SCR_MOVE_TBL ^ SCR_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) ** || offsetof (struct dsb, data[ i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) ** ##===================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) **---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) }/*-------------------------< HDATA_IN2 >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) PADDR (data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) }/*-------------------------< HDATA_OUT >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) ** Because the size depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) ** #define MAX_SCATTERH parameter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) ** it is filled in at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) ** ##==< i=MAX_SCATTERL; i<MAX_SCATTERL+MAX_SCATTERH >==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) ** || PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) ** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) ** || offsetof (struct dsb, data[ i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) ** ##===================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) **---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }/*-------------------------< HDATA_OUT2 >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) PADDR (data_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }/*-------------------------< RESET >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) ** Send a TARGET_RESET message if bad IDENTIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) ** received on reselection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) SCR_LOAD_REG (scratcha, ABORT_TASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) PADDRH (abort_resel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) }/*-------------------------< ABORTTAG >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) ** Abort a wrong tag received on reselection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) SCR_LOAD_REG (scratcha, ABORT_TASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) PADDRH (abort_resel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }/*-------------------------< ABORT >----------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) ** Abort a reselection when no active CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) SCR_LOAD_REG (scratcha, ABORT_TASK_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) }/*-------------------------< ABORT_RESEL >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) SCR_SET (SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) SCR_CLR (SCR_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) ** and send it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) ** we expect an immediate disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) SCR_REG_REG (scntl2, SCR_AND, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) SCR_COPY (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) NADDR (msgout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) NADDR (lastmsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) SCR_CLR (SCR_ACK|SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) SCR_WAIT_DISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) }/*-------------------------< RESEND_IDENT >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) ** The target stays in MSG OUT phase after having acked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) ** Identify [+ Tag [+ Extended message ]]. Targets shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) ** behave this way on parity error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) ** We must send it again all the messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) 0, /* 1rst ACK = 90 ns. Hope the NCR is'nt too fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) PADDR (send_ident),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }/*-------------------------< CLRATN_GO_ON >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) SCR_CLR (SCR_ATN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) }/*-------------------------< NXTDSP_GO_ON >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) }/*-------------------------< SDATA_IN >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) SCR_MOVE_TBL ^ SCR_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) offsetof (struct dsb, sense),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) SCR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) PADDR (dispatch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) PADDR (no_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) }/*-------------------------< DATA_IO >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) ** We jump here if the data direction was unknown at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) ** time we had to queue the command to the scripts processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) ** Pointers had been set as follow in this situation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) ** savep --> DATA_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) ** lastp --> start pointer when DATA_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) ** goalp --> goal pointer when DATA_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) ** wlastp --> start pointer when DATA_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) ** wgoalp --> goal pointer when DATA_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) ** This script sets savep/lastp/goalp according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) ** direction chosen by the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_OUT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) ** Direction is DATA IN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) ** Warning: we jump here, even when phase is DATA OUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) NADDR (header.lastp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) NADDR (header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) ** Jump to the SCRIPTS according to actual direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) NADDR (header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) ** Direction is DATA OUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) NADDR (header.wlastp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) NADDR (header.lastp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) NADDR (header.wgoalp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) NADDR (header.goalp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) SCR_JUMPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) -64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }/*-------------------------< BAD_IDENTIFY >---------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) ** If message phase but not an IDENTIFY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) ** get some help from the C code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) ** Old SCSI device may behave so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) SCR_JUMPR ^ IFTRUE (MASK (0x80, 0x80)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) SIR_RESEL_NO_IDENTIFY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) PADDRH (reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) ** Message is an IDENTIFY, but lun is unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) ** Read the message, since we got it directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ** from the SCSI BUS data lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) ** Signal problem to C code for logging the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) ** Send an ABORT_TASK_SET to clear all pending tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) SIR_RESEL_BAD_LUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) NADDR (msgin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) PADDRH (abort),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }/*-------------------------< BAD_I_T_L >------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) ** We donnot have a task for that I_T_L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) ** Signal problem to C code for logging the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) ** Send an ABORT_TASK_SET message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) SIR_RESEL_BAD_I_T_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) PADDRH (abort),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) }/*-------------------------< BAD_I_T_L_Q >----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) ** We donnot have a task that matches the tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ** Signal problem to C code for logging the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) ** Send an ABORT_TASK message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) SIR_RESEL_BAD_I_T_L_Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) PADDRH (aborttag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) }/*-------------------------< BAD_TARGET >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) ** We donnot know the target that reselected us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) ** Grab the first message if any (IDENTIFY).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) ** Signal problem to C code for logging the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) ** TARGET_RESET message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) SIR_RESEL_BAD_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) NADDR (msgin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) PADDRH (reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }/*-------------------------< BAD_STATUS >-----------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) ** If command resulted in either QUEUE FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) ** CHECK CONDITION or COMMAND TERMINATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) ** call the C code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) SCR_INT ^ IFTRUE (DATA (S_QUEUE_FULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) SIR_BAD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) SCR_INT ^ IFTRUE (DATA (S_CHECK_COND)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) SIR_BAD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) SCR_INT ^ IFTRUE (DATA (S_TERMINATED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) SIR_BAD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }/*-------------------------< START_RAM >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) ** Load the script into on-chip RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) ** and jump to start point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) SCR_COPY_F (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) PADDRH (start_ram0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) ** Flush script prefetch if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) PREFETCH_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) SCR_COPY (sizeof (struct script)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }/*-------------------------< START_RAM0 >--------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }/*-------------------------< STO_RESTART >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) ** Repair start queue (e.g. next time use the next slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) ** and jump to start point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) PADDR (startpos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) SCR_JUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) PADDR (start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }/*-------------------------< WAIT_DMA >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) ** For HP Zalon/53c720 systems, the Zalon interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) ** between CPU and 53c720 does prefetches, which causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) ** problems with self modifying scripts. The problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) ** is overcome by calling a dummy subroutine after each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) ** modification, to force a refetch of the script on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) ** return from the subroutine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) SCR_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) }/*-------------------------< SNOOPTEST >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) ** Read the variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) NADDR(ncr_cache),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) RADDR (scratcha),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) ** Write the variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) NADDR(ncr_cache),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) ** Read back the variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) SCR_COPY (4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) NADDR(ncr_cache),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) RADDR (temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) }/*-------------------------< SNOOPEND >-------------------*/,{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) ** And stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) SCR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }/*--------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) ** Fill in #define dependent parts of the script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) void __init ncr_script_fill (struct script * scr, struct scripth * scrh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) ncrcmd *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) p = scrh->tryloop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) for (i=0; i<MAX_START; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) *p++ =SCR_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) *p++ =PADDR (idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) BUG_ON((u_long)p != (u_long)&scrh->tryloop + sizeof (scrh->tryloop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) p = scrh->done_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) for (i = 0; i<MAX_DONE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) *p++ =SCR_COPY (sizeof(struct ccb *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) *p++ =NADDR (header.cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) *p++ =NADDR (ccb_done[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) *p++ =SCR_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) *p++ =PADDR (done_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) BUG_ON((u_long)p != (u_long)&scrh->done_queue+sizeof(scrh->done_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) #endif /* SCSI_NCR_CCB_DONE_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) p = scrh->hdata_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) for (i=0; i<MAX_SCATTERH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) *p++ =PADDR (dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) *p++ =offsetof (struct dsb, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) BUG_ON((u_long)p != (u_long)&scrh->hdata_in + sizeof (scrh->hdata_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) p = scr->data_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) for (i=MAX_SCATTERH; i<MAX_SCATTERH+MAX_SCATTERL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) *p++ =PADDR (dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) *p++ =offsetof (struct dsb, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) BUG_ON((u_long)p != (u_long)&scr->data_in + sizeof (scr->data_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) p = scrh->hdata_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) for (i=0; i<MAX_SCATTERH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) *p++ =PADDR (dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) *p++ =offsetof (struct dsb, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) BUG_ON((u_long)p != (u_long)&scrh->hdata_out + sizeof (scrh->hdata_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) p = scr->data_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) for (i=MAX_SCATTERH; i<MAX_SCATTERH+MAX_SCATTERL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) *p++ =PADDR (dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) *p++ =offsetof (struct dsb, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) BUG_ON((u_long) p != (u_long)&scr->data_out + sizeof (scr->data_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) ** Copy and rebind a script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) ncr_script_copy_and_bind (struct ncb *np, ncrcmd *src, ncrcmd *dst, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) ncrcmd opcode, new, old, tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) ncrcmd *start, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) int relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) int opchanged = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) start = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) end = src + len/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) while (src < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) opcode = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) *dst++ = cpu_to_scr(opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) ** If we forget to change the length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) ** in struct script, a field will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) ** padded with 0. This is an illegal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) ** command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) if (opcode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) printk (KERN_ERR "%s: ERROR0 IN SCRIPT at %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) ncr_name(np), (int) (src-start-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) if (DEBUG_FLAGS & DEBUG_SCRIPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) printk (KERN_DEBUG "%p: <%x>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) (src-1), (unsigned)opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) ** We don't have to decode ALL commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) switch (opcode >> 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) case 0xc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) ** COPY has TWO arguments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) relocs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) tmp1 = src[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) #ifdef RELOC_KVAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) if ((tmp1 & RELOC_MASK) == RELOC_KVAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) tmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) tmp2 = src[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) #ifdef RELOC_KVAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) if ((tmp2 & RELOC_MASK) == RELOC_KVAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) tmp2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) if ((tmp1 ^ tmp2) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) printk (KERN_ERR"%s: ERROR1 IN SCRIPT at %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) ncr_name(np), (int) (src-start-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) ** If PREFETCH feature not enabled, remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) ** the NO FLUSH bit if present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) if ((opcode & SCR_NO_FLUSH) && !(np->features & FE_PFEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) dst[-1] = cpu_to_scr(opcode & ~SCR_NO_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) ++opchanged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) ** MOVE (absolute address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) relocs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) ** JUMP / CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) ** don't relocate if relative :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) if (opcode & 0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) relocs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) relocs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) case 0x5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) case 0x7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) relocs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) relocs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) if (relocs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) while (relocs--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) old = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) switch (old & RELOC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) case RELOC_REGISTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) new = (old & ~RELOC_MASK) + np->paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) case RELOC_LABEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) new = (old & ~RELOC_MASK) + np->p_script;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) case RELOC_LABELH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) new = (old & ~RELOC_MASK) + np->p_scripth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) case RELOC_SOFTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) new = (old & ~RELOC_MASK) + np->p_ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) #ifdef RELOC_KVAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) case RELOC_KVAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) if (((old & ~RELOC_MASK) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) SCRIPT_KVAR_FIRST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) ((old & ~RELOC_MASK) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) SCRIPT_KVAR_LAST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) panic("ncr KVAR out of range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) new = vtophys(script_kvars[old &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) ~RELOC_MASK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) /* Don't relocate a 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) if (old == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) new = old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) panic("ncr_script_copy_and_bind: weird relocation %x\n", old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) *dst++ = cpu_to_scr(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) *dst++ = cpu_to_scr(*src++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) ** Linux host data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) struct host_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) struct ncb *ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) #define PRINT_ADDR(cmd, arg...) dev_info(&cmd->device->sdev_gendev , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) static void ncr_print_msg(struct ccb *cp, char *label, u_char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) PRINT_ADDR(cp->cmd, "%s: ", label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) spi_print_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) ** NCR chip clock divisor table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) ** Divisors are multiplied by 10,000,000 in order to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) ** calculations more simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) #define _5M 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) static u_long div_10M[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) /*===============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) ** Prepare io register values used by ncr_init() according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) ** to selected and supported features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) ** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) ** transfers. 32,64,128 are only supported by 875 and 895 chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) ** We use log base 2 (burst length) as internal code, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) ** value 0 meaning "burst disabled".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) **===============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) * Burst length from burst code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) * Burst code from io register bits. Burst enable is ctest0 for c720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) #define burst_code(dmode, ctest0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) (ctest0) & 0x80 ? 0 : (((dmode) & 0xc0) >> 6) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) * Set initial io register bits from burst code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) static inline void ncr_init_burst(struct ncb *np, u_char bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) u_char *be = &np->rv_ctest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) *be &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) np->rv_dmode &= ~(0x3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) np->rv_ctest5 &= ~0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) if (!bc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) *be |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) --bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) np->rv_dmode |= ((bc & 0x3) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) np->rv_ctest5 |= (bc & 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) static void __init ncr_prepare_setting(struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) u_char burst_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) u_long period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) ** Save assumed BIOS setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) np->sv_scntl3 = INB(nc_scntl3) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) np->sv_dmode = INB(nc_dmode) & 0xce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) np->sv_dcntl = INB(nc_dcntl) & 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) np->sv_ctest0 = INB(nc_ctest0) & 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) np->sv_ctest3 = INB(nc_ctest3) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) np->sv_ctest4 = INB(nc_ctest4) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) np->sv_ctest5 = INB(nc_ctest5) & 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) np->sv_gpcntl = INB(nc_gpcntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) np->sv_stest2 = INB(nc_stest2) & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) np->sv_stest4 = INB(nc_stest4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) ** Wide ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) np->maxwide = (np->features & FE_WIDE)? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) * Guess the frequency of the chip's clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if (np->features & FE_ULTRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) np->clock_khz = 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) np->clock_khz = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) * Get the clock multiplier factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) if (np->features & FE_QUAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) np->multiplier = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) else if (np->features & FE_DBLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) np->multiplier = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) np->multiplier = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) * Measure SCSI clock frequency for chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) * it may vary from assumed one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) if (np->features & FE_VARCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) ncr_getclock(np, np->multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) * Divisor to be used for async (timer pre-scaler).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) i = np->clock_divn - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) np->rv_scntl3 = i+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) * Minimum synchronous period factor supported by the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) * Btw, 'period' is in tenths of nanoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) if (period <= 250) np->minsync = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) else if (period <= 303) np->minsync = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) else if (period <= 500) np->minsync = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) else np->minsync = (period + 40 - 1) / 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) if (np->minsync < 25 && !(np->features & FE_ULTRA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) np->minsync = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) * Maximum synchronous period factor supported by the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) np->maxsync = period > 2540 ? 254 : period / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) ** Prepare initial value of other IO registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) #if defined SCSI_NCR_TRUST_BIOS_SETTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) np->rv_scntl0 = np->sv_scntl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) np->rv_dmode = np->sv_dmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) np->rv_dcntl = np->sv_dcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) np->rv_ctest0 = np->sv_ctest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) np->rv_ctest3 = np->sv_ctest3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) np->rv_ctest4 = np->sv_ctest4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) np->rv_ctest5 = np->sv_ctest5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) burst_max = burst_code(np->sv_dmode, np->sv_ctest0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) ** Select burst length (dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) burst_max = driver_setup.burst_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) if (burst_max == 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) burst_max = burst_code(np->sv_dmode, np->sv_ctest0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) if (burst_max > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) burst_max = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) if (burst_max > np->maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) burst_max = np->maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) ** Select all supported special features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) if (np->features & FE_ERL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) np->rv_dmode |= ERL; /* Enable Read Line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) if (np->features & FE_BOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) np->rv_dmode |= BOF; /* Burst Opcode Fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) if (np->features & FE_ERMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) np->rv_dmode |= ERMP; /* Enable Read Multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) if (np->features & FE_PFEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) np->rv_dcntl |= PFEN; /* Prefetch Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) if (np->features & FE_CLSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) if (np->features & FE_WRIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) np->rv_ctest3 |= WRIE; /* Write and Invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) if (np->features & FE_DFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) np->rv_ctest5 |= DFS; /* Dma Fifo Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) if (np->features & FE_MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) np->rv_ctest4 |= MUX; /* Host bus multiplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) if (np->features & FE_EA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) np->rv_dcntl |= EA; /* Enable ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) if (np->features & FE_EHP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) np->rv_ctest0 |= EHP; /* Even host parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) ** Select some other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) if (driver_setup.master_parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) np->rv_ctest4 |= MPEE; /* Master parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) if (driver_setup.scsi_parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) ** Get SCSI addr of host adapter (set by bios?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) if (np->myaddr == 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) np->myaddr = INB(nc_scid) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) if (!np->myaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) np->myaddr = SCSI_NCR_MYADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) #endif /* SCSI_NCR_TRUST_BIOS_SETTING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) * Prepare initial io register bits for burst length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) ncr_init_burst(np, burst_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) ** Set SCSI BUS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) ** - ULTRA2 chips (895/895A/896) report the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) ** BUS mode through the STEST4 IO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) ** - For previous generation chips (825/825A/875),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) ** user has to tell us how to check against HVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) ** since a 100% safe algorithm is not possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) np->scsi_mode = SMODE_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) if (np->features & FE_DIFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) switch(driver_setup.diff_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) case 4: /* Trust previous settings if present, then GPIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) if (np->sv_scntl3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (np->sv_stest2 & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) np->scsi_mode = SMODE_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) case 3: /* SYMBIOS controllers report HVD through GPIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) if (INB(nc_gpreg) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) case 2: /* Set HVD unconditionally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) np->scsi_mode = SMODE_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) case 1: /* Trust previous settings for HVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) if (np->sv_stest2 & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) np->scsi_mode = SMODE_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) default:/* Don't care about HVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) if (np->scsi_mode == SMODE_HVD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) np->rv_stest2 |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) ** Set LED support from SCRIPTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) ** Ignore this feature for boards known to use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) ** specific GPIO wiring and for the 895A or 896
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) ** that drive the LED directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) ** Also probe initial setting of GPIO0 as output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) if ((driver_setup.led_pin) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) np->features |= FE_LED0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) ** Set irq mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) switch(driver_setup.irqm & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) np->rv_dcntl |= IRQM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) np->rv_dcntl |= (np->sv_dcntl & IRQM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) ** Configure targets according to driver setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) ** Allow to override sync, wide and NOSCAN from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) ** boot command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) for (i = 0 ; i < MAX_TARGET ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) struct tcb *tp = &np->target[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) tp->usrsync = driver_setup.default_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) tp->usrwide = driver_setup.max_wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) tp->usrtags = MAX_TAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) tp->period = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) if (!driver_setup.disconnection)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) np->target[i].usrflag = UF_NODISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) ** Announce all that stuff to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) printk(KERN_INFO "%s: ID %d, Fast-%d%s%s\n", ncr_name(np),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) np->myaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) np->minsync < 12 ? 40 : (np->minsync < 25 ? 20 : 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) (np->rv_scntl0 & 0xa) ? ", Parity Checking" : ", NO Parity",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) (np->rv_stest2 & 0x20) ? ", Differential" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) if (bootverbose > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) printk (KERN_INFO "%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) ncr_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) printk (KERN_INFO "%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) ncr_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) if (bootverbose && np->paddr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) printk (KERN_INFO "%s: on-chip RAM at 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) ncr_name(np), np->paddr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) ** Done SCSI commands list management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) ** We donnot enter the scsi_done() callback immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) ** after a command has been seen as completed but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) ** insert it into a list which is flushed outside any kind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) ** of driver critical section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) ** This allows to do minimal stuff under interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) ** inside critical sections and to also avoid locking up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) ** on recursive calls to driver entry points under SMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) ** In fact, the only kernel point which is entered by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) ** driver with a driver lock set is kmalloc(GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) ** that shall not reenter the driver under any circumstances,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) ** AFAIK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) static inline void ncr_queue_done_cmd(struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) unmap_scsi_data(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) cmd->host_scribble = (char *) np->done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) np->done_list = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) static inline void ncr_flush_done_cmds(struct scsi_cmnd *lcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) while (lcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) cmd = lcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) lcmd = (struct scsi_cmnd *) cmd->host_scribble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) ** Prepare the next negotiation message if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) ** Fill in the part of message buffer that contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) ** negotiation and the nego_status field of the CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) ** Returns the size of the message in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) static int ncr_prepare_nego(struct ncb *np, struct ccb *cp, u_char *msgptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) struct tcb *tp = &np->target[cp->target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) int msglen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) int nego = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) struct scsi_target *starget = tp->starget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) /* negotiate wide transfers ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) if (!tp->widedone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) if (spi_support_wide(starget)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) nego = NS_WIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) tp->widedone=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) /* negotiate synchronous transfers? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) if (!nego && !tp->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) if (spi_support_sync(starget)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) nego = NS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) tp->period =0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) dev_info(&starget->dev, "target did not report SYNC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) switch (nego) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) case NS_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) msglen += spi_populate_sync_msg(msgptr + msglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) tp->maxoffs ? tp->minsync : 0, tp->maxoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) case NS_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) msglen += spi_populate_width_msg(msgptr + msglen, tp->usrwide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) cp->nego_status = nego;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) if (nego) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) tp->nego_cp = cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) ncr_print_msg(cp, nego == NS_WIDE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) "wide msgout":"sync_msgout", msgptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) return msglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) ** Start execution of a SCSI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) ** This is called from the generic SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) static int ncr_queue_command (struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) struct scsi_device *sdev = cmd->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) struct tcb *tp = &np->target[sdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) struct lcb *lp = tp->lp[sdev->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) int segments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) u_char idmsg, *msgptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) u32 msglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) u32 lastp, goalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) /*---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) ** Some shortcuts ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) **---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) if ((sdev->id == np->myaddr ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) (sdev->id >= MAX_TARGET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) (sdev->lun >= MAX_LUN )) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) return(DID_BAD_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) /*---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) ** Complete the 1st TEST UNIT READY command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) ** with error condition if the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) ** flagged NOSCAN, in order to speed up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) ** the boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) **---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) (tp->usrflag & UF_NOSCAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) tp->usrflag &= ~UF_NOSCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) return DID_BAD_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) if (DEBUG_FLAGS & DEBUG_TINY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) PRINT_ADDR(cmd, "CMD=%x ", cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) /*---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) ** Assign a ccb / bind cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) ** If resetting, shorten settle_time if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) ** in order to avoid spurious timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) ** If resetting or no free ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) ** insert cmd into the waiting list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) if (np->settle_time && cmd->request->timeout >= HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) u_long tlimit = jiffies + cmd->request->timeout - HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) if (time_after(np->settle_time, tlimit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) np->settle_time = tlimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) if (np->settle_time || !(cp=ncr_get_ccb (np, cmd))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) insert_into_waiting_list(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) return(DID_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) cp->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) /*----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) ** Build the identify / tag / sdtr message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) idmsg = IDENTIFY(0, sdev->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) if (cp ->tag != NO_TAG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) (cp != np->ccb && np->disc && !(tp->usrflag & UF_NODISC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) idmsg |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) msgptr = cp->scsi_smsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) msglen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) msgptr[msglen++] = idmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) if (cp->tag != NO_TAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) char order = np->order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) ** Force ordered tag if necessary to avoid timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) ** and to preserve interactivity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) if (lp && time_after(jiffies, lp->tags_stime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) if (lp->tags_smap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) order = ORDERED_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) if ((DEBUG_FLAGS & DEBUG_TAGS)||bootverbose>2){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) PRINT_ADDR(cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) "ordered tag forced.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) lp->tags_stime = jiffies + 3*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) lp->tags_smap = lp->tags_umap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) if (order == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) ** Ordered write ops, unordered read ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) switch (cmd->cmnd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) case 0x08: /* READ_SMALL (6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) case 0x28: /* READ_BIG (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) case 0xa8: /* READ_HUGE (12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) order = SIMPLE_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) order = ORDERED_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) msgptr[msglen++] = order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) ** Actual tags are numbered 1,3,5,..2*MAXTAGS+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) ** since we may have to deal with devices that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) ** problems with #TAG 0 or too great #TAG numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) msgptr[msglen++] = (cp->tag << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) /*----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) ** Build the data descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) direction = cmd->sc_data_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) if (direction != DMA_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) segments = ncr_scatter(np, cp, cp->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) if (segments < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) ncr_free_ccb(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) return(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) cp->data_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) segments = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) /*---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) ** negotiation required?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) ** (nego_status is filled by ncr_prepare_nego())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) **---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) cp->nego_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) if ((!tp->widedone || !tp->period) && !tp->nego_cp && lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) msglen += ncr_prepare_nego (np, cp, msgptr + msglen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) /*----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) ** Determine xfer direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) if (!cp->data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) ** If data direction is BIDIRECTIONAL, speculate FROM_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) ** but prepare alternate pointers for TO_DEVICE in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) ** of our speculation will be just wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) ** SCRIPTS will swap values if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) switch(direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) case DMA_BIDIRECTIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) case DMA_TO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) goalp = NCB_SCRIPT_PHYS (np, data_out2) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) if (segments <= MAX_SCATTERL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) lastp = goalp - 8 - (segments * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) lastp = NCB_SCRIPTH_PHYS (np, hdata_out2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) lastp -= (segments - MAX_SCATTERL) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) if (direction != DMA_BIDIRECTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) cp->phys.header.wgoalp = cpu_to_scr(goalp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) cp->phys.header.wlastp = cpu_to_scr(lastp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) case DMA_FROM_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) goalp = NCB_SCRIPT_PHYS (np, data_in2) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) if (segments <= MAX_SCATTERL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) lastp = goalp - 8 - (segments * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) lastp = NCB_SCRIPTH_PHYS (np, hdata_in2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) lastp -= (segments - MAX_SCATTERL) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) case DMA_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) lastp = goalp = NCB_SCRIPT_PHYS (np, no_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) ** Set all pointers values needed by SCRIPTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) ** If direction is unknown, start at data_io.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) cp->phys.header.lastp = cpu_to_scr(lastp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) cp->phys.header.goalp = cpu_to_scr(goalp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) if (direction == DMA_BIDIRECTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) cp->phys.header.savep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) cpu_to_scr(NCB_SCRIPTH_PHYS (np, data_io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) cp->phys.header.savep= cpu_to_scr(lastp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) ** Save the initial data pointer in order to be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) ** to redo the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) cp->startp = cp->phys.header.savep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) /*----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ** fill in ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) ** physical -> virtual backlink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) ** Generic SCSI command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) ** Startqueue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) cp->start.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) cp->restart.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_dsa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) ** select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) cp->phys.select.sel_id = sdev_id(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) cp->phys.select.sel_scntl3 = tp->wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) cp->phys.select.sel_sxfer = tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) ** message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) cp->phys.smsg.addr = cpu_to_scr(CCB_PHYS (cp, scsi_smsg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) cp->phys.smsg.size = cpu_to_scr(msglen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) ** command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) memcpy(cp->cdb_buf, cmd->cmnd, min_t(int, cmd->cmd_len, sizeof(cp->cdb_buf)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) cp->phys.cmd.addr = cpu_to_scr(CCB_PHYS (cp, cdb_buf[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) cp->phys.cmd.size = cpu_to_scr(cmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) ** status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) cp->actualquirks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) cp->scsi_status = S_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) cp->parity_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) cp->xerr_status = XE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) cp->sync_status = tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) cp->wide_status = tp->wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) /*----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) ** Critical region: start this job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) **----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) /* activate this job. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) cp->magic = CCB_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) ** insert next CCBs into start queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) ** 2 max at a time is enough to flush the CCB wait queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) cp->auto_sense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) if (lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) ncr_start_next_ccb(np, lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) ncr_put_start_queue(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) /* Command is successfully queued. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) return DID_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) ** Insert a CCB into the start queue and wake up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) ** SCRIPTS processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) static void ncr_start_next_ccb(struct ncb *np, struct lcb *lp, int maxn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) struct list_head *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) if (lp->held_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) while (maxn-- && lp->queuedccbs < lp->queuedepth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) qp = ncr_list_pop(&lp->wait_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) ++lp->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) cp = list_entry(qp, struct ccb, link_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) list_add_tail(qp, &lp->busy_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) lp->jump_ccb[cp->tag == NO_TAG ? 0 : cp->tag] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) cpu_to_scr(CCB_PHYS (cp, restart));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) ncr_put_start_queue(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) static void ncr_put_start_queue(struct ncb *np, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) u16 qidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) ** insert into start queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) if (!np->squeueput) np->squeueput = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) qidx = np->squeueput + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (qidx >= MAX_START + MAX_START) qidx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) np->scripth->tryloop [qidx] = cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) MEMORY_BARRIER();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) np->scripth->tryloop [np->squeueput] = cpu_to_scr(CCB_PHYS (cp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) np->squeueput = qidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) ++np->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) cp->queued = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) if (DEBUG_FLAGS & DEBUG_QUEUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) printk ("%s: queuepos=%d.\n", ncr_name (np), np->squeueput);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) ** Script processor may be waiting for reselect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) ** Wake it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) MEMORY_BARRIER();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) OUTB (nc_istat, SIGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) static int ncr_reset_scsi_bus(struct ncb *np, int enab_int, int settle_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) u32 term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) int retv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) np->settle_time = jiffies + settle_delay * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) if (bootverbose > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) printk("%s: resetting, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) "command processing suspended for %d seconds\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) ncr_name(np), settle_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) ncr_chip_reset(np, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) udelay(2000); /* The 895 needs time for the bus mode to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) if (enab_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) OUTW (nc_sien, RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) ** Enable Tolerant, reset IRQD if present and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) ** properly set IRQ mode, prior to resetting the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) OUTB (nc_stest3, TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) OUTB (nc_scntl1, CRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) if (!driver_setup.bus_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) ** Check for no terminators or SCSI bus shorts to ground.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) ** Read SCSI data bus, data parity bits and control signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) ** We are expecting RESET to be TRUE and other signals to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) ** FALSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) term = INB(nc_sstat0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) if (!(np->features & FE_WIDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) term &= 0x3ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) if (term != (2<<7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) printk("%s: suspicious SCSI data while resetting the BUS.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) printk("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) "0x%lx, expecting 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) ncr_name(np),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) (np->features & FE_WIDE) ? "dp1,d15-8," : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) (u_long)term, (u_long)(2<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) if (driver_setup.bus_check == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) retv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) OUTB (nc_scntl1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) return retv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) * Start reset process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) * If reset in progress do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) * The interrupt handler will reinitialize the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) * The timeout handler will wait for settle_time before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) * clearing it and so resuming command processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) static void ncr_start_reset(struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) if (!np->settle_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) ncr_reset_scsi_bus(np, 1, driver_setup.settle_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) ** Reset the SCSI BUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) ** This is called from the generic SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) static int ncr_reset_bus (struct ncb *np, struct scsi_cmnd *cmd, int sync_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) /* struct scsi_device *device = cmd->device; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) * Return immediately if reset is in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) if (np->settle_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) * Start the reset process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) * The script processor is then assumed to be stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) * Commands will now be queued in the waiting list until a settle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) * delay of 2 seconds will be completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) ncr_start_reset(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) * First, look in the wakeup list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) for (found=0, cp=np->ccb; cp; cp=cp->link_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) ** look for the ccb of this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) if (cp->host_status == HS_IDLE) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) if (cp->cmd == cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) * Then, look in the waiting list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) if (!found && retrieve_from_waiting_list(0, np, cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) * Wake-up all awaiting commands with DID_RESET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) reset_waiting_list(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) * Wake-up all pending commands with HS_RESET -> DID_RESET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) ncr_wakeup(np, HS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) * If the involved command was not in a driver queue, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) * scsi driver told us reset is synchronous, and the command is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) * currently in the waiting list, complete it with DID_RESET status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) * in order to keep it alive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) if (!found && sync_reset && !retrieve_from_waiting_list(0, np, cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) cmd->result = DID_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) ncr_queue_done_cmd(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) #if 0 /* unused and broken.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) ** Abort an SCSI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) ** This is called from the generic SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) static int ncr_abort_command (struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) /* struct scsi_device *device = cmd->device; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) int retv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * First, look for the scsi command in the waiting list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) if (remove_from_waiting_list(np, cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) cmd->result = ScsiResult(DID_ABORT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) ncr_queue_done_cmd(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) return SCSI_ABORT_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) * Then, look in the wakeup list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) for (found=0, cp=np->ccb; cp; cp=cp->link_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) ** look for the ccb of this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) if (cp->host_status == HS_IDLE) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) if (cp->cmd == cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) return SCSI_ABORT_NOT_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) if (np->settle_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) return SCSI_ABORT_SNOOZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) ** If the CCB is active, patch schedule jumps for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) ** script to abort the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) switch(cp->host_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) case HS_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) case HS_NEGOTIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) printk ("%s: abort ccb=%p (cancel)\n", ncr_name (np), cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) cp->start.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) cpu_to_scr(NCB_SCRIPTH_PHYS (np, cancel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) retv = SCSI_ABORT_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) case HS_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) cp->restart.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) cpu_to_scr(NCB_SCRIPTH_PHYS (np, abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) retv = SCSI_ABORT_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) retv = SCSI_ABORT_NOT_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) ** If there are no requests, the script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) ** processor will sleep on SEL_WAIT_RESEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) ** Let's wake it up, since it may have to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) OUTB (nc_istat, SIGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) return retv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) static void ncr_detach(struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) struct tcb *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) struct lcb *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) int target, lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) char inst_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) /* Local copy so we don't access np after freeing it! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) strlcpy(inst_name, ncr_name(np), sizeof(inst_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) printk("%s: releasing host resources\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) ** Stop the ncr_timeout process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) ** Set release_stage to 1 and wait that ncr_timeout() set it to 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) printk("%s: stopping the timer\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) np->release_stage = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) for (i = 50 ; i && np->release_stage != 2 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if (np->release_stage != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) printk("%s: the timer seems to be already stopped\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) else np->release_stage = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) ** Disable chip interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) printk("%s: disabling chip interrupts\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) OUTW (nc_sien , 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) OUTB (nc_dien , 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) ** Reset NCR chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) ** Restore bios setting for automatic clock detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) printk("%s: resetting chip\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) ncr_chip_reset(np, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) OUTB(nc_dmode, np->sv_dmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) OUTB(nc_dcntl, np->sv_dcntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) OUTB(nc_ctest0, np->sv_ctest0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) OUTB(nc_ctest3, np->sv_ctest3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) OUTB(nc_ctest4, np->sv_ctest4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) OUTB(nc_ctest5, np->sv_ctest5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) OUTB(nc_gpcntl, np->sv_gpcntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) OUTB(nc_stest2, np->sv_stest2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) ncr_selectclock(np, np->sv_scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) ** Free allocated ccb(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) while ((cp=np->ccb->link_ccb) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) np->ccb->link_ccb = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) if (cp->host_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) printk("%s: shall free an active ccb (host_status=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) ncr_name(np), cp->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) printk("%s: freeing ccb (%lx)\n", ncr_name(np), (u_long) cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) m_free_dma(cp, sizeof(*cp), "CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) /* Free allocated tp(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) for (target = 0; target < MAX_TARGET ; target++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) tp=&np->target[target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) for (lun = 0 ; lun < MAX_LUN ; lun++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) lp = tp->lp[lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) printk("%s: freeing lp (%lx)\n", ncr_name(np), (u_long) lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) if (lp->jump_ccb != &lp->jump_ccb_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) m_free_dma(lp->jump_ccb,256,"JUMP_CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) m_free_dma(lp, sizeof(*lp), "LCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) if (np->scripth0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) m_free_dma(np->scripth0, sizeof(struct scripth), "SCRIPTH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) if (np->script0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) m_free_dma(np->script0, sizeof(struct script), "SCRIPT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) if (np->ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) m_free_dma(np->ccb, sizeof(struct ccb), "CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) m_free_dma(np, sizeof(struct ncb), "NCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) printk("%s: host resources successfully released\n", inst_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) ** Complete execution of a SCSI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) ** Signal completion to the generic SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) void ncr_complete (struct ncb *np, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) struct tcb *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) struct lcb *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) ** Sanity check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) if (!cp || cp->magic != CCB_MAGIC || !cp->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) ** Print minimal debug information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) if (DEBUG_FLAGS & DEBUG_TINY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) printk ("CCB=%lx STAT=%x/%x\n", (unsigned long)cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) cp->host_status,cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) ** Get command, target and lun pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) cmd = cp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) cp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) tp = &np->target[cmd->device->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) lp = tp->lp[cmd->device->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) ** We donnot queue more than 1 ccb per target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) ** with negotiation at any time. If this ccb was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) ** used for negotiation, clear this info in the tcb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) if (cp == tp->nego_cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) tp->nego_cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) ** If auto-sense performed, change scsi status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) if (cp->auto_sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) cp->scsi_status = cp->auto_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) ** If we were recovering from queue full or performing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) ** auto-sense, requeue skipped CCBs to the wait queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) if (lp && lp->held_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) if (cp == lp->held_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) list_splice_init(&lp->skip_ccbq, &lp->wait_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) lp->held_ccb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) ** Check for parity errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) if (cp->parity_status > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) PRINT_ADDR(cmd, "%d parity error(s).\n",cp->parity_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) ** Check for extended errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) if (cp->xerr_status != XE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) switch (cp->xerr_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) case XE_EXTRA_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) PRINT_ADDR(cmd, "extraneous data discarded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) case XE_BAD_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) PRINT_ADDR(cmd, "invalid scsi phase (4/5).\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) PRINT_ADDR(cmd, "extended error %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) cp->xerr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) if (cp->host_status==HS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) cp->host_status = HS_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) ** Print out any error for debugging purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) if (DEBUG_FLAGS & (DEBUG_RESULT|DEBUG_TINY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) if (cp->host_status!=HS_COMPLETE || cp->scsi_status!=S_GOOD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) PRINT_ADDR(cmd, "ERROR: cmd=%x host_status=%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) "scsi_status=%x\n", cmd->cmnd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) cp->host_status, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) ** Check the status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) if ( (cp->host_status == HS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) && (cp->scsi_status == S_GOOD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) cp->scsi_status == S_COND_MET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) * All went well (GOOD status).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) * CONDITION MET status is returned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) * `Pre-Fetch' or `Search data' success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) cmd->result = ScsiResult(DID_OK, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) ** @RESID@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) ** Could dig out the correct value for resid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) ** but it would be quite complicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) /* if (cp->phys.header.lastp != cp->phys.header.goalp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) ** Allocate the lcb if not yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) if (!lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) ncr_alloc_lcb (np, cmd->device->id, cmd->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) tp->bytes += cp->data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) tp->transfers ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) ** If tags was reduced due to queue full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) ** increase tags if 1000 good status received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) if (lp && lp->usetags && lp->numtags < lp->maxtags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) ++lp->num_good;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) if (lp->num_good >= 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) lp->num_good = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) ++lp->numtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) ncr_setup_tags (np, cmd->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) } else if ((cp->host_status == HS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) && (cp->scsi_status == S_CHECK_COND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) ** Check condition code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) cmd->result = DID_OK << 16 | S_CHECK_COND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) ** Copy back sense data to caller's buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) memcpy(cmd->sense_buffer, cp->sense_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) min_t(size_t, SCSI_SENSE_BUFFERSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) sizeof(cp->sense_buf)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) if (DEBUG_FLAGS & (DEBUG_RESULT|DEBUG_TINY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) u_char *p = cmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) PRINT_ADDR(cmd, "sense data:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) for (i=0; i<14; i++) printk (" %x", *p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) printk (".\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) } else if ((cp->host_status == HS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) && (cp->scsi_status == S_CONFLICT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) ** Reservation Conflict condition code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) cmd->result = DID_OK << 16 | S_CONFLICT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) } else if ((cp->host_status == HS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) && (cp->scsi_status == S_BUSY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) cp->scsi_status == S_QUEUE_FULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) ** Target is busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) cmd->result = ScsiResult(DID_OK, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) } else if ((cp->host_status == HS_SEL_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) || (cp->host_status == HS_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) ** No response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) cmd->result = ScsiResult(DID_TIME_OUT, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) } else if (cp->host_status == HS_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) ** SCSI bus reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) cmd->result = ScsiResult(DID_RESET, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) } else if (cp->host_status == HS_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) ** Transfer aborted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) cmd->result = ScsiResult(DID_ABORT, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) ** Other protocol messes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) PRINT_ADDR(cmd, "COMMAND FAILED (%x %x) @%p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) cp->host_status, cp->scsi_status, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) cmd->result = ScsiResult(DID_ERROR, cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) ** trace output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) if (tp->usrflag & UF_TRACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) u_char * p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) PRINT_ADDR(cmd, " CMD:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) p = (u_char*) &cmd->cmnd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) for (i=0; i<cmd->cmd_len; i++) printk (" %x", *p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) if (cp->host_status==HS_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) switch (cp->scsi_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) case S_GOOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) printk (" GOOD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) case S_CHECK_COND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) printk (" SENSE:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) p = (u_char*) &cmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) for (i=0; i<14; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) printk (" %x", *p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) printk (" STAT: %x\n", cp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) } else printk (" HOSTERROR: %x", cp->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) printk ("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) ** Free this ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) ncr_free_ccb (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) ** requeue awaiting scsi commands for this lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) if (lp && lp->queuedccbs < lp->queuedepth &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) !list_empty(&lp->wait_ccbq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) ncr_start_next_ccb(np, lp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) ** requeue awaiting scsi commands for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) if (np->waiting_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) requeue_waiting_list(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) ** signal completion to generic driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) ncr_queue_done_cmd(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) ** Signal all (or one) control block done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) ** This CCB has been skipped by the NCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) ** Queue it in the corresponding unit queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) static void ncr_ccb_skipped(struct ncb *np, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) struct tcb *tp = &np->target[cp->target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) struct lcb *lp = tp->lp[cp->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) if (lp && cp != np->ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) cp->host_status &= ~HS_SKIPMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) cp->start.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) list_move_tail(&cp->link_ccbq, &lp->skip_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) if (cp->queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) --lp->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) if (cp->queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) --np->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) cp->queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) ** The NCR has completed CCBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) ** Look at the DONE QUEUE if enabled, otherwise scan all CCBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) void ncr_wakeup_done (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) i = np->ccb_done_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) j = i+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) if (j >= MAX_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) cp = np->ccb_done[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) if (!CCB_DONE_VALID(cp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) np->ccb_done[j] = (struct ccb *)CCB_DONE_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) np->scripth->done_queue[5*j + 4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) cpu_to_scr(NCB_SCRIPT_PHYS (np, done_plug));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) MEMORY_BARRIER();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) np->scripth->done_queue[5*i + 4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) cpu_to_scr(NCB_SCRIPT_PHYS (np, done_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) if (cp->host_status & HS_DONEMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) ncr_complete (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) else if (cp->host_status & HS_SKIPMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) ncr_ccb_skipped (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) i = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) np->ccb_done_ic = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) while (cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) if (cp->host_status & HS_DONEMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) ncr_complete (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) else if (cp->host_status & HS_SKIPMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) ncr_ccb_skipped (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) cp = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) ** Complete all active CCBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) void ncr_wakeup (struct ncb *np, u_long code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) struct ccb *cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) while (cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) if (cp->host_status != HS_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) cp->host_status = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) ncr_complete (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) cp = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) ** Reset ncr chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) /* Some initialisation must be done immediately following reset, for 53c720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) * at least. EA (dcntl bit 5) isn't set here as it is set once only in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) * the _detect function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) static void ncr_chip_reset(struct ncb *np, int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) OUTB (nc_istat, SRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) udelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) OUTB (nc_istat, 0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) if (np->features & FE_EHP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) OUTB (nc_ctest0, EHP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) if (np->features & FE_MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) OUTB (nc_ctest4, MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) ** Start NCR chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) void ncr_init (struct ncb *np, int reset, char * msg, u_long code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) ** Reset chip if asked, otherwise just clear fifos.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) OUTB (nc_istat, SRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) OUTB (nc_stest3, TE|CSF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) OUTONB (nc_ctest3, CLF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) ** Message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) if (msg) printk (KERN_INFO "%s: restart (%s).\n", ncr_name (np), msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) ** Clear Start Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) np->queuedepth = MAX_START - 1; /* 1 entry needed as end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) for (i = 1; i < MAX_START + MAX_START; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) np->scripth0->tryloop[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) ** Start at first entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) np->squeueput = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) np->script0->startpos[0] = cpu_to_scr(NCB_SCRIPTH_PHYS (np, tryloop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) ** Clear Done Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) for (i = 0; i < MAX_DONE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) np->ccb_done[i] = (struct ccb *)CCB_DONE_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) np->scripth0->done_queue[5*i + 4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) cpu_to_scr(NCB_SCRIPT_PHYS (np, done_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) ** Start at first entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) np->script0->done_pos[0] = cpu_to_scr(NCB_SCRIPTH_PHYS (np,done_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) np->ccb_done_ic = MAX_DONE-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) np->scripth0->done_queue[5*(MAX_DONE-1) + 4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) cpu_to_scr(NCB_SCRIPT_PHYS (np, done_plug));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) ** Wakeup all pending jobs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) ncr_wakeup (np, code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) ** Init chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) ** Remove reset; big delay because the 895 needs time for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) ** bus mode to settle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) ncr_chip_reset(np, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) /* full arb., ena parity, par->ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) OUTB (nc_istat , SIGP ); /* Signal Process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) OUTB (nc_ctest0, np->rv_ctest0); /* 720: CDIS and EHP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) OUTB (nc_stest2, EXT|np->rv_stest2); /* Extended Sreq/Sack filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) OUTB (nc_stest3, TE); /* TolerANT enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) OUTB (nc_stime0, 0x0c ); /* HTH disabled STO 0.25 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) ** Disable disconnects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) np->disc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) ** Enable GPIO0 pin for writing if LED support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) if (np->features & FE_LED0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) OUTOFFB (nc_gpcntl, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) ** enable ints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) ** Fill in target structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) ** Reinitialize usrsync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) ** Reinitialize usrwide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) ** Prepare sync negotiation according to actual SCSI bus mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) for (i=0;i<MAX_TARGET;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) struct tcb *tp = &np->target[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) tp->sval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) tp->wval = np->rv_scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) if (tp->usrsync != 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) if (tp->usrsync <= np->maxsync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) if (tp->usrsync < np->minsync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) tp->usrsync = np->minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) tp->usrsync = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) if (tp->usrwide > np->maxwide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) tp->usrwide = np->maxwide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) ** Start script processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) if (np->paddr2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) printk ("%s: Downloading SCSI SCRIPTS.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) OUTL (nc_scratcha, vtobus(np->script0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) OUTL_DSP (NCB_SCRIPTH_PHYS (np, start_ram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) OUTL_DSP (NCB_SCRIPT_PHYS (np, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) ** Prepare the negotiation values for wide and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) ** synchronous transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) static void ncr_negotiate (struct ncb* np, struct tcb* tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) ** minsync unit is 4ns !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) u_long minsync = tp->usrsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) ** SCSI bus mode limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) if (np->scsi_mode && np->scsi_mode == SMODE_SE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) if (minsync < 12) minsync = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) ** our limit ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) if (minsync < np->minsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) minsync = np->minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) ** divider limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (minsync > np->maxsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) minsync = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) if (tp->maxoffs > np->maxoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) tp->maxoffs = np->maxoffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) tp->minsync = minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) tp->maxoffs = (minsync<255 ? tp->maxoffs : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) ** period=0: has to negotiate sync transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) tp->period=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) ** widedone=0: has to negotiate wide transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) tp->widedone=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) ** Get clock factor and sync divisor for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) ** synchronous factor period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) ** Returns the clock factor (in sxfer) and scntl3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) ** synchronous divisor field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) static void ncr_getsync(struct ncb *np, u_char sfac, u_char *fakp, u_char *scntl3p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) int div = np->clock_divn; /* Number of divisors supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) u_long fak; /* Sync factor in sxfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) u_long per; /* Period in tenths of ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) u_long kpc; /* (per * clk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) ** Compute the synchronous period in tenths of nano-seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) if (sfac <= 10) per = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) else if (sfac == 11) per = 303;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) else if (sfac == 12) per = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) else per = 40 * sfac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) ** Look for the greatest clock divisor that allows an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) ** input speed faster than the period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) kpc = per * clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) while (--div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) if (kpc >= (div_10M[div] << 2)) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) ** Calculate the lowest clock factor that allows an output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) ** speed not faster than the period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) fak = (kpc - 1) / div_10M[div] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) #if 0 /* This optimization does not seem very useful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) per = (fak * div_10M[div]) / clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) ** Why not to try the immediate lower divisor and to choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) ** the one that allows the fastest output speed ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) ** We don't want input speed too much greater than output speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) if (div >= 1 && fak < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) u_long fak2, per2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) fak2 = (kpc - 1) / div_10M[div-1] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) per2 = (fak2 * div_10M[div-1]) / clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) if (per2 < per && fak2 <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) fak = fak2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) per = per2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) --div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) if (fak < 4) fak = 4; /* Should never happen, too bad ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) ** Compute and return sync parameters for the ncr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) *fakp = fak - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) ** Set actual values, sync status and patch all ccbs of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) ** a target according to new sync/wide agreement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) static void ncr_set_sync_wide_status (struct ncb *np, u_char target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) struct tcb *tp = &np->target[target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) ** set actual value and sync_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) OUTB (nc_sxfer, tp->sval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) np->sync_st = tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) OUTB (nc_scntl3, tp->wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) np->wide_st = tp->wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) ** patch ALL ccbs of this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) for (cp = np->ccb; cp; cp = cp->link_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) if (!cp->cmd) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) if (scmd_id(cp->cmd) != target) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) cp->sync_status = tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) cp->wide_status = tp->wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) cp->phys.select.sel_scntl3 = tp->wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) cp->phys.select.sel_sxfer = tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) ** Switch sync mode for current job and it's target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) static void ncr_setsync (struct ncb *np, struct ccb *cp, u_char scntl3, u_char sxfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) struct scsi_cmnd *cmd = cp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) struct tcb *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) u_char target = INB (nc_sdid) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) u_char idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) BUG_ON(target != (scmd_id(cmd) & 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) tp = &np->target[target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) if (!scntl3 || !(sxfer & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) scntl3 = np->rv_scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) scntl3 = (scntl3 & 0xf0) | (tp->wval & EWS) | (np->rv_scntl3 & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) ** Deduce the value of controller sync period from scntl3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) ** period is in tenths of nano-seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) idiv = ((scntl3 >> 4) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) if ((sxfer & 0x1f) && idiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) tp->period = (((sxfer>>5)+4)*div_10M[idiv-1])/np->clock_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) tp->period = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) /* Stop there if sync parameters are unchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) if (tp->sval == sxfer && tp->wval == scntl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) tp->sval = sxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) tp->wval = scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) if (sxfer & 0x01f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) /* Disable extended Sreq/Sack filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) if (tp->period <= 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) OUTOFFB(nc_stest2, EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) spi_display_xfer_agreement(tp->starget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) ** set actual value and sync_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) ** patch ALL ccbs of this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) ncr_set_sync_wide_status(np, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) ** Switch wide mode for current job and it's target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) ** SCSI specs say: a SCSI device that accepts a WDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) ** message shall reset the synchronous agreement to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) ** asynchronous mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) static void ncr_setwide (struct ncb *np, struct ccb *cp, u_char wide, u_char ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) struct scsi_cmnd *cmd = cp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) u16 target = INB (nc_sdid) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) struct tcb *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) u_char scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) u_char sxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) BUG_ON(target != (scmd_id(cmd) & 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) tp = &np->target[target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) tp->widedone = wide+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) scntl3 = (tp->wval & (~EWS)) | (wide ? EWS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) sxfer = ack ? 0 : tp->sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) ** Stop there if sync/wide parameters are unchanged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) if (tp->sval == sxfer && tp->wval == scntl3) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) tp->sval = sxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) tp->wval = scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) ** Bells and whistles ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) if (bootverbose >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) dev_info(&cmd->device->sdev_target->dev, "WIDE SCSI %sabled.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) (scntl3 & EWS) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) ** set actual value and sync_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) ** patch ALL ccbs of this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) ncr_set_sync_wide_status(np, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) ** Switch tagged mode for a target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) static void ncr_setup_tags (struct ncb *np, struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) unsigned char tn = sdev->id, ln = sdev->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) struct lcb *lp = tp->lp[ln];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) u_char reqtags, maxdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) ** Just in case ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) if ((!tp) || (!lp) || !sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) ** If SCSI device queue depth is not yet set, leave here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) if (!lp->scdev_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) ** Donnot allow more tags than the SCSI driver can queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) ** for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) ** Donnot allow more tags than we can handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) maxdepth = lp->scdev_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) if (maxdepth > lp->maxnxs) maxdepth = lp->maxnxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) if (lp->maxtags > maxdepth) lp->maxtags = maxdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) if (lp->numtags > maxdepth) lp->numtags = maxdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) ** only devices conformant to ANSI Version >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) ** only devices capable of tagged commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) ** only if enabled by user ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) if (sdev->tagged_supported && lp->numtags > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) reqtags = lp->numtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) reqtags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) ** Update max number of tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) lp->numtags = reqtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) if (lp->numtags > lp->maxtags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) lp->maxtags = lp->numtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) ** If we want to switch tag mode, we must wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) ** for no CCB to be active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) if (reqtags > 1 && lp->usetags) { /* Stay in tagged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) if (lp->queuedepth == reqtags) /* Already announced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) lp->queuedepth = reqtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) else if (reqtags <= 1 && !lp->usetags) { /* Stay in untagged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) lp->queuedepth = reqtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) else { /* Want to switch tag mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) if (lp->busyccbs) /* If not yet safe, return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) lp->queuedepth = reqtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) lp->usetags = reqtags > 1 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) ** Patch the lun mini-script, according to tag mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) lp->jump_tag.l_paddr = lp->usetags?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) cpu_to_scr(NCB_SCRIPT_PHYS(np, resel_tag)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) cpu_to_scr(NCB_SCRIPT_PHYS(np, resel_notag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) ** Announce change to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) if (lp->usetags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) dev_info(&sdev->sdev_gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) "tagged command queue depth set to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) reqtags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) dev_info(&sdev->sdev_gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) "tagged command queueing disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) ** ncr timeout handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) ** Misused to keep the driver running when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) ** interrupts are not configured correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) static void ncr_timeout (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) u_long thistime = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) ** If release process in progress, let's go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) ** Set the release stage from 1 to 2 to synchronize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) ** with the release process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) if (np->release_stage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) if (np->release_stage == 1) np->release_stage = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) np->timer.expires = jiffies + SCSI_NCR_TIMER_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) add_timer(&np->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) ** If we are resetting the ncr, wait for settle_time before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) ** clearing it. Then command processing will be resumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) if (np->settle_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) if (np->settle_time <= thistime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) if (bootverbose > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) printk("%s: command processing resumed\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) np->settle_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) np->disc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) requeue_waiting_list(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) ** Since the generic scsi driver only allows us 0.5 second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) ** to perform abort of a command, we must look at ccbs about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) ** every 0.25 second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) if (np->lasttime + 4*HZ < thistime) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) ** block ncr interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) np->lasttime = thistime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) #ifdef SCSI_NCR_BROKEN_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) if (INB(nc_istat) & (INTF|SIP|DIP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) ** Process pending interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) if (DEBUG_FLAGS & DEBUG_TINY) printk ("{");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) ncr_exception (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) if (DEBUG_FLAGS & DEBUG_TINY) printk ("}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) #endif /* SCSI_NCR_BROKEN_INTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) ** log message for real hard errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) ** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) ** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) ** exception register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) ** ds: dstat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) ** si: sist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) ** SCSI bus lines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) ** so: control lines as driver by NCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) ** si: control lines as seen by NCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) ** sd: scsi data lines as seen by NCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) ** wide/fastmode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) ** sxfer: (see the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) ** scntl3: (see the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) ** current script command:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) ** dsp: script address (relative to start of script).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) ** dbc: first word of script command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) ** First 16 register of the chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) ** r0..rf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) static void ncr_log_hard_error(struct ncb *np, u16 sist, u_char dstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) u32 dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) int script_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) int script_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) char *script_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) u_char *script_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) dsp = INL (nc_dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) if (dsp > np->p_script && dsp <= np->p_script + sizeof(struct script)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) script_ofs = dsp - np->p_script;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) script_size = sizeof(struct script);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) script_base = (u_char *) np->script0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) script_name = "script";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) else if (np->p_scripth < dsp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) dsp <= np->p_scripth + sizeof(struct scripth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) script_ofs = dsp - np->p_scripth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) script_size = sizeof(struct scripth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) script_base = (u_char *) np->scripth0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) script_name = "scripth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) script_ofs = dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) script_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) script_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) script_name = "mem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) printk ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) (unsigned)INL (nc_dbc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) if (((script_ofs & 3) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) (unsigned)script_ofs < script_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) printk ("%s: script cmd = %08x\n", ncr_name(np),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) scr_to_cpu((int) *(ncrcmd *)(script_base + script_ofs)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) printk ("%s: regdump:", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) for (i=0; i<16;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) printk (" %02x", (unsigned)INB_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) printk (".\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) /*============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) ** ncr chip exception handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) **============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) ** In normal cases, interrupt conditions occur one at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) ** time. The ncr is able to stack in some extra registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) ** other interrupts that will occur after the first one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) ** But, several interrupts may occur at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) ** We probably should only try to deal with the normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) ** case, but it seems that multiple interrupts occur in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) ** some cases that are not abnormal at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) ** The most frequent interrupt condition is Phase Mismatch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) ** We should want to service this interrupt quickly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) ** A SCSI parity error may be delivered at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) ** The SIR interrupt is not very frequent in this driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) ** since the INTFLY is likely used for command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) ** signaling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) ** The Selection Timeout interrupt may be triggered with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) ** IID and/or UDC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) ** The SBMC interrupt (SCSI Bus Mode Change) may probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) ** occur at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) ** This handler try to deal as cleverly as possible with all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) ** the above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) **============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) void ncr_exception (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) u_char istat, dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) u16 sist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) ** interrupt on the fly ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) ** Since the global header may be copied back to a CCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) ** using a posted PCI memory write, the last operation on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) ** the istat register is a READ in order to flush posted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) ** PCI write commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) istat = INB (nc_istat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) if (istat & INTF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) OUTB (nc_istat, (istat & SIGP) | INTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) istat = INB (nc_istat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) if (DEBUG_FLAGS & DEBUG_TINY) printk ("F ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) ncr_wakeup_done (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) if (!(istat & (SIP|DIP)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) if (istat & CABRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) OUTB (nc_istat, CABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) ** Steinbach's Guideline for Systems Programming:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) ** Never test for an error condition you don't know how to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) sist = (istat & SIP) ? INW (nc_sist) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) dstat = (istat & DIP) ? INB (nc_dstat) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) if (DEBUG_FLAGS & DEBUG_TINY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) printk ("<%d|%x:%x|%x:%x>",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) (int)INB(nc_scr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) dstat,sist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) (unsigned)INL(nc_dsp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) (unsigned)INL(nc_dbc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) /*========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) ** First, interrupts we want to service cleanly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) ** Phase mismatch is the most frequent interrupt, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) ** so we have to service it as quickly and as cleanly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) ** as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) ** Programmed interrupts are rarely used in this driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) ** but we must handle them cleanly anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) ** We try to deal with PAR and SBMC combined with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) ** some other interrupt(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) **=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) if (!(sist & (STO|GEN|HTH|SGE|UDC|RST)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) !(dstat & (MDPE|BF|ABRT|IID))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) if ((sist & SBMC) && ncr_int_sbmc (np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) if ((sist & PAR) && ncr_int_par (np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) if (sist & MA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) ncr_int_ma (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) if (dstat & SIR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) ncr_int_sir (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) if (!(sist & (SBMC|PAR)) && !(dstat & SSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) printk( "%s: unknown interrupt(s) ignored, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) "ISTAT=%x DSTAT=%x SIST=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) ncr_name(np), istat, dstat, sist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) OUTONB_STD ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) /*========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) ** Now, interrupts that need some fixing up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) ** Order and multiple interrupts is so less important.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) ** If SRST has been asserted, we just reset the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) ** Selection is intirely handled by the chip. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) ** chip says STO, we trust it. Seems some other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) ** interrupts may occur at the same time (UDC, IID), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) ** we ignore them. In any case we do enough fix-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) ** in the service routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) ** We just exclude some fatal dma errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) **=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) if (sist & RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) ncr_init (np, 1, bootverbose ? "scsi reset" : NULL, HS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) if ((sist & STO) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) !(dstat & (MDPE|BF|ABRT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) OUTONB (nc_ctest3, CLF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) ncr_int_sto (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) /*=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) ** Now, interrupts we are not able to recover cleanly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) ** (At least for the moment).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) ** Do the register dump.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) ** Log message for real hard errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) ** Clear all fifos.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) ** For MDPE, BF, ABORT, IID, SGE and HTH we reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) ** BUS and the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) ** We are more soft for UDC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) **=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) if (time_after(jiffies, np->regtime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) np->regtime = jiffies + 10*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) for (i = 0; i<sizeof(np->regdump); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) ((char*)&np->regdump)[i] = INB_OFF(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) np->regdump.nc_dstat = dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) np->regdump.nc_sist = sist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) ncr_log_hard_error(np, sist, dstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) printk ("%s: have to clear fifos.\n", ncr_name (np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) OUTB (nc_stest3, TE|CSF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) OUTONB (nc_ctest3, CLF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) if ((sist & (SGE)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) (dstat & (MDPE|BF|ABRT|IID))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) ncr_start_reset(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) if (sist & HTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) printk ("%s: handshake timeout\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) ncr_start_reset(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) if (sist & UDC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) printk ("%s: unexpected disconnect\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) OUTB (HS_PRT, HS_UNEXPECTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) OUTL_DSP (NCB_SCRIPT_PHYS (np, cleanup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) /*=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) ** We just miss the cause of the interrupt. :(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) ** Print a message. The timeout will do the real work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) **=========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) printk ("%s: unknown interrupt\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) ** ncr chip exception handler for selection timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) ** There seems to be a bug in the 53c810.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) ** Although a STO-Interrupt is pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) ** it continues executing script commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) ** But it will fail and interrupt (IID) on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) ** the next instruction where it's looking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) ** for a valid phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) void ncr_int_sto (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) u_long dsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) if (DEBUG_FLAGS & DEBUG_TINY) printk ("T");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) ** look for ccb and set the status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) dsa = INL (nc_dsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) while (cp && (CCB_PHYS (cp, phys) != dsa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) cp = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) if (cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) cp-> host_status = HS_SEL_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) ncr_complete (np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) ** repair start queue and jump to start point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) OUTL_DSP (NCB_SCRIPTH_PHYS (np, sto_restart));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) ** ncr chip exception handler for SCSI bus mode change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) ** spi2-r12 11.2.3 says a transceiver mode change must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) ** generate a reset event and a device that detects a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) ** event shall initiate a hard reset. It says also that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) ** device that detects a mode change shall set data transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) ** mode to eight bit asynchronous, etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) ** So, just resetting should be enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) static int ncr_int_sbmc (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) u_char scsi_mode = INB (nc_stest4) & SMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) if (scsi_mode != np->scsi_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) printk("%s: SCSI bus mode change from %x to %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) ncr_name(np), np->scsi_mode, scsi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) np->scsi_mode = scsi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) ** Suspend command processing for 1 second and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) ** reinitialize all except the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) np->settle_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) ncr_init (np, 0, bootverbose ? "scsi mode change" : NULL, HS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) ** ncr chip exception handler for SCSI parity error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) static int ncr_int_par (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) u_char hsts = INB (HS_PRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) u32 dbc = INL (nc_dbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) u_char sstat1 = INB (nc_sstat1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) int phase = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) int msg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) u32 jmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) printk("%s: SCSI parity error detected: SCR1=%d DBC=%x SSTAT1=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) ncr_name(np), hsts, dbc, sstat1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) * Ignore the interrupt if the NCR is not connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) * to the SCSI bus, since the right work should have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) * been done on unexpected disconnection handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) if (!(INB (nc_scntl1) & ISCON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) * If the nexus is not clearly identified, reset the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) * We will try to do better later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) if (hsts & HS_INVALMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) goto reset_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) * If the SCSI parity error occurs in MSG IN phase, prepare a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) * MSG PARITY message. Otherwise, prepare a INITIATOR DETECTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) * ERROR message and let the device decide to retry the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) * or to terminate with check condition. If we were in MSG IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) * phase waiting for the response of a negotiation, we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) * get SIR_NEGO_FAILED at dispatch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) if (!(dbc & 0xc0000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) phase = (dbc >> 24) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) if (phase == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) msg = MSG_PARITY_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) msg = INITIATOR_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) * If the NCR stopped on a MOVE ^ DATA_IN, we jump to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) * script that will ignore all data in bytes until phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) * change, since we are not sure the chip will wait the phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) * change prior to delivering the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) if (phase == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) jmp = NCB_SCRIPTH_PHYS (np, par_err_data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) jmp = NCB_SCRIPTH_PHYS (np, par_err_other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) OUTONB (nc_ctest3, CLF ); /* clear dma fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) np->msgout[0] = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) OUTL_DSP (jmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) reset_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) ncr_start_reset(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) ** ncr chip exception handler for phase errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) ** We have to construct a new transfer descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) ** to transfer the rest of the current block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) static void ncr_int_ma (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) u32 dbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) u32 rest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) u32 dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) u32 dsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) u32 nxtdsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) u32 newtmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) u32 *vdsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) u32 oadr, olen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) u32 *tblp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) ncrcmd *newcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) u_char cmd, sbcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) struct ccb *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) dsp = INL (nc_dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) dbc = INL (nc_dbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) sbcl = INB (nc_sbcl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) cmd = dbc >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) rest = dbc & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) ** Take into account dma fifo and various buffers and latches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) ** only if the interrupted phase is an OUTPUT phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) if ((cmd & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) u_char ctest5, ss0, ss2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) u16 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) if (ctest5 & DFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) delta=(((ctest5 << 8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) delta=(INB (nc_dfifo) - rest) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) ** The data in the dma fifo has not been transferred to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) ** the target -> add the amount to the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) ** and clear the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) ** Check the sstat2 register in case of wide transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) rest += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) ss0 = INB (nc_sstat0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (ss0 & OLF) rest++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) if (ss0 & ORF) rest++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) if (INB(nc_scntl3) & EWS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) ss2 = INB (nc_sstat2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) if (ss2 & OLF1) rest++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) if (ss2 & ORF1) rest++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) printk ("P%x%x RL=%d D=%d SS0=%x ", cmd&7, sbcl&7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) (unsigned) rest, (unsigned) delta, ss0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) printk ("P%x%x RL=%d ", cmd&7, sbcl&7, rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) ** Clear fifos.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) OUTONB (nc_ctest3, CLF ); /* clear dma fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) ** locate matching cp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) ** if the interrupted phase is DATA IN or DATA OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) ** trust the global header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) dsa = INL (nc_dsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) if (!(cmd & 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) cp = np->header.cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) if (CCB_PHYS(cp, phys) != dsa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) while (cp && (CCB_PHYS (cp, phys) != dsa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) cp = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) ** try to find the interrupted script command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) ** and the address at which to continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) vdsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) nxtdsp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) if (dsp > np->p_script &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) dsp <= np->p_script + sizeof(struct script)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) vdsp = (u32 *)((char*)np->script0 + (dsp-np->p_script-8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) nxtdsp = dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) else if (dsp > np->p_scripth &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) dsp <= np->p_scripth + sizeof(struct scripth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) vdsp = (u32 *)((char*)np->scripth0 + (dsp-np->p_scripth-8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) nxtdsp = dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) else if (cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) if (dsp == CCB_PHYS (cp, patch[2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) vdsp = &cp->patch[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) nxtdsp = scr_to_cpu(vdsp[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) else if (dsp == CCB_PHYS (cp, patch[6])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) vdsp = &cp->patch[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) nxtdsp = scr_to_cpu(vdsp[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) ** log the information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) if (DEBUG_FLAGS & DEBUG_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) printk ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) cp, np->header.cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) (unsigned)dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) (unsigned)nxtdsp, vdsp, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) ** cp=0 means that the DSA does not point to a valid control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) ** block. This should not happen since we donnot use multi-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) ** move while we are being reselected ot after command complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) ** We are not able to recover from such a phase error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) if (!cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) printk ("%s: SCSI phase error fixup: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) "CCB already dequeued (0x%08lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) ncr_name (np), (u_long) np->header.cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) goto reset_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) ** get old startaddress and old length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) oadr = scr_to_cpu(vdsp[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) if (cmd & 0x10) { /* Table indirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) tblp = (u32 *) ((char*) &cp->phys + oadr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) olen = scr_to_cpu(tblp[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) oadr = scr_to_cpu(tblp[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) tblp = (u32 *) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) olen = scr_to_cpu(vdsp[0]) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) if (DEBUG_FLAGS & DEBUG_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) printk ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) tblp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) (unsigned) olen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) (unsigned) oadr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) ** check cmd against assumed interrupted script command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) if (cmd != (scr_to_cpu(vdsp[0]) >> 24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) PRINT_ADDR(cp->cmd, "internal error: cmd=%02x != %02x=(vdsp[0] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) ">> 24)\n", cmd, scr_to_cpu(vdsp[0]) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) goto reset_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) ** cp != np->header.cp means that the header of the CCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) ** currently being processed has not yet been copied to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) ** the global header area. That may happen if the device did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) ** not accept all our messages after having been selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) if (cp != np->header.cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) printk ("%s: SCSI phase error fixup: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) "CCB address mismatch (0x%08lx != 0x%08lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) ncr_name (np), (u_long) cp, (u_long) np->header.cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) ** if old phase not dataphase, leave here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) if (cmd & 0x06) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) PRINT_ADDR(cp->cmd, "phase change %x-%x %d@%08x resid=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) cmd&7, sbcl&7, (unsigned)olen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) (unsigned)oadr, (unsigned)rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) goto unexpected_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) ** choose the correct patch area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) ** if savep points to one, choose the other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) newcmd = cp->patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) newtmp = CCB_PHYS (cp, patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) if (newtmp == scr_to_cpu(cp->phys.header.savep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) newcmd = &cp->patch[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) newtmp = CCB_PHYS (cp, patch[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) ** fillin the commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) newcmd[0] = cpu_to_scr(((cmd & 0x0f) << 24) | rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) newcmd[1] = cpu_to_scr(oadr + olen - rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) newcmd[2] = cpu_to_scr(SCR_JUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) newcmd[3] = cpu_to_scr(nxtdsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) if (DEBUG_FLAGS & DEBUG_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) PRINT_ADDR(cp->cmd, "newcmd[%d] %x %x %x %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) (int) (newcmd - cp->patch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) (unsigned)scr_to_cpu(newcmd[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) (unsigned)scr_to_cpu(newcmd[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) (unsigned)scr_to_cpu(newcmd[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) (unsigned)scr_to_cpu(newcmd[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) ** fake the return address (to the patch).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) ** and restart script processor at dispatcher.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) OUTL (nc_temp, newtmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) OUTL_DSP (NCB_SCRIPT_PHYS (np, dispatch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) ** Unexpected phase changes that occurs when the current phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) ** is not a DATA IN or DATA OUT phase are due to error conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) ** Such event may only happen when the SCRIPTS is using a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) ** multibyte SCSI MOVE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) ** Phase change Some possible cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) ** COMMAND --> MSG IN SCSI parity error detected by target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) ** COMMAND --> STATUS Bad command or refused by target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) ** MSG OUT --> MSG IN Message rejected by target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) ** MSG OUT --> COMMAND Bogus target that discards extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) ** negotiation messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) ** The code below does not care of the new phase and so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) ** trusts the target. Why to annoy it ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) ** If the interrupted phase is COMMAND phase, we restart at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) ** dispatcher.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) ** If a target does not get all the messages after selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) ** the code assumes blindly that the target discards extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) ** messages and clears the negotiation status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) ** If the target does not want all our response to negotiation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) ** we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) ** bloat for such a should_not_happen situation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) ** In all other situation, we reset the BUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) ** Are these assumptions reasonable ? (Wait and see ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) unexpected_phase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) dsp -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) nxtdsp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) switch (cmd & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) case 2: /* COMMAND phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) nxtdsp = NCB_SCRIPT_PHYS (np, dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) case 3: /* STATUS phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) nxtdsp = NCB_SCRIPT_PHYS (np, dispatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) case 6: /* MSG OUT phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) np->scripth->nxtdsp_go_on[0] = cpu_to_scr(dsp + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) if (dsp == NCB_SCRIPT_PHYS (np, send_ident)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) cp->host_status = HS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) nxtdsp = NCB_SCRIPTH_PHYS (np, clratn_go_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) else if (dsp == NCB_SCRIPTH_PHYS (np, send_wdtr) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) dsp == NCB_SCRIPTH_PHYS (np, send_sdtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) nxtdsp = NCB_SCRIPTH_PHYS (np, nego_bad_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) case 7: /* MSG IN phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) nxtdsp = NCB_SCRIPT_PHYS (np, clrack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) if (nxtdsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) OUTL_DSP (nxtdsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) reset_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) ncr_start_reset(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) static void ncr_sir_to_redo(struct ncb *np, int num, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) struct scsi_cmnd *cmd = cp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) struct tcb *tp = &np->target[cmd->device->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) struct lcb *lp = tp->lp[cmd->device->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) struct list_head *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) struct ccb * cp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) int disc_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) int busy_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) u32 startp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) u_char s_status = INB (SS_PRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) ** Let the SCRIPTS processor skip all not yet started CCBs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) ** and count disconnected CCBs. Since the busy queue is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) ** the same order as the chip start queue, disconnected CCBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) ** are before cp and busy ones after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) qp = lp->busy_ccbq.prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) while (qp != &lp->busy_ccbq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) cp2 = list_entry(qp, struct ccb, link_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) qp = qp->prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) ++busy_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) if (cp2 == cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) cp2->start.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) cpu_to_scr(NCB_SCRIPTH_PHYS (np, skip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) lp->held_ccb = cp; /* Requeue when this one completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) disc_cnt = lp->queuedccbs - busy_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) switch(s_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) default: /* Just for safety, should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) case S_QUEUE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) ** Decrease number of tags to the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) ** disconnected commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) if (!lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) if (bootverbose >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) PRINT_ADDR(cmd, "QUEUE FULL! %d busy, %d disconnected "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) "CCBs\n", busy_cnt, disc_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) if (disc_cnt < lp->numtags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) lp->numtags = disc_cnt > 2 ? disc_cnt : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) lp->num_good = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) ncr_setup_tags (np, cmd->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) ** Requeue the command to the start queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) ** If any disconnected commands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) ** Clear SIGP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) ** Jump to reselect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) cp->phys.header.savep = cp->startp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) cp->host_status = HS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) cp->scsi_status = S_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) ncr_put_start_queue(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) if (disc_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) INB (nc_ctest2); /* Clear SIGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) OUTL_DSP (NCB_SCRIPT_PHYS (np, reselect));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) case S_TERMINATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) case S_CHECK_COND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) ** If we were requesting sense, give up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) if (cp->auto_sense)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) ** Device returned CHECK CONDITION status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) ** Prepare all needed data strutures for getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) ** sense data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) ** identify message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) cp->scsi_smsg2[0] = IDENTIFY(0, cmd->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) cp->phys.smsg.addr = cpu_to_scr(CCB_PHYS (cp, scsi_smsg2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) cp->phys.smsg.size = cpu_to_scr(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) ** sense command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) cp->phys.cmd.addr = cpu_to_scr(CCB_PHYS (cp, sensecmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) cp->phys.cmd.size = cpu_to_scr(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) ** patch requested size into sense command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) cp->sensecmd[0] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) cp->sensecmd[1] = (cmd->device->lun & 0x7) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) cp->sensecmd[4] = sizeof(cp->sense_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) ** sense data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) memset(cp->sense_buf, 0, sizeof(cp->sense_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) cp->phys.sense.addr = cpu_to_scr(CCB_PHYS(cp,sense_buf[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) cp->phys.sense.size = cpu_to_scr(sizeof(cp->sense_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) ** requeue the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) startp = cpu_to_scr(NCB_SCRIPTH_PHYS (np, sdata_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) cp->phys.header.savep = startp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) cp->phys.header.goalp = startp + 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) cp->phys.header.lastp = startp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) cp->phys.header.wgoalp = startp + 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) cp->phys.header.wlastp = startp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) cp->host_status = HS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) cp->scsi_status = S_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) cp->auto_sense = s_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) cp->start.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) ** Select without ATN for quirky devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) if (cmd->device->select_no_atn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) cp->start.schedule.l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) cpu_to_scr(NCB_SCRIPTH_PHYS (np, select_no_atn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) ncr_put_start_queue(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) OUTL_DSP (NCB_SCRIPT_PHYS (np, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) OUTONB_STD ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) ** ncr chip exception handler for programmed interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) void ncr_int_sir (struct ncb *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) u_char scntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) u_char chg, ofs, per, fak, wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) u_char num = INB (nc_dsps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) struct ccb *cp=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) u_long dsa = INL (nc_dsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) u_char target = INB (nc_sdid) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) struct tcb *tp = &np->target[target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) struct scsi_target *starget = tp->starget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) if (DEBUG_FLAGS & DEBUG_TINY) printk ("I#%d", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) switch (num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) case SIR_INTFLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) ** This is used for HP Zalon/53c720 where INTFLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) ** operation is currently broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) ncr_wakeup_done(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) #ifdef SCSI_NCR_CCB_DONE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) OUTL(nc_dsp, NCB_SCRIPT_PHYS (np, done_end) + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) OUTL(nc_dsp, NCB_SCRIPT_PHYS (np, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) case SIR_RESEL_NO_MSG_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) case SIR_RESEL_NO_IDENTIFY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) ** If devices reselecting without sending an IDENTIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) ** message still exist, this should help.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) ** We just assume lun=0, 1 CCB, no tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) if (tp->lp[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) OUTL_DSP (scr_to_cpu(tp->lp[0]->jump_ccb[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) case SIR_RESEL_BAD_TARGET: /* Will send a TARGET RESET message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) case SIR_RESEL_BAD_LUN: /* Will send a TARGET RESET message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) case SIR_RESEL_BAD_I_T_L_Q: /* Will send an ABORT TAG message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) case SIR_RESEL_BAD_I_T_L: /* Will send an ABORT message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) printk ("%s:%d: SIR %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) "incorrect nexus identification on reselection\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) ncr_name (np), target, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) case SIR_DONE_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) printk ("%s:%d: SIR %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) "CCB done queue overflow\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) ncr_name (np), target, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) case SIR_BAD_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) cp = np->header.cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) if (!cp || CCB_PHYS (cp, phys) != dsa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) ncr_sir_to_redo(np, num, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) ** lookup the ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) while (cp && (CCB_PHYS (cp, phys) != dsa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) cp = cp->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) BUG_ON(!cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) BUG_ON(cp != np->header.cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) if (!cp || cp != np->header.cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) switch (num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) ** Was Sie schon immer ueber transfermode negotiation wissen wollten ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) ** ("Everything you've always wanted to know about transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) ** negotiation")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) ** We try to negotiate sync and wide transfer only after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) ** a successful inquire command. We look at byte 7 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) ** inquire data to determine the capabilities of the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) ** When we try to negotiate, we append the negotiation message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) ** to the identify and (maybe) simple tag message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) ** The host status field is set to HS_NEGOTIATE to mark this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) ** situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) ** If the target doesn't answer this message immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) ** (as required by the standard), the SIR_NEGO_FAIL interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) ** will be raised eventually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) ** The handler removes the HS_NEGOTIATE status, and sets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) ** negotiated value to the default (async / nowide).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) ** If we receive a matching answer immediately, we check it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) ** for validity, and set the values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) ** If we receive a Reject message immediately, we assume the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) ** negotiation has failed, and fall back to standard values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) ** If we receive a negotiation message while not in HS_NEGOTIATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) ** state, it's a target initiated negotiation. We prepare a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) ** (hopefully) valid answer, set our parameters, and send back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) ** this answer to the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) ** If the target doesn't fetch the answer (no message out phase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) ** we assume the negotiation has failed, and fall back to default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) ** settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) ** When we set the values, we adjust them in all ccbs belonging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) ** to this target, in the controller's register, and in the "phys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) ** field of the controller's struct ncb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) ** Possible cases: hs sir msg_in value send goto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) ** We try to negotiate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) ** -> target doesn't msgin NEG FAIL noop defa. - dispatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) ** -> target rejected our msg NEG FAIL reject defa. - dispatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) ** -> target answered (ok) NEG SYNC sdtr set - clrack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) ** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) ** -> target answered (ok) NEG WIDE wdtr set - clrack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) ** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) ** -> any other msgin NEG FAIL noop defa. - dispatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) ** Target tries to negotiate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) ** -> incoming message --- SYNC sdtr set SDTR -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) ** -> incoming message --- WIDE wdtr set WDTR -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) ** We sent our answer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) ** -> target doesn't msgout --- PROTO ? defa. - dispatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) **-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) case SIR_NEGO_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) /*-------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) ** Negotiation failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) ** Target doesn't send an answer message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) ** or target rejected our message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) ** Remove negotiation request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) **-------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) OUTB (HS_PRT, HS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) case SIR_NEGO_PROTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) /*-------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) ** Negotiation failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) ** Target doesn't fetch the answer message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) **-------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) PRINT_ADDR(cp->cmd, "negotiation failed sir=%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) "status=%x.\n", num, cp->nego_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) ** any error in negotiation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) ** fall back to default mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) switch (cp->nego_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) case NS_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) spi_period(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) spi_offset(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) ncr_setsync (np, cp, 0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) case NS_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) spi_width(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) ncr_setwide (np, cp, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) np->msgin [0] = NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) np->msgout[0] = NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) cp->nego_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) case SIR_NEGO_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) ncr_print_msg(cp, "sync msgin", np->msgin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) chg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) per = np->msgin[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) ofs = np->msgin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) if (ofs==0) per=255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) ** if target sends SDTR message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) ** it CAN transfer synch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) if (ofs && starget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) spi_support_sync(starget) = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) ** check values against driver limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) if (per < np->minsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) {chg = 1; per = np->minsync;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) if (per < tp->minsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) {chg = 1; per = tp->minsync;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) if (ofs > tp->maxoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) {chg = 1; ofs = tp->maxoffs;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) ** Check against controller limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) fak = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) scntl3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) if (ofs != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) ncr_getsync(np, per, &fak, &scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) if (fak > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) chg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) if (ofs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) fak = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) per = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) scntl3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) tp->minsync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) PRINT_ADDR(cp->cmd, "sync: per=%d scntl3=0x%x ofs=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) "fak=%d chg=%d.\n", per, scntl3, ofs, fak, chg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) if (INB (HS_PRT) == HS_NEGOTIATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) OUTB (HS_PRT, HS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) switch (cp->nego_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) case NS_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) /* This was an answer message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) if (chg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) /* Answer wasn't acceptable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) spi_period(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) spi_offset(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) ncr_setsync(np, cp, 0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) OUTL_DSP(NCB_SCRIPT_PHYS (np, msg_bad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) /* Answer is ok. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) spi_period(starget) = per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) spi_offset(starget) = ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) ncr_setsync(np, cp, scntl3, (fak<<5)|ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) OUTL_DSP(NCB_SCRIPT_PHYS (np, clrack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) case NS_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) spi_width(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) ncr_setwide(np, cp, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) ** It was a request. Set value and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) ** prepare an answer message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) spi_period(starget) = per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) spi_offset(starget) = ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) ncr_setsync(np, cp, scntl3, (fak<<5)|ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) spi_populate_sync_msg(np->msgout, per, ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) cp->nego_status = NS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) ncr_print_msg(cp, "sync msgout", np->msgout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) if (!ofs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) OUTL_DSP (NCB_SCRIPT_PHYS (np, msg_bad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) np->msgin [0] = NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) case SIR_NEGO_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) ** Wide request message received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) ncr_print_msg(cp, "wide msgin", np->msgin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) ** get requested values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) chg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) wide = np->msgin[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) ** if target sends WDTR message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) ** it CAN transfer wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) if (wide && starget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) spi_support_wide(starget) = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) ** check values against driver limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) if (wide > tp->usrwide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) {chg = 1; wide = tp->usrwide;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) PRINT_ADDR(cp->cmd, "wide: wide=%d chg=%d.\n", wide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) chg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) if (INB (HS_PRT) == HS_NEGOTIATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) OUTB (HS_PRT, HS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) switch (cp->nego_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) case NS_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) ** This was an answer message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) if (chg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) /* Answer wasn't acceptable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) spi_width(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) ncr_setwide(np, cp, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) OUTL_DSP (NCB_SCRIPT_PHYS (np, msg_bad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) /* Answer is ok. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) spi_width(starget) = wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) ncr_setwide(np, cp, wide, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) OUTL_DSP (NCB_SCRIPT_PHYS (np, clrack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) case NS_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) spi_period(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) spi_offset(starget) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) ncr_setsync(np, cp, 0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) ** It was a request, set value and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) ** prepare an answer message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) spi_width(starget) = wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) ncr_setwide(np, cp, wide, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) spi_populate_width_msg(np->msgout, wide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) np->msgin [0] = NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) cp->nego_status = NS_WIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) if (DEBUG_FLAGS & DEBUG_NEGO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) ncr_print_msg(cp, "wide msgout", np->msgin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) /*--------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) ** Processing of special messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) **--------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) case SIR_REJECT_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) /*-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) ** We received a MESSAGE_REJECT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) **-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) PRINT_ADDR(cp->cmd, "MESSAGE_REJECT received (%x:%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) (unsigned)scr_to_cpu(np->lastmsg), np->msgout[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) case SIR_REJECT_SENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) /*-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) ** We received an unknown message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) **-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) ncr_print_msg(cp, "MESSAGE_REJECT sent for", np->msgin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) /*--------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) ** Processing of special messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) **--------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) case SIR_IGN_RESIDUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) /*-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) ** We received an IGNORE RESIDUE message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) ** which couldn't be handled by the script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) **-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) PRINT_ADDR(cp->cmd, "IGNORE_WIDE_RESIDUE received, but not yet "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) "implemented.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) case SIR_MISSING_SAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) /*-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) ** We received an DISCONNECT message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) ** but the datapointer wasn't saved before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) **-----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) PRINT_ADDR(cp->cmd, "DISCONNECT received, but datapointer "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) "not saved: data=%x save=%x goal=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) (unsigned) INL (nc_temp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) (unsigned) scr_to_cpu(np->header.savep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) (unsigned) scr_to_cpu(np->header.goalp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) OUTONB_STD ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) ** Acquire a control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) static struct ccb *ncr_get_ccb(struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) u_char tn = cmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) u_char ln = cmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) struct lcb *lp = tp->lp[ln];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) u_char tag = NO_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) struct ccb *cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) ** Lun structure available ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) struct list_head *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) ** Keep from using more tags than we can handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) if (lp->usetags && lp->busyccbs >= lp->maxnxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) ** Allocate a new CCB if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) if (list_empty(&lp->free_ccbq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) ncr_alloc_ccb(np, tn, ln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) ** Look for free CCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) qp = ncr_list_pop(&lp->free_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) if (qp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) cp = list_entry(qp, struct ccb, link_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) if (cp->magic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) PRINT_ADDR(cmd, "ccb free list corrupted "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) "(@%p)\n", cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) list_add_tail(qp, &lp->wait_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) ++lp->busyccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) ** If a CCB is available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) ** Get a tag for this nexus if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) if (cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) if (lp->usetags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) tag = lp->cb_tags[lp->ia_tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) else if (lp->actccbs > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) ** if nothing available, take the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) if (!cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) cp = np->ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) ** Wait until available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) while (cp->magic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) if (flags & SCSI_NOSLEEP) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) if (tsleep ((caddr_t)cp, PRIBIO|PCATCH, "ncr", 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) if (cp->magic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) cp->magic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) ** Move to next available tag if tag used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) if (tag != NO_TAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) ++lp->ia_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) if (lp->ia_tag == MAX_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) lp->ia_tag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) lp->tags_umap |= (((tagmap_t) 1) << tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) ** Remember all informations needed to free this CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) cp->tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) cp->target = tn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) cp->lun = ln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) if (DEBUG_FLAGS & DEBUG_TAGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) PRINT_ADDR(cmd, "ccb @%p using tag %d.\n", cp, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) return cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) ** Release one control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) static void ncr_free_ccb (struct ncb *np, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) struct tcb *tp = &np->target[cp->target];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) struct lcb *lp = tp->lp[cp->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) if (DEBUG_FLAGS & DEBUG_TAGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) PRINT_ADDR(cp->cmd, "ccb @%p freeing tag %d.\n", cp, cp->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) ** If lun control block available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) ** decrement active commands and increment credit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) ** free the tag if any and remove the JUMP for reselect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) if (cp->tag != NO_TAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) lp->cb_tags[lp->if_tag++] = cp->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) if (lp->if_tag == MAX_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) lp->if_tag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) lp->tags_umap &= ~(((tagmap_t) 1) << cp->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) lp->tags_smap &= lp->tags_umap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) lp->jump_ccb[cp->tag] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) cpu_to_scr(NCB_SCRIPTH_PHYS(np, bad_i_t_l_q));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) lp->jump_ccb[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) cpu_to_scr(NCB_SCRIPTH_PHYS(np, bad_i_t_l));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) ** Make this CCB available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) if (cp != np->ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) list_move(&cp->link_ccbq, &lp->free_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) --lp->busyccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) if (cp->queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) --lp->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) cp -> host_status = HS_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) cp -> magic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) if (cp->queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) --np->queuedccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) cp->queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) if (cp == np->ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) wakeup ((caddr_t) cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) #define ncr_reg_bus_addr(r) (np->paddr + offsetof (struct ncr_reg, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) ** Initialize the fixed part of a CCB structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) static void ncr_init_ccb(struct ncb *np, struct ccb *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) ncrcmd copy_4 = np->features & FE_PFEN ? SCR_COPY(4) : SCR_COPY_F(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) ** Remember virtual and bus address of this ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) cp->p_ccb = vtobus(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) cp->phys.header.cp = cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) ** This allows list_del to work for the default ccb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) INIT_LIST_HEAD(&cp->link_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) ** Initialyze the start and restart launch script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) ** COPY(4) @(...p_phys), @(dsa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) ** JUMP @(sched_point)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) cp->start.setup_dsa[0] = cpu_to_scr(copy_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) cp->start.setup_dsa[1] = cpu_to_scr(CCB_PHYS(cp, start.p_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) cp->start.setup_dsa[2] = cpu_to_scr(ncr_reg_bus_addr(nc_dsa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) cp->start.schedule.l_cmd = cpu_to_scr(SCR_JUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) cp->start.p_phys = cpu_to_scr(CCB_PHYS(cp, phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) memcpy(&cp->restart, &cp->start, sizeof(cp->restart));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) cp->start.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) cp->restart.schedule.l_paddr = cpu_to_scr(NCB_SCRIPTH_PHYS (np, abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) ** Allocate a CCB and initialize its fixed part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) static void ncr_alloc_ccb(struct ncb *np, u_char tn, u_char ln)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) struct lcb *lp = tp->lp[ln];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) struct ccb *cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) ** Allocate memory for this CCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) cp = m_calloc_dma(sizeof(struct ccb), "CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) if (!cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) ** Count it and initialyze it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) lp->actccbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) np->actccbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) memset(cp, 0, sizeof (*cp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) ncr_init_ccb(np, cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) ** Chain into wakeup list and free ccb queue and take it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) ** into account for tagged commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) cp->link_ccb = np->ccb->link_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) np->ccb->link_ccb = cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) list_add(&cp->link_ccbq, &lp->free_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) ** Allocation of resources for Targets/Luns/Tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) ** Target control block initialisation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) ** This data structure is fully initialized after a SCSI command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) ** has been successfully completed for this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) ** It contains a SCRIPT that is called on target reselection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) static void ncr_init_tcb (struct ncb *np, u_char tn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) ncrcmd copy_1 = np->features & FE_PFEN ? SCR_COPY(1) : SCR_COPY_F(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) int th = tn & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) ** Jump to next tcb if SFBR does not match this target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) ** JUMP IF (SFBR != #target#), @(next tcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) tp->jump_tcb.l_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) cpu_to_scr((SCR_JUMP ^ IFFALSE (DATA (0x80 + tn))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) tp->jump_tcb.l_paddr = np->jump_tcb[th].l_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) ** Load the synchronous transfer register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) ** COPY @(tp->sval), @(sxfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) tp->getscr[0] = cpu_to_scr(copy_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) tp->getscr[1] = cpu_to_scr(vtobus (&tp->sval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) tp->getscr[2] = cpu_to_scr(ncr_reg_bus_addr(nc_sxfer) ^ 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) tp->getscr[2] = cpu_to_scr(ncr_reg_bus_addr(nc_sxfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) ** Load the timing register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) ** COPY @(tp->wval), @(scntl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) tp->getscr[3] = cpu_to_scr(copy_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) tp->getscr[4] = cpu_to_scr(vtobus (&tp->wval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) tp->getscr[5] = cpu_to_scr(ncr_reg_bus_addr(nc_scntl3) ^ 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) tp->getscr[5] = cpu_to_scr(ncr_reg_bus_addr(nc_scntl3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) ** Get the IDENTIFY message and the lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) ** CALL @script(resel_lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) tp->call_lun.l_cmd = cpu_to_scr(SCR_CALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) tp->call_lun.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_lun));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) ** Look for the lun control block of this nexus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) ** For i = 0 to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) ** JUMP ^ IFTRUE (MASK (i, 3)), @(next_lcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) for (i = 0 ; i < 4 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) tp->jump_lcb[i].l_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) tp->jump_lcb[i].l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_identify));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) ** Link this target control block to the JUMP chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) np->jump_tcb[th].l_paddr = cpu_to_scr(vtobus (&tp->jump_tcb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) ** These assert's should be moved at driver initialisations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) #ifdef SCSI_NCR_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) BUG_ON(((offsetof(struct ncr_reg, nc_sxfer) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) offsetof(struct tcb , sval )) &3) != 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) BUG_ON(((offsetof(struct ncr_reg, nc_scntl3) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) offsetof(struct tcb , wval )) &3) != 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) BUG_ON(((offsetof(struct ncr_reg, nc_sxfer) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) offsetof(struct tcb , sval )) &3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) BUG_ON(((offsetof(struct ncr_reg, nc_scntl3) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) offsetof(struct tcb , wval )) &3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) ** Lun control block allocation and initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) ** This data structure is allocated and initialized after a SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) ** command has been successfully completed for this target/lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) static struct lcb *ncr_alloc_lcb (struct ncb *np, u_char tn, u_char ln)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) struct lcb *lp = tp->lp[ln];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) ncrcmd copy_4 = np->features & FE_PFEN ? SCR_COPY(4) : SCR_COPY_F(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) int lh = ln & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) ** Already done, return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) if (lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) return lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) ** Allocate the lcb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) lp = m_calloc_dma(sizeof(struct lcb), "LCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) if (!lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) memset(lp, 0, sizeof(*lp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) tp->lp[ln] = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) ** Initialize the target control block if not yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) if (!tp->jump_tcb.l_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) ncr_init_tcb(np, tn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) ** Initialize the CCB queue headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) INIT_LIST_HEAD(&lp->free_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) INIT_LIST_HEAD(&lp->busy_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) INIT_LIST_HEAD(&lp->wait_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) INIT_LIST_HEAD(&lp->skip_ccbq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) ** Set max CCBs to 1 and use the default 1 entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) ** jump table by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) lp->maxnxs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) lp->jump_ccb = &lp->jump_ccb_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) lp->p_jump_ccb = cpu_to_scr(vtobus(lp->jump_ccb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) ** Initilialyze the reselect script:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) ** Jump to next lcb if SFBR does not match this lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) ** Load TEMP with the CCB direct jump table bus address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) ** Get the SIMPLE TAG message and the tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) ** JUMP IF (SFBR != #lun#), @(next lcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) ** COPY @(lp->p_jump_ccb), @(temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) ** JUMP @script(resel_notag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) lp->jump_lcb.l_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) cpu_to_scr((SCR_JUMP ^ IFFALSE (MASK (0x80+ln, 0xff))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) lp->jump_lcb.l_paddr = tp->jump_lcb[lh].l_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) lp->load_jump_ccb[0] = cpu_to_scr(copy_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) lp->load_jump_ccb[1] = cpu_to_scr(vtobus (&lp->p_jump_ccb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) lp->load_jump_ccb[2] = cpu_to_scr(ncr_reg_bus_addr(nc_temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) lp->jump_tag.l_cmd = cpu_to_scr(SCR_JUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) lp->jump_tag.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_notag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) ** Link this lun control block to the JUMP chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) tp->jump_lcb[lh].l_paddr = cpu_to_scr(vtobus (&lp->jump_lcb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) ** Initialize command queuing control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) lp->busyccbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) lp->queuedccbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) lp->queuedepth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) return lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) ** Lun control block setup on INQUIRY data received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) ** We only support WIDE, SYNC for targets and CMDQ for logical units.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) ** This setup is done on each INQUIRY since we are expecting user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) ** will play with CHANGE DEFINITION commands. :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) **------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) static struct lcb *ncr_setup_lcb (struct ncb *np, struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) unsigned char tn = sdev->id, ln = sdev->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) struct tcb *tp = &np->target[tn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) struct lcb *lp = tp->lp[ln];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) /* If no lcb, try to allocate it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) if (!lp && !(lp = ncr_alloc_lcb(np, tn, ln)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) ** If unit supports tagged commands, allocate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) ** CCB JUMP table if not yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) if (sdev->tagged_supported && lp->jump_ccb == &lp->jump_ccb_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) lp->jump_ccb = m_calloc_dma(256, "JUMP_CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) if (!lp->jump_ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591) lp->jump_ccb = &lp->jump_ccb_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) lp->p_jump_ccb = cpu_to_scr(vtobus(lp->jump_ccb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) for (i = 0 ; i < 64 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) lp->jump_ccb[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_i_t_l_q));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) for (i = 0 ; i < MAX_TAGS ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) lp->cb_tags[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) lp->maxnxs = MAX_TAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) lp->tags_stime = jiffies + 3*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) ncr_setup_tags (np, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) return lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) ** Build Scatter Gather Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) ** The transfer area may be scattered among
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) ** several non adjacent physical pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) ** We may use MAX_SCATTER blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) ** We try to reduce the number of interrupts caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) ** by unexpected phase changes due to disconnects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) ** A typical harddisk may disconnect before ANY block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) ** If we wanted to avoid unexpected phase changes at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) ** we had to use a break point every 512 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) ** Of course the number of scatter/gather blocks is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) ** limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) ** Under Linux, the scatter/gatter blocks are provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) ** the generic driver. We just have to copy addresses and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) ** sizes to the data segment array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) static int ncr_scatter(struct ncb *np, struct ccb *cp, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) int segment = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) int use_sg = scsi_sg_count(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) cp->data_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) use_sg = map_scsi_sg_data(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) if (use_sg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) struct scr_tblmove *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) if (use_sg > MAX_SCATTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) unmap_scsi_data(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) data = &cp->phys.data[MAX_SCATTER - use_sg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) scsi_for_each_sg(cmd, sg, use_sg, segment) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) dma_addr_t baddr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) unsigned int len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) ncr_build_sge(np, &data[segment], baddr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) cp->data_len += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) segment = -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) return segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) ** Test the bus snoop logic :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) ** Has to be called with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) static int __init ncr_regtest (struct ncb* np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) register volatile u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) ** ncr registers may NOT be cached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) ** write 0xffffffff to a read only register area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) ** and try to read it back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) data = INL_OFF(offsetof(struct ncr_reg, nc_dstat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) if (data == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) if ((data & 0xe2f0fffd) != 0x02000080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) printk ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) (unsigned) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) return (0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) static int __init ncr_snooptest (struct ncb* np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) u32 ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) int i, err=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) if (np->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) err |= ncr_regtest (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) return (err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) /* init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) pc = NCB_SCRIPTH_PHYS (np, snooptest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) host_wr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) ncr_wr = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) ** Set memory and register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) np->ncr_cache = cpu_to_scr(host_wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) OUTL (nc_temp, ncr_wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) ** Start script (exchange values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) OUTL_DSP (pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) ** Wait 'til done (with timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) for (i=0; i<NCR_SNOOP_TIMEOUT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) if (INB(nc_istat) & (INTF|SIP|DIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) ** Save termination position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) pc = INL (nc_dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) ** Read memory and register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) host_rd = scr_to_cpu(np->ncr_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) ncr_rd = INL (nc_scratcha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) ncr_bk = INL (nc_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) ** Reset ncr chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) ncr_chip_reset(np, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) ** check for timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) if (i>=NCR_SNOOP_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) printk ("CACHE TEST FAILED: timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) return (0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) ** Check termination position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) printk ("CACHE TEST FAILED: script execution failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) printk ("start=%08lx, pc=%08lx, end=%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) return (0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766) ** Show results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) if (host_wr != ncr_rd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) printk ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) (int) host_wr, (int) ncr_rd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) err |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) if (host_rd != ncr_wr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) printk ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) (int) ncr_wr, (int) host_rd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) err |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) if (ncr_bk != ncr_wr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) printk ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) (int) ncr_wr, (int) ncr_bk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) err |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) return (err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) ** Determine the ncr's clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) ** This is essential for the negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) ** of the synchronous transfer rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) ** Note: we have to return the correct value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) ** THERE IS NO SAFE DEFAULT VALUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) ** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) ** 53C860 and 53C875 rev. 1 support fast20 transfers but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) ** do not have a clock doubler and so are provided with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) ** 80 MHz clock. All other fast20 boards incorporate a doubler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) ** and so should be delivered with a 40 MHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802) ** The future fast40 chips (895/895) use a 40 Mhz base clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) ** and provide a clock quadrupler (160 Mhz). The code below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) ** tries to deal as cleverly as possible with all this stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) **----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) * Select NCR SCSI clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) static void ncr_selectclock(struct ncb *np, u_char scntl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814) if (np->multiplier < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) OUTB(nc_scntl3, scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) if (bootverbose >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) printk ("%s: enabling clock multiplier\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) int i = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825) while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) printk("%s: the chip cannot lock the frequency\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) } else /* Wait 20 micro-seconds for doubler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) OUTB(nc_stest3, HSC); /* Halt the scsi clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) OUTB(nc_scntl3, scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) OUTB(nc_stest3, 0x00); /* Restart scsi clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) * calculate NCR SCSI clock frequency (in KHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841) static unsigned __init ncrgetfreq (struct ncb *np, int gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) unsigned ms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) char count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) * Measure GEN timer delay in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) * to calculate SCSI clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850) * This code will never execute too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) * many loop iterations (if DELAY is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) * reasonably correct). It could get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) * too low a delay (too high a freq.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854) * if the CPU is slow executing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) * loop for some reason (an NMI, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) * example). For this reason we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) * if multiple measurements are to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) * performed trust the higher delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859) * (lower frequency returned).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) OUTW (nc_sien , 0); /* mask all scsi interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863) (void) INW (nc_sist); /* clear pending scsi interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) OUTB (nc_dien , 0); /* mask all dma interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) (void) INW (nc_sist); /* another one, just to be sure :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) OUTB (nc_stime1, 0); /* disable general purpose timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) while (!(INW(nc_sist) & GEN) && ms++ < 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) for (count = 0; count < 10; count ++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871) udelay(100); /* count ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) OUTB (nc_stime1, 0); /* disable general purpose timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) * set prescaler to divide by whatever 0 means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) * 0 ought to choose divide by 2, but appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) * to set divide by 3.5 mode in my 53c810 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) OUTB (nc_scntl3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) if (bootverbose >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) printk ("%s: Delay (GEN=%d): %u msec\n", ncr_name(np), gen, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) * adjust for prescaler, and convert into KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) return ms ? ((1 << gen) * 4340) / ms : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) * Get/probe NCR SCSI clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) static void __init ncr_getclock (struct ncb *np, int mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) unsigned char scntl3 = INB(nc_scntl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) unsigned char stest1 = INB(nc_stest1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) unsigned f1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) np->multiplier = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) f1 = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) ** True with 875 or 895 with clock multiplier selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905) if (bootverbose >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) printk ("%s: clock multiplier found\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) np->multiplier = mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911) ** If multiplier not found or scntl3 not 7,5,3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) ** reset chip and get frequency from general purpose timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913) ** Otherwise trust scntl3 BIOS setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) unsigned f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) ncr_chip_reset(np, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) (void) ncrgetfreq (np, 11); /* throw away first result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) f1 = ncrgetfreq (np, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) f2 = ncrgetfreq (np, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) if(bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) printk ("%s: NCR clock is %uKHz, %uKHz\n", ncr_name(np), f1, f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) if (f1 > f2) f1 = f2; /* trust lower result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) if (f1 < 45000) f1 = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) else if (f1 < 55000) f1 = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) else f1 = 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) if (f1 < 80000 && mult > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) if (bootverbose >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) printk ("%s: clock multiplier assumed\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) np->multiplier = mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) if ((scntl3 & 7) == 3) f1 = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) else if ((scntl3 & 7) == 5) f1 = 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) else f1 = 160000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) f1 /= np->multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) ** Compute controller synchronous parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) f1 *= np->multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) np->clock_khz = f1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) /*===================== LINUX ENTRY POINTS SECTION ==========================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) static int ncr53c8xx_slave_alloc(struct scsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) struct Scsi_Host *host = device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) struct ncb *np = ((struct host_data *) host->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) struct tcb *tp = &np->target[device->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) tp->starget = device->sdev_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) static int ncr53c8xx_slave_configure(struct scsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) struct Scsi_Host *host = device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) struct ncb *np = ((struct host_data *) host->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) struct tcb *tp = &np->target[device->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) struct lcb *lp = tp->lp[device->lun];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) int numtags, depth_to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) ncr_setup_lcb(np, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) ** Select queue depth from driver setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) ** Donnot use more than configured by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) ** Use at least 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) ** Donnot use more than our maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) numtags = device_queue_depth(np->unit, device->id, device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) if (numtags > tp->usrtags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) numtags = tp->usrtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) if (!device->tagged_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) numtags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) depth_to_use = numtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987) if (depth_to_use < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) depth_to_use = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) if (depth_to_use > MAX_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) depth_to_use = MAX_TAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) scsi_change_queue_depth(device, depth_to_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) ** Since the queue depth is not tunable under Linux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) ** we need to know this value in order not to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) ** announce stupid things to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) ** XXX(hch): As of Linux 2.6 it certainly _is_ tunable..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) ** In fact we just tuned it, or did I miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) ** something important? :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) lp->numtags = lp->maxtags = numtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) lp->scdev_depth = depth_to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) ncr_setup_tags (np, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) printk("ncr53c8xx_select_queue_depth: host=%d, id=%d, lun=%d, depth=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) np->unit, device->id, device->lun, depth_to_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014) if (spi_support_sync(device->sdev_target) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) !spi_initial_dv(device->sdev_target))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) spi_dv_device(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) static int ncr53c8xx_queue_command_lck (struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) int sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027) printk("ncr53c8xx_queue_command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) cmd->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) cmd->__data_mapped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) cmd->__data_mapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) spin_lock_irqsave(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037) if ((sts = ncr_queue_command(np, cmd)) != DID_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) cmd->result = sts << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040) printk("ncr53c8xx : command not queued - result=%d\n", sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045) printk("ncr53c8xx : command successfully queued\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) if (sts != DID_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051) unmap_scsi_data(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) sts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) return sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) static DEF_SCSI_QCMD(ncr53c8xx_queue_command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) irqreturn_t ncr53c8xx_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) struct Scsi_Host *shost = (struct Scsi_Host *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) struct host_data *host_data = (struct host_data *)shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) struct ncb *np = host_data->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) struct scsi_cmnd *done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) printk("ncr53c8xx : interrupt received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) if (DEBUG_FLAGS & DEBUG_TINY) printk ("[");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075) spin_lock_irqsave(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) ncr_exception(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077) done_list = np->done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078) np->done_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) if (DEBUG_FLAGS & DEBUG_TINY) printk ("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) if (done_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084) ncr_flush_done_cmds(done_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088) static void ncr53c8xx_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) struct ncb *np = from_timer(np, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) struct scsi_cmnd *done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094) spin_lock_irqsave(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) ncr_timeout(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) done_list = np->done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097) np->done_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) if (done_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101) ncr_flush_done_cmds(done_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) static int ncr53c8xx_bus_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) int sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) struct scsi_cmnd *done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112) * If the mid-level driver told us reset is synchronous, it seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) * that we must call the done() callback for the involved command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114) * even if this command was not queued to the low-level driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) * before returning SUCCESS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) spin_lock_irqsave(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) sts = ncr_reset_bus(np, cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121) done_list = np->done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) np->done_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) ncr_flush_done_cmds(done_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127) return sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130) #if 0 /* unused and broken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131) static int ncr53c8xx_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133) struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134) int sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) struct scsi_cmnd *done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) printk("ncr53c8xx_abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) NCR_LOCK_NCB(np, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) sts = ncr_abort_command(np, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) done_list = np->done_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) np->done_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146) NCR_UNLOCK_NCB(np, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) ncr_flush_done_cmds(done_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150) return sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156) ** Scsi command waiting list management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) ** It may happen that we cannot insert a scsi command into the start queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) ** in the following circumstances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) ** Too few preallocated ccb(s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161) ** maxtags < cmd_per_lun of the Linux host control block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) ** etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) ** Such scsi commands are inserted into a waiting list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) ** When a scsi command complete, we try to requeue the commands of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165) ** waiting list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) #define next_wcmd host_scribble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170) static void insert_into_waiting_list(struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172) struct scsi_cmnd *wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174) #ifdef DEBUG_WAITING_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) printk("%s: cmd %lx inserted into waiting list\n", ncr_name(np), (u_long) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) cmd->next_wcmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178) if (!(wcmd = np->waiting_list)) np->waiting_list = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180) while (wcmd->next_wcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) wcmd = (struct scsi_cmnd *) wcmd->next_wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182) wcmd->next_wcmd = (char *) cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188) struct scsi_cmnd **pcmd = &np->waiting_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190) while (*pcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) if (cmd == *pcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192) if (to_remove) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) *pcmd = (struct scsi_cmnd *) cmd->next_wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) cmd->next_wcmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196) #ifdef DEBUG_WAITING_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) printk("%s: cmd %lx retrieved from waiting list\n", ncr_name(np), (u_long) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199) return cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) pcmd = (struct scsi_cmnd **) &(*pcmd)->next_wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206) static void process_waiting_list(struct ncb *np, int sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208) struct scsi_cmnd *waiting_list, *wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210) waiting_list = np->waiting_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) np->waiting_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) #ifdef DEBUG_WAITING_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214) if (waiting_list) printk("%s: waiting_list=%lx processing sts=%d\n", ncr_name(np), (u_long) waiting_list, sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) while ((wcmd = waiting_list) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217) waiting_list = (struct scsi_cmnd *) wcmd->next_wcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) wcmd->next_wcmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) if (sts == DID_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220) #ifdef DEBUG_WAITING_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221) printk("%s: cmd %lx trying to requeue\n", ncr_name(np), (u_long) wcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) sts = ncr_queue_command(np, wcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) if (sts != DID_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226) #ifdef DEBUG_WAITING_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227) printk("%s: cmd %lx done forced sts=%d\n", ncr_name(np), (u_long) wcmd, sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) wcmd->result = sts << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) ncr_queue_done_cmd(np, wcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) #undef next_wcmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) static ssize_t show_ncr53c8xx_revision(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240) struct Scsi_Host *host = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) struct host_data *host_data = (struct host_data *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243) return snprintf(buf, 20, "0x%x\n", host_data->ncb->revision_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) static struct device_attribute ncr53c8xx_revision_attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) .attr = { .name = "revision", .mode = S_IRUGO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248) .show = show_ncr53c8xx_revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) static struct device_attribute *ncr53c8xx_host_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252) &ncr53c8xx_revision_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256) /*==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) ** Boot command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260) **==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) char *ncr53c8xx; /* command line passed by insmod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264) module_param(ncr53c8xx, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268) static int __init ncr53c8xx_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270) return sym53c8xx__setup(str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) __setup("ncr53c8xx=", ncr53c8xx_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) * Host attach and initialisations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) * Allocate host data and ncb structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281) * Request IO region and remap MMIO region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) * Do chip initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) * If all is OK, install interrupt handling and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284) * start the timer daemon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) struct Scsi_Host * __init ncr_attach(struct scsi_host_template *tpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) int unit, struct ncr_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) struct host_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) struct ncb *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) struct Scsi_Host *instance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) u_long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295) if (!tpnt->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296) tpnt->name = SCSI_NCR_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) if (!tpnt->shost_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) tpnt->shost_attrs = ncr53c8xx_host_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) tpnt->queuecommand = ncr53c8xx_queue_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301) tpnt->slave_configure = ncr53c8xx_slave_configure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302) tpnt->slave_alloc = ncr53c8xx_slave_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303) tpnt->eh_bus_reset_handler = ncr53c8xx_bus_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) tpnt->can_queue = SCSI_NCR_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305) tpnt->this_id = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306) tpnt->sg_tablesize = SCSI_NCR_SG_TABLESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307) tpnt->cmd_per_lun = SCSI_NCR_CMD_PER_LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309) if (device->differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) driver_setup.diff_support = device->differential;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) printk(KERN_INFO "ncr53c720-%d: rev 0x%x irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) unit, device->chip.revision_id, device->slot.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315) instance = scsi_host_alloc(tpnt, sizeof(*host_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) host_data = (struct host_data *) instance->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) np = __m_calloc_dma(device->dev, sizeof(struct ncb), "NCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323) spin_lock_init(&np->smp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) np->dev = device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325) np->p_ncb = vtobus(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326) host_data->ncb = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) np->ccb = m_calloc_dma(sizeof(struct ccb), "CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) if (!np->ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) /* Store input information in the host data structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) np->unit = unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) np->verbose = driver_setup.verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335) sprintf(np->inst_name, "ncr53c720-%d", np->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) np->revision_id = device->chip.revision_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) np->features = device->chip.features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) np->clock_divn = device->chip.nr_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339) np->maxoffs = device->chip.offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) np->maxburst = device->chip.burst_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) np->myaddr = device->host_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343) /* Allocate SCRIPTS areas. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) np->script0 = m_calloc_dma(sizeof(struct script), "SCRIPT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) if (!np->script0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347) np->scripth0 = m_calloc_dma(sizeof(struct scripth), "SCRIPTH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) if (!np->scripth0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351) timer_setup(&np->timer, ncr53c8xx_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353) /* Try to map the controller chip to virtual and physical memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355) np->paddr = device->slot.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) np->paddr2 = (np->features & FE_RAM) ? device->slot.base_2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358) if (device->slot.base_v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359) np->vaddr = device->slot.base_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) np->vaddr = ioremap(device->slot.base_c, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363) if (!np->vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) "%s: can't map memory mapped IO region\n",ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368) if (bootverbose > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370) "%s: using memory mapped IO at virtual address 0x%lx\n", ncr_name(np), (u_long) np->vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373) /* Make the controller's registers available. Now the INB INW INL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) * OUTB OUTW OUTL macros can be used safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377) np->reg = (struct ncr_reg __iomem *)np->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379) /* Do chip dependent initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) ncr_prepare_setting(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) if (np->paddr2 && sizeof(struct script) > 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383) np->paddr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384) printk(KERN_WARNING "%s: script too large, NOT using on chip RAM.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385) ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388) instance->max_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) instance->this_id = np->myaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) instance->max_id = np->maxwide ? 16 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391) instance->max_lun = SCSI_NCR_MAX_LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392) instance->base = (unsigned long) np->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) instance->irq = device->slot.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394) instance->unique_id = device->slot.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395) instance->dma_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396) instance->cmd_per_lun = MAX_TAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) instance->can_queue = (MAX_START-4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) /* This can happen if you forget to call ncr53c8xx_init from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399) * your module_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400) BUG_ON(!ncr53c8xx_transport_template);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) instance->transportt = ncr53c8xx_transport_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403) /* Patch script to physical addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404) ncr_script_fill(&script0, &scripth0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406) np->scripth = np->scripth0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407) np->p_scripth = vtobus(np->scripth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408) np->p_script = (np->paddr2) ? np->paddr2 : vtobus(np->script0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) ncr_script_copy_and_bind(np, (ncrcmd *) &script0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411) (ncrcmd *) np->script0, sizeof(struct script));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412) ncr_script_copy_and_bind(np, (ncrcmd *) &scripth0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) (ncrcmd *) np->scripth0, sizeof(struct scripth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414) np->ccb->p_ccb = vtobus (np->ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) /* Patch the script for LED support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) if (np->features & FE_LED0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419) np->script0->idle[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) cpu_to_scr(SCR_REG_REG(gpreg, SCR_OR, 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) np->script0->reselected[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422) cpu_to_scr(SCR_REG_REG(gpreg, SCR_AND, 0xfe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423) np->script0->start[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) cpu_to_scr(SCR_REG_REG(gpreg, SCR_AND, 0xfe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) * Look for the target control block of this nexus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429) * For i = 0 to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) * JUMP ^ IFTRUE (MASK (i, 3)), @(next_lcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432) for (i = 0 ; i < 4 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) np->jump_tcb[i].l_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434) cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435) np->jump_tcb[i].l_paddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_target));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439) ncr_chip_reset(np, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441) /* Now check the cache handling of the chipset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) if (ncr_snooptest(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444) printk(KERN_ERR "CACHE INCORRECTLY CONFIGURED.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) /* Install the interrupt handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) np->irq = device->slot.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) /* Initialize the fixed part of the default ccb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) ncr_init_ccb(np, np->ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) * After SCSI devices have been opened, we cannot reset the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) * safely, so we do it here. Interrupt handler does the real work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457) * Process the reset exception if interrupts are not enabled yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458) * Then enable disconnects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) spin_lock_irqsave(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461) if (ncr_reset_scsi_bus(np, 0, driver_setup.settle_delay) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462) printk(KERN_ERR "%s: FATAL ERROR: CHECK SCSI BUS - CABLES, TERMINATION, DEVICE POWER etc.!\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) goto attach_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467) ncr_exception(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469) np->disc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) * The middle-level SCSI driver does not wait for devices to settle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) * Wait synchronously if more than 2 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475) if (driver_setup.settle_delay > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476) printk(KERN_INFO "%s: waiting %d seconds for scsi devices to settle...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) ncr_name(np), driver_setup.settle_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478) mdelay(1000 * driver_setup.settle_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481) /* start the timeout daemon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482) np->lasttime=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483) ncr_timeout (np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485) /* use SIMPLE TAG messages by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486) #ifdef SCSI_NCR_ALWAYS_SIMPLE_TAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487) np->order = SIMPLE_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) spin_unlock_irqrestore(&np->smp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492) return instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) attach_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) printk(KERN_INFO "%s: detaching...\n", ncr_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) if (np->scripth0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501) m_free_dma(np->scripth0, sizeof(struct scripth), "SCRIPTH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502) if (np->script0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) m_free_dma(np->script0, sizeof(struct script), "SCRIPT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) if (np->ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505) m_free_dma(np->ccb, sizeof(struct ccb), "CCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) m_free_dma(np, sizeof(struct ncb), "NCB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) host_data->ncb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) scsi_host_put(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) void ncr53c8xx_release(struct Scsi_Host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) struct host_data *host_data = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519) #ifdef DEBUG_NCR53C8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) printk("ncr53c8xx: release\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) if (host_data->ncb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523) ncr_detach(host_data->ncb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) static void ncr53c8xx_set_period(struct scsi_target *starget, int period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8529) struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8530) struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8531) struct tcb *tp = &np->target[starget->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8533) if (period > np->maxsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8534) period = np->maxsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8535) else if (period < np->minsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8536) period = np->minsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8538) tp->usrsync = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8540) ncr_negotiate(np, tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8543) static void ncr53c8xx_set_offset(struct scsi_target *starget, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8545) struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8546) struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8547) struct tcb *tp = &np->target[starget->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8549) if (offset > np->maxoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8550) offset = np->maxoffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8551) else if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8552) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8554) tp->maxoffs = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8556) ncr_negotiate(np, tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8559) static void ncr53c8xx_set_width(struct scsi_target *starget, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8561) struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8562) struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8563) struct tcb *tp = &np->target[starget->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8565) if (width > np->maxwide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8566) width = np->maxwide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8567) else if (width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8568) width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8570) tp->usrwide = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8572) ncr_negotiate(np, tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8575) static void ncr53c8xx_get_signalling(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8577) struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8578) enum spi_signal_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8580) switch (np->scsi_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8581) case SMODE_SE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8582) type = SPI_SIGNAL_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8584) case SMODE_HVD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8585) type = SPI_SIGNAL_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8587) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8588) type = SPI_SIGNAL_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8591) spi_signalling(shost) = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8594) static struct spi_function_template ncr53c8xx_transport_functions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8595) .set_period = ncr53c8xx_set_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8596) .show_period = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8597) .set_offset = ncr53c8xx_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8598) .show_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8599) .set_width = ncr53c8xx_set_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8600) .show_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8601) .get_signalling = ncr53c8xx_get_signalling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8604) int __init ncr53c8xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8606) ncr53c8xx_transport_template = spi_attach_transport(&ncr53c8xx_transport_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8607) if (!ncr53c8xx_transport_template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8608) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8612) void ncr53c8xx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8614) spi_release_transport(ncr53c8xx_transport_template);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8615) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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