^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver supports the newer, SCSI-based firmware interface only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2018 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on the original DAC960 driver, which has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Portions Copyright 2002 by Mylex (An IBM Business Unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _MYRS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _MYRS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MYRS_MAILBOX_TIMEOUT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MYRS_DCMD_TAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MYRS_MCMD_TAG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MYRS_LINE_BUFFER_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MYRS_PRIMARY_MONITOR_INTERVAL (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MYRS_SECONDARY_MONITOR_INTERVAL (60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Maximum number of Scatter/Gather Segments supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MYRS_SG_LIMIT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Number of Command and Status Mailboxes used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAC960 V2 Firmware Memory Mailbox Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MYRS_MAX_CMD_MBOX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MYRS_MAX_STAT_MBOX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MYRS_DCDB_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MYRS_SENSE_SIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DAC960 V2 Firmware Command Opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum myrs_cmd_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MYRS_CMD_OP_MEMCOPY = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MYRS_CMD_OP_SCSI_10_PASSTHRU = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MYRS_CMD_OP_SCSI_255_PASSTHRU = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MYRS_CMD_OP_SCSI_10 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MYRS_CMD_OP_SCSI_256 = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MYRS_CMD_OP_IOCTL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * DAC960 V2 Firmware IOCTL Opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum myrs_ioctl_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MYRS_IOCTL_GET_CTLR_INFO = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MYRS_IOCTL_GET_LDEV_INFO_VALID = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MYRS_IOCTL_GET_PDEV_INFO_VALID = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MYRS_IOCTL_GET_HEALTH_STATUS = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MYRS_IOCTL_GET_EVENT = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MYRS_IOCTL_START_DISCOVERY = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MYRS_IOCTL_SET_DEVICE_STATE = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MYRS_IOCTL_INIT_PDEV_START = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MYRS_IOCTL_INIT_PDEV_STOP = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MYRS_IOCTL_INIT_LDEV_START = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MYRS_IOCTL_INIT_LDEV_STOP = 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MYRS_IOCTL_RBLD_DEVICE_START = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MYRS_IOCTL_RBLD_DEVICE_STOP = 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MYRS_IOCTL_MAKE_CONSISTENT_START = 0x8A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MYRS_IOCTL_MAKE_CONSISTENT_STOP = 0x8B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MYRS_IOCTL_CC_START = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MYRS_IOCTL_CC_STOP = 0x8D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MYRS_IOCTL_SET_MEM_MBOX = 0x8E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MYRS_IOCTL_RESET_DEVICE = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MYRS_IOCTL_FLUSH_DEVICE_DATA = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MYRS_IOCTL_PAUSE_DEVICE = 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MYRS_IOCTL_UNPAUS_EDEVICE = 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MYRS_IOCTL_LOCATE_DEVICE = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MYRS_IOCTL_CREATE_CONFIGURATION = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MYRS_IOCTL_DELETE_LDEV = 0xC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MYRS_IOCTL_REPLACE_INTERNALDEVICE = 0xC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MYRS_IOCTL_RENAME_LDEV = 0xC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MYRS_IOCTL_ADD_CONFIGURATION = 0xC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MYRS_IOCTL_XLATE_PDEV_TO_LDEV = 0xC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MYRS_IOCTL_CLEAR_CONFIGURATION = 0xCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * DAC960 V2 Firmware Command Status Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MYRS_STATUS_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MYRS_STATUS_FAILED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MYRS_STATUS_DEVICE_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MYRS_STATUS_DEVICE_NON_RESPONSIVE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MYRS_STATUS_DEVICE_NON_RESPONSIVE2 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MYRS_STATUS_RESERVATION_CONFLICT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * DAC960 V2 Firmware Memory Type structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct myrs_mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MYRS_MEMTYPE_RESERVED = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MYRS_MEMTYPE_DRAM = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MYRS_MEMTYPE_EDRAM = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MYRS_MEMTYPE_EDO = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MYRS_MEMTYPE_SDRAM = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MYRS_MEMTYPE_LAST = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } __packed mem_type:5; /* Byte 0 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned rsvd:1; /* Byte 0 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned mem_parity:1; /* Byte 0 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned mem_ecc:1; /* Byte 0 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * DAC960 V2 Firmware Processor Type structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum myrs_cpu_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MYRS_CPUTYPE_i960CA = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MYRS_CPUTYPE_i960RD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MYRS_CPUTYPE_i960RN = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MYRS_CPUTYPE_i960RP = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MYRS_CPUTYPE_NorthBay = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MYRS_CPUTYPE_StrongArm = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MYRS_CPUTYPE_i960RM = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * DAC960 V2 Firmware Get Controller Info reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct myrs_ctlr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char rsvd1; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MYRS_SCSI_BUS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MYRS_Fibre_BUS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MYRS_PCI_BUS = 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } __packed bus; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MYRS_CTLR_DAC960E = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MYRS_CTLR_DAC960M = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MYRS_CTLR_DAC960PD = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MYRS_CTLR_DAC960PL = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MYRS_CTLR_DAC960PU = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MYRS_CTLR_DAC960PE = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MYRS_CTLR_DAC960PG = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MYRS_CTLR_DAC960PJ = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MYRS_CTLR_DAC960PTL0 = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MYRS_CTLR_DAC960PR = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MYRS_CTLR_DAC960PRL = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MYRS_CTLR_DAC960PT = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MYRS_CTLR_DAC1164P = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MYRS_CTLR_DAC960PTL1 = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MYRS_CTLR_EXR2000P = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MYRS_CTLR_EXR3000P = 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MYRS_CTLR_ACCELERAID352 = 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MYRS_CTLR_ACCELERAID170 = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MYRS_CTLR_ACCELERAID160 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MYRS_CTLR_DAC960S = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MYRS_CTLR_DAC960SU = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MYRS_CTLR_DAC960SX = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MYRS_CTLR_DAC960SF = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MYRS_CTLR_DAC960SS = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MYRS_CTLR_DAC960FL = 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MYRS_CTLR_DAC960LL = 0x66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MYRS_CTLR_DAC960FF = 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MYRS_CTLR_DAC960HP = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MYRS_CTLR_RAIDBRICK = 0x69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MYRS_CTLR_METEOR_FL = 0x6A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MYRS_CTLR_METEOR_FF = 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } __packed ctlr_type; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned char rsvd2; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned short bus_speed_mhz; /* Bytes 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned char bus_width; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned char flash_code; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned char ports_present; /* Byte 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned char rsvd3[7]; /* Bytes 9-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char bus_name[16]; /* Bytes 16-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char ctlr_name[16]; /* Bytes 32-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned char rsvd4[16]; /* Bytes 48-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Firmware Release Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned char fw_major_version; /* Byte 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned char fw_minor_version; /* Byte 65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned char fw_turn_number; /* Byte 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned char fw_build_number; /* Byte 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned char fw_release_day; /* Byte 68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char fw_release_month; /* Byte 69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char fw_release_year_hi; /* Byte 70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned char fw_release_year_lo; /* Byte 71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Hardware Release Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char hw_rev; /* Byte 72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned char rsvd5[3]; /* Bytes 73-75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned char hw_release_day; /* Byte 76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned char hw_release_month; /* Byte 77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned char hw_release_year_hi; /* Byte 78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned char hw_release_year_lo; /* Byte 79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Hardware Manufacturing Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned char manuf_batch_num; /* Byte 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char rsvd6; /* Byte 81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned char manuf_plant_num; /* Byte 82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned char rsvd7; /* Byte 83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char hw_manuf_day; /* Byte 84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char hw_manuf_month; /* Byte 85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char hw_manuf_year_hi; /* Byte 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned char hw_manuf_year_lo; /* Byte 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned char max_pd_per_xld; /* Byte 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char max_ild_per_xld; /* Byte 89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned short nvram_size_kb; /* Bytes 90-91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned char max_xld; /* Byte 92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned char rsvd8[3]; /* Bytes 93-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Unique Information per Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char serial_number[16]; /* Bytes 96-111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned char rsvd9[16]; /* Bytes 112-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Vendor Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned char rsvd10[3]; /* Bytes 128-130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned char oem_code; /* Byte 131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char vendor[16]; /* Bytes 132-147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Other Physical/Controller/Operation Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char bbu_present:1; /* Byte 148 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned char cluster_mode:1; /* Byte 148 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned char rsvd11:6; /* Byte 148 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char rsvd12[3]; /* Bytes 149-151 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Physical Device Scan Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char pscan_active:1; /* Byte 152 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned char rsvd13:7; /* Byte 152 Bits 1-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned char pscan_chan; /* Byte 153 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned char pscan_target; /* Byte 154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char pscan_lun; /* Byte 155 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Maximum Command Data Transfer Sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned short max_transfer_size; /* Bytes 156-157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned short max_sge; /* Bytes 158-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Logical/Physical Device Counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned short ldev_present; /* Bytes 160-161 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned short ldev_critical; /* Bytes 162-163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned short ldev_offline; /* Bytes 164-165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned short pdev_present; /* Bytes 166-167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned short pdisk_present; /* Bytes 168-169 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned short pdisk_critical; /* Bytes 170-171 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned short pdisk_offline; /* Bytes 172-173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned short max_tcq; /* Bytes 174-175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Channel and Target ID Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char physchan_present; /* Byte 176 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char virtchan_present; /* Byte 177 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char physchan_max; /* Byte 178 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned char virtchan_max; /* Byte 179 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned char max_targets[16]; /* Bytes 180-195 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned char rsvd14[12]; /* Bytes 196-207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Memory/Cache Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned short mem_size_mb; /* Bytes 208-209 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned short cache_size_mb; /* Bytes 210-211 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int valid_cache_bytes; /* Bytes 212-215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int dirty_cache_bytes; /* Bytes 216-219 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned short mem_speed_mhz; /* Bytes 220-221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned char mem_data_width; /* Byte 222 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct myrs_mem_type mem_type; /* Byte 223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned char cache_mem_type_name[16]; /* Bytes 224-239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Execution Memory Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned short exec_mem_size_mb; /* Bytes 240-241 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned short exec_l2_cache_size_mb; /* Bytes 242-243 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned char rsvd15[8]; /* Bytes 244-251 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned short exec_mem_speed_mhz; /* Bytes 252-253 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned char exec_mem_data_width; /* Byte 254 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct myrs_mem_type exec_mem_type; /* Byte 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char exec_mem_type_name[16]; /* Bytes 256-271 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* CPU Type Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct { /* Bytes 272-335 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned short cpu_speed_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) enum myrs_cpu_type cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned char cpu_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned char rsvd16[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned char cpu_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } __packed cpu[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Debugging/Profiling/Command Time Tracing Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned short cur_prof_page_num; /* Bytes 336-337 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned short num_prof_waiters; /* Bytes 338-339 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned short cur_trace_page_num; /* Bytes 340-341 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned short num_trace_waiters; /* Bytes 342-343 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned char rsvd18[8]; /* Bytes 344-351 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Error Counters on Physical Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned short pdev_bus_resets; /* Bytes 352-353 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned short pdev_parity_errors; /* Bytes 355-355 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned short pdev_soft_errors; /* Bytes 356-357 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned short pdev_cmds_failed; /* Bytes 358-359 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned short pdev_misc_errors; /* Bytes 360-361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned short pdev_cmd_timeouts; /* Bytes 362-363 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned short pdev_sel_timeouts; /* Bytes 364-365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned short pdev_retries_done; /* Bytes 366-367 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned short pdev_aborts_done; /* Bytes 368-369 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned short pdev_host_aborts_done; /* Bytes 370-371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned short pdev_predicted_failures; /* Bytes 372-373 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned short pdev_host_cmds_failed; /* Bytes 374-375 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned short pdev_hard_errors; /* Bytes 376-377 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned char rsvd19[6]; /* Bytes 378-383 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Error Counters on Logical Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned short ldev_soft_errors; /* Bytes 384-385 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned short ldev_cmds_failed; /* Bytes 386-387 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned short ldev_host_aborts_done; /* Bytes 388-389 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned char rsvd20[2]; /* Bytes 390-391 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Error Counters on Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned short ctlr_mem_errors; /* Bytes 392-393 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned short ctlr_host_aborts_done; /* Bytes 394-395 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned char rsvd21[4]; /* Bytes 396-399 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Long Duration Activity Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned short bg_init_active; /* Bytes 400-401 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned short ldev_init_active; /* Bytes 402-403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned short pdev_init_active; /* Bytes 404-405 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned short cc_active; /* Bytes 406-407 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned short rbld_active; /* Bytes 408-409 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned short exp_active; /* Bytes 410-411 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned short patrol_active; /* Bytes 412-413 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned char rsvd22[2]; /* Bytes 414-415 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Flash ROM Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned char flash_type; /* Byte 416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned char rsvd23; /* Byte 417 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned short flash_size_MB; /* Bytes 418-419 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int flash_limit; /* Bytes 420-423 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int flash_count; /* Bytes 424-427 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned char rsvd24[4]; /* Bytes 428-431 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned char flash_type_name[16]; /* Bytes 432-447 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Firmware Run Time Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned char rbld_rate; /* Byte 448 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned char bg_init_rate; /* Byte 449 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char fg_init_rate; /* Byte 450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned char cc_rate; /* Byte 451 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned char rsvd25[4]; /* Bytes 452-455 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int max_dp; /* Bytes 456-459 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int free_dp; /* Bytes 460-463 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int max_iop; /* Bytes 464-467 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int free_iop; /* Bytes 468-471 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned short max_combined_len; /* Bytes 472-473 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned short num_cfg_groups; /* Bytes 474-475 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned installation_abort_status:1; /* Byte 476 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned maint_mode_status:1; /* Byte 476 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned rsvd26:6; /* Byte 476 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned char rsvd27[6]; /* Bytes 477-511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned char rsvd28[512]; /* Bytes 512-1023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * DAC960 V2 Firmware Device State type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum myrs_devstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MYRS_DEVICE_UNCONFIGURED = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MYRS_DEVICE_ONLINE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MYRS_DEVICE_REBUILD = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MYRS_DEVICE_MISSING = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MYRS_DEVICE_SUSPECTED_CRITICAL = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MYRS_DEVICE_OFFLINE = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MYRS_DEVICE_CRITICAL = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MYRS_DEVICE_SUSPECTED_DEAD = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MYRS_DEVICE_COMMANDED_OFFLINE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MYRS_DEVICE_STANDBY = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MYRS_DEVICE_INVALID_STATE = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * DAC960 V2 RAID Levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum myrs_raid_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MYRS_RAID_LEVEL0 = 0x0, /* RAID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MYRS_RAID_LEVEL1 = 0x1, /* RAID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MYRS_RAID_LEVEL3 = 0x3, /* RAID 3 right asymmetric parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MYRS_RAID_LEVEL5 = 0x5, /* RAID 5 right asymmetric parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MYRS_RAID_LEVEL6 = 0x6, /* RAID 6 (Mylex RAID 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MYRS_RAID_JBOD = 0x7, /* RAID 7 (JBOD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MYRS_RAID_NEWSPAN = 0x8, /* New Mylex SPAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MYRS_RAID_LEVEL3F = 0x9, /* RAID 3 fixed parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MYRS_RAID_LEVEL3L = 0xb, /* RAID 3 left symmetric parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MYRS_RAID_SPAN = 0xc, /* current spanning implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MYRS_RAID_LEVEL5L = 0xd, /* RAID 5 left symmetric parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MYRS_RAID_LEVELE = 0xe, /* RAID E (concatenation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MYRS_RAID_PHYSICAL = 0xf, /* physical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum myrs_stripe_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MYRS_STRIPE_SIZE_0 = 0x0, /* no stripe (RAID 1, RAID 7, etc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MYRS_STRIPE_SIZE_512B = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MYRS_STRIPE_SIZE_1K = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MYRS_STRIPE_SIZE_2K = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MYRS_STRIPE_SIZE_4K = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MYRS_STRIPE_SIZE_8K = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MYRS_STRIPE_SIZE_16K = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MYRS_STRIPE_SIZE_32K = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MYRS_STRIPE_SIZE_64K = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MYRS_STRIPE_SIZE_128K = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MYRS_STRIPE_SIZE_256K = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MYRS_STRIPE_SIZE_512K = 0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MYRS_STRIPE_SIZE_1M = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum myrs_cacheline_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MYRS_CACHELINE_ZERO = 0x0, /* caching cannot be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MYRS_CACHELINE_512B = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MYRS_CACHELINE_1K = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MYRS_CACHELINE_2K = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MYRS_CACHELINE_4K = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MYRS_CACHELINE_8K = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MYRS_CACHELINE_16K = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MYRS_CACHELINE_32K = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MYRS_CACHELINE_64K = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * DAC960 V2 Firmware Get Logical Device Info reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct myrs_ldev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char ctlr; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned char channel; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned char target; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned char lun; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum myrs_devstate dev_state; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned char raid_level; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) enum myrs_stripe_size stripe_size; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enum myrs_cacheline_size cacheline_size; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MYRS_READCACHE_DISABLED = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MYRS_READCACHE_ENABLED = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MYRS_READAHEAD_ENABLED = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MYRS_INTELLIGENT_READAHEAD_ENABLED = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MYRS_READCACHE_LAST = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } __packed rce:3; /* Byte 8 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MYRS_WRITECACHE_DISABLED = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MYRS_LOGICALDEVICE_RO = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MYRS_WRITECACHE_ENABLED = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MYRS_INTELLIGENT_WRITECACHE_ENABLED = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MYRS_WRITECACHE_LAST = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } __packed wce:3; /* Byte 8 Bits 3-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned rsvd1:1; /* Byte 8 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned ldev_init_done:1; /* Byte 8 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } ldev_control; /* Byte 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Logical Device Operations Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned char cc_active:1; /* Byte 9 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned char rbld_active:1; /* Byte 9 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned char bg_init_active:1; /* Byte 9 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned char fg_init_active:1; /* Byte 9 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned char migration_active:1; /* Byte 9 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned char patrol_active:1; /* Byte 9 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned char rsvd2:2; /* Byte 9 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned char raid5_writeupdate; /* Byte 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned char raid5_algo; /* Byte 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned short ldev_num; /* Bytes 12-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* BIOS Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned char bios_disabled:1; /* Byte 14 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned char cdrom_boot:1; /* Byte 14 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned char drv_coercion:1; /* Byte 14 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned char write_same_disabled:1; /* Byte 14 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned char hba_mode:1; /* Byte 14 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MYRS_GEOMETRY_128_32 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MYRS_GEOMETRY_255_63 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MYRS_GEOMETRY_RSVD1 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MYRS_GEOMETRY_RSVD2 = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } __packed drv_geom:2; /* Byte 14 Bits 5-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned char super_ra_enabled:1; /* Byte 14 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned char rsvd3; /* Byte 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Error Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned short soft_errs; /* Bytes 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned short cmds_failed; /* Bytes 18-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned short cmds_aborted; /* Bytes 20-21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned short deferred_write_errs; /* Bytes 22-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int rsvd4; /* Bytes 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int rsvd5; /* Bytes 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Device Size Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned short rsvd6; /* Bytes 32-33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned short devsize_bytes; /* Bytes 34-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int orig_devsize; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned int cfg_devsize; /* Bytes 40-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int rsvd7; /* Bytes 44-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned char ldev_name[32]; /* Bytes 48-79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned char inquiry[36]; /* Bytes 80-115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned char rsvd8[12]; /* Bytes 116-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u64 last_read_lba; /* Bytes 128-135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u64 last_write_lba; /* Bytes 136-143 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u64 cc_lba; /* Bytes 144-151 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u64 rbld_lba; /* Bytes 152-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u64 bg_init_lba; /* Bytes 160-167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u64 fg_init_lba; /* Bytes 168-175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u64 migration_lba; /* Bytes 176-183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u64 patrol_lba; /* Bytes 184-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned char rsvd9[64]; /* Bytes 192-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * DAC960 V2 Firmware Get Physical Device Info reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct myrs_pdev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned char rsvd1; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned char channel; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned char target; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned char lun; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Configuration Status Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned char pdev_fault_tolerant:1; /* Byte 4 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned char pdev_connected:1; /* Byte 4 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned char pdev_local_to_ctlr:1; /* Byte 4 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned char rsvd2:5; /* Byte 4 Bits 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Multiple Host/Controller Status Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned char remote_host_dead:1; /* Byte 5 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned char remove_ctlr_dead:1; /* Byte 5 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned char rsvd3:6; /* Byte 5 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum myrs_devstate dev_state; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned char nego_data_width; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned short nego_sync_rate; /* Bytes 8-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Multiported Physical Device Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned char num_ports; /* Byte 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned char drv_access_bitmap; /* Byte 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int rsvd4; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned char ip_address[16]; /* Bytes 16-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned short max_tags; /* Bytes 32-33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Physical Device Operations Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned char cc_in_progress:1; /* Byte 34 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned char rbld_in_progress:1; /* Byte 34 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned char makecc_in_progress:1; /* Byte 34 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned char pdevinit_in_progress:1; /* Byte 34 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned char migration_in_progress:1; /* Byte 34 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned char patrol_in_progress:1; /* Byte 34 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned char rsvd5:2; /* Byte 34 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned char long_op_status; /* Byte 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned char parity_errs; /* Byte 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned char soft_errs; /* Byte 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned char hard_errs; /* Byte 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned char misc_errs; /* Byte 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned char cmd_timeouts; /* Byte 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned char retries; /* Byte 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned char aborts; /* Byte 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned char pred_failures; /* Byte 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int rsvd6; /* Bytes 44-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned short rsvd7; /* Bytes 48-49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned short devsize_bytes; /* Bytes 50-51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int orig_devsize; /* Bytes 52-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int cfg_devsize; /* Bytes 56-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int rsvd8; /* Bytes 60-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned char pdev_name[16]; /* Bytes 64-79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned char rsvd9[16]; /* Bytes 80-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned char rsvd10[32]; /* Bytes 96-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned char inquiry[36]; /* Bytes 128-163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned char rsvd11[20]; /* Bytes 164-183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned char rsvd12[8]; /* Bytes 184-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u64 last_read_lba; /* Bytes 192-199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u64 last_write_lba; /* Bytes 200-207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u64 cc_lba; /* Bytes 208-215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u64 rbld_lba; /* Bytes 216-223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u64 makecc_lba; /* Bytes 224-231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u64 devinit_lba; /* Bytes 232-239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u64 migration_lba; /* Bytes 240-247 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u64 patrol_lba; /* Bytes 248-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned char rsvd13[256]; /* Bytes 256-511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * DAC960 V2 Firmware Health Status Buffer structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct myrs_fwstat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int uptime_usecs; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int uptime_msecs; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int seconds; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned char rsvd1[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int epoch; /* Bytes 16-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned char rsvd2[4]; /* Bytes 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int dbg_msgbuf_idx; /* Bytes 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int coded_msgbuf_idx; /* Bytes 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int cur_timetrace_page; /* Bytes 32-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned int cur_prof_page; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int next_evseq; /* Bytes 40-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned char rsvd3[4]; /* Bytes 44-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned char rsvd4[16]; /* Bytes 48-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned char rsvd5[64]; /* Bytes 64-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * DAC960 V2 Firmware Get Event reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct myrs_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int ev_seq; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int ev_time; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int ev_code; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned char rsvd1; /* Byte 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned char channel; /* Byte 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned char target; /* Byte 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned char lun; /* Byte 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int rsvd2; /* Bytes 16-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int ev_parm; /* Bytes 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned char sense_data[40]; /* Bytes 24-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * DAC960 V2 Firmware Command Control Bits structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct myrs_cmd_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned char fua:1; /* Byte 0 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned char disable_pgout:1; /* Byte 0 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned char rsvd1:1; /* Byte 0 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned char add_sge_mem:1; /* Byte 0 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned char dma_ctrl_to_host:1; /* Byte 0 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned char rsvd2:1; /* Byte 0 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned char no_autosense:1; /* Byte 0 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned char disc_prohibited:1; /* Byte 0 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * DAC960 V2 Firmware Command Timeout structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct myrs_cmd_tmo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned char tmo_val:6; /* Byte 0 Bits 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MYRS_TMO_SCALE_SECONDS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MYRS_TMO_SCALE_MINUTES = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MYRS_TMO_SCALE_HOURS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MYRS_TMO_SCALE_RESERVED = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } __packed tmo_scale:2; /* Byte 0 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * DAC960 V2 Firmware Physical Device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct myrs_pdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned char lun; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned char target; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned char channel:3; /* Byte 2 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * DAC960 V2 Firmware Logical Device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct myrs_ldev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned short ldev_num; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned char rsvd:3; /* Byte 2 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * DAC960 V2 Firmware Operation Device type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum myrs_opdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MYRS_PHYSICAL_DEVICE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MYRS_RAID_DEVICE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MYRS_PHYSICAL_CHANNEL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MYRS_RAID_CHANNEL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MYRS_PHYSICAL_CONTROLLER = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MYRS_RAID_CONTROLLER = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MYRS_CONFIGURATION_GROUP = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MYRS_ENCLOSURE = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * DAC960 V2 Firmware Translate Physical To Logical Device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct myrs_devmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned short ldev_num; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned short rsvd; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned char prev_boot_ctlr; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned char prev_boot_channel; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned char prev_boot_target; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned char prev_boot_lun; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * DAC960 V2 Firmware Scatter/Gather List Entry structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct myrs_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u64 sge_addr; /* Bytes 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u64 sge_count; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * DAC960 V2 Firmware Data Transfer Memory Address structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) union myrs_sgl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct myrs_sge sge[2]; /* Bytes 0-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned short sge0_len; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned short sge1_len; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned short sge2_len; /* Bytes 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned short rsvd; /* Bytes 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u64 sge0_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u64 sge1_addr; /* Bytes 16-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u64 sge2_addr; /* Bytes 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * 64 Byte DAC960 V2 Firmware Command Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) union myrs_cmd_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned int words[16]; /* Words 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int rsvd1:24; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned char rsvd2[10]; /* Bytes 22-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 dma_size; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct myrs_pdev pdev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned char cdb_len; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned char cdb[10]; /* Bytes 22-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } SCSI_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 dma_size; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct myrs_pdev pdev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned char cdb_len; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned short rsvd; /* Bytes 22-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u64 cdb_addr; /* Bytes 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } SCSI_255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned short rsvd1; /* Bytes 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned char ctlr_num; /* Byte 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) unsigned char rsvd2[10]; /* Bytes 22-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } ctlr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct myrs_ldev ldev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) unsigned char rsvd[10]; /* Bytes 22-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } ldev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct myrs_pdev pdev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned char rsvd[10]; /* Bytes 22-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } pdev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned short evnum_upper; /* Bytes 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned char ctlr_num; /* Byte 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned short evnum_lower; /* Bytes 22-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned char rsvd[8]; /* Bytes 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } get_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct myrs_ldev ldev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct myrs_pdev pdev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) enum myrs_devstate state; /* Byte 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned char rsvd[9]; /* Bytes 23-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } set_devstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct myrs_ldev ldev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned char restore_consistency:1; /* Byte 22 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned char initialized_area_only:1; /* Byte 22 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned char rsvd1:6; /* Byte 22 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned char rsvd2[9]; /* Bytes 23-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned char first_cmd_mbox_size_kb; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned char first_stat_mbox_size_kb; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned char second_cmd_mbox_size_kb; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned char second_stat_mbox_size_kb; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned int rsvd1:24; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned char fwstat_buf_size_kb; /* Byte 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned char rsvd2; /* Byte 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u64 fwstat_buf_addr; /* Bytes 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u64 first_cmd_mbox_addr; /* Bytes 32-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u64 first_stat_mbox_addr; /* Bytes 40-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u64 second_cmd_mbox_addr; /* Bytes 48-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u64 second_stat_mbox_addr; /* Bytes 56-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } set_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) enum myrs_cmd_opcode opcode; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct myrs_cmd_ctrl control; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u32 dma_size:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned char dma_num; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u64 sense_addr; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct myrs_pdev pdev; /* Bytes 16-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct myrs_cmd_tmo tmo; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned char sense_len; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) enum myrs_opdev opdev; /* Byte 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned char rsvd[9]; /* Bytes 23-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) union myrs_sgl dma_addr; /* Bytes 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } dev_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * DAC960 V2 Firmware Controller Status Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct myrs_stat_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned short id; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned char status; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned char sense_len; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int residual; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct myrs_cmdblk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) union myrs_cmd_mbox mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned char sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct completion *complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct myrs_sge *sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dma_addr_t sgl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) unsigned char *dcdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dma_addr_t dcdb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned char *sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dma_addr_t sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * DAC960 Driver Controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct myrs_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) phys_addr_t io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) phys_addr_t pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) unsigned char model_name[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) unsigned char fw_version[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned int epoch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned int next_evseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Monitor flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) bool needs_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) bool disable_enc_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct workqueue_struct *work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) char work_q_name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct delayed_work monitor_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) unsigned long primary_monitor_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) unsigned long secondary_monitor_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct dma_pool *sg_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct dma_pool *sense_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct dma_pool *dcdb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) void (*write_cmd_mbox)(union myrs_cmd_mbox *next_mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) union myrs_cmd_mbox *cmd_mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) void (*get_cmd_mbox)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) void (*disable_intr)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) void (*reset)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dma_addr_t cmd_mbox_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) size_t cmd_mbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) union myrs_cmd_mbox *first_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) union myrs_cmd_mbox *last_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) union myrs_cmd_mbox *next_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) union myrs_cmd_mbox *prev_cmd_mbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) union myrs_cmd_mbox *prev_cmd_mbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dma_addr_t stat_mbox_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) size_t stat_mbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct myrs_stat_mbox *first_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct myrs_stat_mbox *last_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct myrs_stat_mbox *next_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct myrs_cmdblk dcmd_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct myrs_cmdblk mcmd_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct mutex dcmd_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct myrs_fwstat *fwstat_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dma_addr_t fwstat_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct myrs_ctlr_info *ctlr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct mutex cinfo_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct myrs_event *event_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) typedef unsigned char (*enable_mbox_t)(void __iomem *base, dma_addr_t addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) typedef int (*myrs_hwinit_t)(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct myrs_hba *c, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct myrs_privdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) myrs_hwinit_t hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) irq_handler_t irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * DAC960 GEM Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define DAC960_GEM_mmio_size 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) enum DAC960_GEM_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DAC960_GEM_IDB_READ_OFFSET = 0x214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DAC960_GEM_IDB_CLEAR_OFFSET = 0x218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) DAC960_GEM_ODB_READ_OFFSET = 0x224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) DAC960_GEM_ODB_CLEAR_OFFSET = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DAC960_GEM_IRQSTS_OFFSET = 0x208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) DAC960_GEM_IRQMASK_READ_OFFSET = 0x22C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) DAC960_GEM_IRQMASK_CLEAR_OFFSET = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) DAC960_GEM_CMDMBX_OFFSET = 0x510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) DAC960_GEM_CMDSTS_OFFSET = 0x518,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) DAC960_GEM_ERRSTS_READ_OFFSET = 0x224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) DAC960_GEM_ERRSTS_CLEAR_OFFSET = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * DAC960 GEM Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define DAC960_GEM_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define DAC960_GEM_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define DAC960_GEM_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define DAC960_GEM_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define DAC960_GEM_IDB_MMBOX_NEW_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define DAC960_GEM_IDB_HWMBOX_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define DAC960_GEM_IDB_INIT_IN_PROGRESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * DAC960 GEM Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define DAC960_GEM_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define DAC960_GEM_ODB_MMBOX_ACK_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define DAC960_GEM_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define DAC960_GEM_ODB_MMBOX_STS_AVAIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * DAC960 GEM Series Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define DAC960_GEM_IRQMASK_HWMBOX_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define DAC960_GEM_IRQMASK_MMBOX_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * DAC960 GEM Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define DAC960_GEM_ERRSTS_PENDING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * dma_addr_writeql is provided to write dma_addr_t types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * to a 64-bit pci address space register. The controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * will accept having the register written as two 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * In HIGHMEM kernels, dma_addr_t is a 64-bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * without HIGHMEM, dma_addr_t is a 32-bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * The compiler should always fix up the assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * to u.wq appropriately, depending upon the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * dma_addr_t.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u64 wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) uint wl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) u.wq = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) writel(u.wl[0], write_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) writel(u.wl[1], write_address + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * DAC960 BA Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define DAC960_BA_mmio_size 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) enum DAC960_BA_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) DAC960_BA_IRQSTS_OFFSET = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) DAC960_BA_IRQMASK_OFFSET = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) DAC960_BA_CMDMBX_OFFSET = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) DAC960_BA_CMDSTS_OFFSET = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) DAC960_BA_IDB_OFFSET = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) DAC960_BA_ODB_OFFSET = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) DAC960_BA_ERRSTS_OFFSET = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * DAC960 BA Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define DAC960_BA_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define DAC960_BA_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define DAC960_BA_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define DAC960_BA_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define DAC960_BA_IDB_MMBOX_NEW_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define DAC960_BA_IDB_HWMBOX_EMPTY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define DAC960_BA_IDB_INIT_DONE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * DAC960 BA Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define DAC960_BA_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define DAC960_BA_ODB_MMBOX_ACK_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define DAC960_BA_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define DAC960_BA_ODB_MMBOX_STS_AVAIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * DAC960 BA Series Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define DAC960_BA_IRQMASK_DISABLE_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define DAC960_BA_IRQMASK_DISABLEW_I2O 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * DAC960 BA Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define DAC960_BA_ERRSTS_PENDING 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * DAC960 LP Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define DAC960_LP_mmio_size 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) enum DAC960_LP_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) DAC960_LP_CMDMBX_OFFSET = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) DAC960_LP_CMDSTS_OFFSET = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DAC960_LP_IDB_OFFSET = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) DAC960_LP_ODB_OFFSET = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) DAC960_LP_ERRSTS_OFFSET = 0x2E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) DAC960_LP_IRQSTS_OFFSET = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DAC960_LP_IRQMASK_OFFSET = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * DAC960 LP Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define DAC960_LP_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define DAC960_LP_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define DAC960_LP_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define DAC960_LP_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define DAC960_LP_IDB_MMBOX_NEW_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define DAC960_LP_IDB_HWMBOX_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define DAC960_LP_IDB_INIT_IN_PROGRESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * DAC960 LP Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define DAC960_LP_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define DAC960_LP_ODB_MMBOX_ACK_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define DAC960_LP_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define DAC960_LP_ODB_MMBOX_STS_AVAIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * DAC960 LP Series Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define DAC960_LP_IRQMASK_DISABLE_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * DAC960 LP Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define DAC960_LP_ERRSTS_PENDING 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #endif /* _MYRS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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