^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the original DAC960 driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Portions Copyright 2002 by Mylex (An IBM Business Unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef MYRB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MYRB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MYRB_MAX_LDEVS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MYRB_MAX_CHANNELS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MYRB_MAX_TARGETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MYRB_MAX_PHYSICAL_DEVICES 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MYRB_SCATTER_GATHER_LIMIT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MYRB_CMD_MBOX_COUNT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MYRB_STAT_MBOX_COUNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MYRB_BLKSIZE_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MYRB_MAILBOX_TIMEOUT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MYRB_DCMD_TAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MYRB_MCMD_TAG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MYRB_PRIMARY_MONITOR_INTERVAL (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MYRB_SECONDARY_MONITOR_INTERVAL (60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DAC960 V1 Firmware Command Opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum myrb_cmd_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* I/O Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MYRB_CMD_READ_EXTENDED = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MYRB_CMD_WRITE_EXTENDED = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MYRB_CMD_READAHEAD_EXTENDED = 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MYRB_CMD_READ_EXTENDED_SG = 0xB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MYRB_CMD_WRITE_EXTENDED_SG = 0xB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MYRB_CMD_READ = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MYRB_CMD_READ_SG = 0xB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MYRB_CMD_WRITE = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MYRB_CMD_WRITE_SG = 0xB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MYRB_CMD_DCDB = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MYRB_CMD_DCDB_SG = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MYRB_CMD_FLUSH = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Controller Status Related Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MYRB_CMD_ENQUIRY = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MYRB_CMD_ENQUIRY2 = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MYRB_CMD_GET_LDRV_ELEMENT = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MYRB_CMD_GET_LDEV_INFO = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MYRB_CMD_IOPORTREAD = 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MYRB_CMD_IOPORTWRITE = 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MYRB_CMD_GET_SD_STATS = 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MYRB_CMD_GET_PD_STATS = 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MYRB_CMD_EVENT_LOG_OPERATION = 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Device Related Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MYRB_CMD_START_DEVICE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MYRB_CMD_GET_DEVICE_STATE = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MYRB_CMD_STOP_CHANNEL = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MYRB_CMD_START_CHANNEL = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MYRB_CMD_RESET_CHANNEL = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Commands Associated with Data Consistency and Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MYRB_CMD_REBUILD = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MYRB_CMD_REBUILD_ASYNC = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MYRB_CMD_CHECK_CONSISTENCY = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MYRB_CMD_CHECK_CONSISTENCY_ASYNC = 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MYRB_CMD_REBUILD_STAT = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MYRB_CMD_GET_REBUILD_PROGRESS = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MYRB_CMD_REBUILD_CONTROL = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MYRB_CMD_READ_BADBLOCK_TABLE = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MYRB_CMD_READ_BADDATA_TABLE = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MYRB_CMD_CLEAR_BADDATA_TABLE = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MYRB_CMD_GET_ERROR_TABLE = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MYRB_CMD_ADD_CAPACITY_ASYNC = 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MYRB_CMD_BGI_CONTROL = 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Configuration Related Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MYRB_CMD_READ_CONFIG2 = 0x3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MYRB_CMD_WRITE_CONFIG2 = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MYRB_CMD_READ_CONFIG_ONDISK = 0x4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MYRB_CMD_WRITE_CONFIG_ONDISK = 0x4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MYRB_CMD_READ_CONFIG = 0x4E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MYRB_CMD_READ_BACKUP_CONFIG = 0x4D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MYRB_CMD_WRITE_CONFIG = 0x4F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MYRB_CMD_ADD_CONFIG = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MYRB_CMD_READ_CONFIG_LABEL = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MYRB_CMD_WRITE_CONFIG_LABEL = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Firmware Upgrade Related Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MYRB_CMD_LOAD_IMAGE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MYRB_CMD_STORE_IMAGE = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MYRB_CMD_PROGRAM_IMAGE = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Diagnostic Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MYRB_CMD_SET_DIAGNOSTIC_MODE = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MYRB_CMD_RUN_DIAGNOSTIC = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Subsystem Service Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MYRB_CMD_GET_SUBSYS_DATA = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MYRB_CMD_SET_SUBSYS_PARAM = 0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Version 2.xx Firmware Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MYRB_CMD_ENQUIRY_OLD = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MYRB_CMD_GET_DEVICE_STATE_OLD = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MYRB_CMD_READ_OLD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MYRB_CMD_WRITE_OLD = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MYRB_CMD_READ_SG_OLD = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MYRB_CMD_WRITE_SG_OLD = 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * DAC960 V1 Firmware Command Status Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MYRB_STATUS_SUCCESS 0x0000 /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MYRB_STATUS_CHECK_CONDITION 0x0002 /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MYRB_STATUS_NO_DEVICE 0x0102 /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MYRB_STATUS_INVALID_ADDRESS 0x0105 /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MYRB_STATUS_INVALID_PARAM 0x0105 /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR 0x0001 /* I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE 0x0002 /* I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV 0x0105 /* I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MYRB_STATUS_BAD_DATA 0x010C /* I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MYRB_STATUS_DEVICE_BUSY 0x0008 /* DCDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MYRB_STATUS_DEVICE_NONRESPONSIVE 0x000E /* DCDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MYRB_STATUS_COMMAND_TERMINATED 0x000F /* DCDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MYRB_STATUS_START_DEVICE_FAILED 0x0002 /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET 0x0105 /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MYRB_STATUS_CHANNEL_BUSY 0x0106 /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MYRB_STATUS_OUT_OF_MEMORY 0x0107 /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MYRB_STATUS_CHANNEL_NOT_STOPPED 0x0002 /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE 0x0002 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MYRB_STATUS_RBLD_BADBLOCKS 0x0003 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MYRB_STATUS_RBLD_NEW_DISK_FAILED 0x0004 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS 0x0106 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MYRB_STATUS_DEPENDENT_DISK_DEAD 0x0002 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MYRB_STATUS_INCONSISTENT_BLOCKS 0x0003 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV 0x0105 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS 0x0105 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID 0x0000 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE 0x0002 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS 0x0003 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED 0x0004 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MYRB_STATUS_RBLD_SUCCESS 0x0100 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED 0x0107 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MYRB_STATUS_RBLD_NOT_CHECKED 0x0108 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MYRB_STATUS_BGI_SUCCESS 0x0100 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MYRB_STATUS_BGI_ABORTED 0x0005 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MYRB_STATUS_NO_BGI_INPROGRESS 0x0105 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS 0x0004 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED 0x00F4 /* Consistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MYRB_STATUS_CONFIG2_CSUM_ERROR 0x0002 /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MYRB_STATUS_CONFIGURATION_SUSPENDED 0x0106 /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM 0x0105 /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MYRB_STATUS_CONFIGURATION_NOT_SAVED 0x0106 /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MYRB_STATUS_SUBSYS_NOTINSTALLED 0x0001 /* Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MYRB_STATUS_SUBSYS_FAILED 0x0002 /* Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MYRB_STATUS_SUBSYS_BUSY 0x0106 /* Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MYRB_STATUS_SUBSYS_TIMEOUT 0x0108 /* Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * DAC960 V1 Firmware Enquiry Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct myrb_enquiry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char ldev_count; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int rsvd1:24; /* Bytes 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int ldev_sizes[32]; /* Bytes 4-131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned short flash_age; /* Bytes 132-133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char deferred:1; /* Byte 134 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned char low_bat:1; /* Byte 134 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned char rsvd2:6; /* Byte 134 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned char rsvd3:8; /* Byte 135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned char fw_minor_version; /* Byte 136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned char fw_major_version; /* Byte 137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MYRB_STDBY_RBLD_IN_PROGRESS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MYRB_BG_RBLD_IN_PROGRESS = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MYRB_BG_CHECK_IN_PROGRESS = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED = 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED = 0xF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER = 0xF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED = 0xF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } __packed rbld; /* Byte 138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char max_tcq; /* Byte 139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char ldev_offline; /* Byte 140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned char rsvd4:8; /* Byte 141 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned short ev_seq; /* Bytes 142-143 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char ldev_critical; /* Byte 144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int rsvd5:24; /* Bytes 145-147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned char pdev_dead; /* Byte 148 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned char rsvd6:8; /* Byte 149 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned char rbld_count; /* Byte 150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned char rsvd7:3; /* Byte 151 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned char bbu_present:1; /* Byte 151 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char rsvd8:4; /* Byte 151 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } dead_drives[21]; /* Bytes 152-194 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned char rsvd9[62]; /* Bytes 195-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * DAC960 V1 Firmware Enquiry2 Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct myrb_enquiry2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DAC960_V1_P_PD_PU = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DAC960_V1_PL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DAC960_V1_PG = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DAC960_V1_PJ = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DAC960_V1_PR = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DAC960_V1_PT = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DAC960_V1_PTL0 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DAC960_V1_PRL = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DAC960_V1_PTL1 = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DAC960_V1_1164P = 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } __packed sub_model; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned char actual_channels; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MYRB_5_CHANNEL_BOARD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MYRB_3_CHANNEL_BOARD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MYRB_2_CHANNEL_BOARD = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MYRB_3_CHANNEL_ASIC_DAC = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } __packed model; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MYRB_EISA_CONTROLLER = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MYRB_MCA_CONTROLLER = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MYRB_PCI_CONTROLLER = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MYRB_SCSI_TO_SCSI = 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } __packed controller; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } hw; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* MajorVersion.MinorVersion-FirmwareType-TurnID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned char major_version; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char minor_version; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char turn_id; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) char firmware_type; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } fw; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int rsvd1; /* Byte 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned char cfg_chan; /* Byte 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned char cur_chan; /* Byte 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned char max_targets; /* Byte 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned char max_tcq; /* Byte 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned char max_ldev; /* Byte 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned char max_arms; /* Byte 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned char max_spans; /* Byte 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned char rsvd2; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int rsvd3; /* Bytes 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int mem_size; /* Bytes 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int cache_size; /* Bytes 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int flash_size; /* Bytes 32-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int nvram_size; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MYRB_RAM_TYPE_DRAM = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MYRB_RAM_TYPE_EDO = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MYRB_RAM_TYPE_SDRAM = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MYRB_RAM_TYPE_Last = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } __packed ram:3; /* Byte 40 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MYRB_ERR_CORR_None = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MYRB_ERR_CORR_Parity = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MYRB_ERR_CORR_ECC = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MYRB_ERR_CORR_Last = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } __packed ec:3; /* Byte 40 Bits 3-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned char fast_page:1; /* Byte 40 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char low_power:1; /* Byte 40 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned char rsvd4; /* Bytes 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } mem_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned short clock_speed; /* Bytes 42-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned short mem_speed; /* Bytes 44-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned short hw_speed; /* Bytes 46-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char rsvd5[12]; /* Bytes 48-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned short max_cmds; /* Bytes 60-61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned short max_sge; /* Bytes 62-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned short max_drv_cmds; /* Bytes 64-65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned short max_io_desc; /* Bytes 66-67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned short max_sectors; /* Bytes 68-69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned char latency; /* Byte 70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned char rsvd6; /* Byte 71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned char scsi_tmo; /* Byte 72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned char rsvd7; /* Byte 73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned short min_freelines; /* Bytes 74-75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned char rsvd8[8]; /* Bytes 76-83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned char rbld_rate_const; /* Byte 84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned char rsvd9[11]; /* Byte 85-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned short pdrv_block_size; /* Bytes 96-97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned short ldev_block_size; /* Bytes 98-99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned short max_blocks_per_cmd; /* Bytes 100-101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned short block_factor; /* Bytes 102-103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned short cacheline_size; /* Bytes 104-105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MYRB_WIDTH_NARROW_8BIT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MYRB_WIDTH_WIDE_16BIT = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MYRB_WIDTH_WIDE_32BIT = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } __packed bus_width:2; /* Byte 106 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MYRB_SCSI_SPEED_FAST = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MYRB_SCSI_SPEED_ULTRA = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MYRB_SCSI_SPEED_ULTRA2 = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } __packed bus_speed:2; /* Byte 106 Bits 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned char differential:1; /* Byte 106 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned char rsvd10:3; /* Byte 106 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } scsi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned char rsvd11[5]; /* Byte 107-111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned short fw_build; /* Bytes 112-113 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MYRB_FAULT_AEMI = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MYRB_FAULT_OEM1 = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MYRB_FAULT_OEM2 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MYRB_FAULT_OEM3 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MYRB_FAULT_CONNER = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MYRB_FAULT_SAFTE = 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } __packed fault_mgmt; /* Byte 114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char rsvd12; /* Byte 115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int clustering:1; /* Byte 116 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int online_RAID_expansion:1; /* Byte 116 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int readahead:1; /* Byte 116 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int bgi:1; /* Byte 116 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int rsvd13:28; /* Bytes 116-119 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } fw_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned char rsvd14[8]; /* Bytes 120-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * DAC960 V1 Firmware Logical Drive State type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum myrb_devstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MYRB_DEVICE_DEAD = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MYRB_DEVICE_WO = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MYRB_DEVICE_ONLINE = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MYRB_DEVICE_CRITICAL = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MYRB_DEVICE_STANDBY = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MYRB_DEVICE_OFFLINE = 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * DAC960 V1 RAID Levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) enum myrb_raidlevel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MYRB_RAID_LEVEL0 = 0x0, /* RAID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MYRB_RAID_LEVEL1 = 0x1, /* RAID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MYRB_RAID_LEVEL3 = 0x3, /* RAID 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MYRB_RAID_LEVEL5 = 0x5, /* RAID 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MYRB_RAID_LEVEL6 = 0x6, /* RAID 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MYRB_RAID_JBOD = 0x7, /* RAID 7 (JBOD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * DAC960 V1 Firmware Logical Drive Information structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct myrb_ldev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int size; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum myrb_devstate state; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int raid_level:7; /* Byte 5 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int wb_enabled:1; /* Byte 5 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int rsvd:16; /* Bytes 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * DAC960 V1 Firmware Perform Event Log Operation Types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DAC960_V1_GetEventLogEntry 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * DAC960 V1 Firmware Get Event Log Entry Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct myrb_log_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned char msg_type; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned char msg_len; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned char target:5; /* Byte 2 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned char channel:3; /* Byte 2 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned char lun:6; /* Byte 3 Bits 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned char rsvd1:2; /* Byte 3 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned short seq_num; /* Bytes 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned char sense[26]; /* Bytes 6-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * DAC960 V1 Firmware Get Device State Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * The structure is padded by 2 bytes for compatibility with Version 2.xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct myrb_pdev_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int present:1; /* Byte 0 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int :7; /* Byte 0 Bits 1-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MYRB_TYPE_OTHER = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MYRB_TYPE_DISK = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MYRB_TYPE_TAPE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MYRB_TYPE_CDROM_OR_WORM = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } __packed devtype:2; /* Byte 1 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int rsvd1:1; /* Byte 1 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int fast20:1; /* Byte 1 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int sync:1; /* Byte 1 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int fast:1; /* Byte 1 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int wide:1; /* Byte 1 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int tcq_supported:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum myrb_devstate state; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int rsvd2:8; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int sync_multiplier; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int sync_offset:5; /* Byte 5 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int rsvd3:3; /* Byte 5 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int size; /* Bytes 6-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int rsvd4:16; /* Bytes 10-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * DAC960 V1 Firmware Get Rebuild Progress Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct myrb_rbld_progress {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int ldev_num; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int ldev_size; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int blocks_left; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * DAC960 V1 Firmware Background Initialization Status Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct myrb_bgi_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int ldev_size; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int blocks_done; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned char rsvd1[12]; /* Bytes 8-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int ldev_num; /* Bytes 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned char raid_level; /* Byte 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MYRB_BGI_INVALID = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MYRB_BGI_STARTED = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MYRB_BGI_INPROGRESS = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MYRB_BGI_SUSPENDED = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MYRB_BGI_CANCELLED = 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } __packed status; /* Byte 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned char rsvd2[6]; /* Bytes 26-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * DAC960 V1 Firmware Error Table Entry structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct myrb_error_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned char parity_err; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned char soft_err; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned char hard_err; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned char misc_err; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * DAC960 V1 Firmware Read Config2 Command reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct myrb_config2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned rsvd1:1; /* Byte 0 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned active_negation:1; /* Byte 0 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned rsvd2:5; /* Byte 0 Bits 2-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned no_rescan_on_reset_during_scan:1; /* Byte 0 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned StorageWorks_support:1; /* Byte 1 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned HewlettPackard_support:1; /* Byte 1 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned no_disconnect_on_first_command:1; /* Byte 1 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned rsvd3:2; /* Byte 1 Bits 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned AEMI_ARM:1; /* Byte 1 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned AEMI_OFM:1; /* Byte 1 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned rsvd4:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MYRB_OEMID_MYLEX = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MYRB_OEMID_IBM = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MYRB_OEMID_HP = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MYRB_OEMID_DEC = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MYRB_OEMID_SIEMENS = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MYRB_OEMID_INTEL = 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } __packed OEMID; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned char oem_model_number; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned char physical_sector; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned char logical_sector; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned char block_factor; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned readahead_enabled:1; /* Byte 7 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned low_BIOS_delay:1; /* Byte 7 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned rsvd5:2; /* Byte 7 Bits 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned restrict_reassign_to_one_sector:1; /* Byte 7 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned rsvd6:1; /* Byte 7 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned FUA_during_write_recovery:1; /* Byte 7 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned enable_LeftSymmetricRAID5Algorithm:1; /* Byte 7 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned char default_rebuild_rate; /* Byte 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned char rsvd7; /* Byte 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned char blocks_per_cacheline; /* Byte 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned char blocks_per_stripe; /* Byte 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MYRB_SPEED_ASYNC = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MYRB_SPEED_SYNC_8MHz = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MYRB_SPEED_SYNC_5MHz = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MYRB_SPEED_SYNC_10_OR_20MHz = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) } __packed speed:2; /* Byte 11 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned force_8bit:1; /* Byte 11 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned disable_fast20:1; /* Byte 11 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned rsvd8:3; /* Byte 11 Bits 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned enable_tcq:1; /* Byte 11 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } __packed channelparam[6]; /* Bytes 12-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned char SCSIInitiatorID; /* Byte 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned char rsvd9; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MYRB_STARTUP_CONTROLLER_SPINUP = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MYRB_STARTUP_POWERON_SPINUP = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } __packed startup; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned char simultaneous_device_spinup_count; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned char seconds_delay_between_spinups; /* Byte 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned char rsvd10[29]; /* Bytes 23-51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned BIOS_disabled:1; /* Byte 52 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned CDROM_boot_enabled:1; /* Byte 52 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned rsvd11:3; /* Byte 52 Bits 2-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MYRB_GEOM_128_32 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MYRB_GEOM_255_63 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MYRB_GEOM_RESERVED1 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MYRB_GEOM_RESERVED2 = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } __packed drive_geometry:2; /* Byte 52 Bits 5-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned rsvd12:1; /* Byte 52 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned char rsvd13[9]; /* Bytes 53-61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned short csum; /* Bytes 62-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * DAC960 V1 Firmware DCDB request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct myrb_dcdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned target:4; /* Byte 0 Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned channel:4; /* Byte 0 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MYRB_DCDB_XFER_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MYRB_DCDB_XFER_DEVICE_TO_SYSTEM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MYRB_DCDB_XFER_SYSTEM_TO_DEVICE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MYRB_DCDB_XFER_ILLEGAL = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } __packed data_xfer:2; /* Byte 1 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned early_status:1; /* Byte 1 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned rsvd1:1; /* Byte 1 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MYRB_DCDB_TMO_24_HRS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MYRB_DCDB_TMO_10_SECS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MYRB_DCDB_TMO_60_SECS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MYRB_DCDB_TMO_10_MINS = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } __packed timeout:2; /* Byte 1 Bits 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned no_autosense:1; /* Byte 1 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned allow_disconnect:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned short xfer_len_lo; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 dma_addr; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned char cdb_len:4; /* Byte 8 Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned char xfer_len_hi4:4; /* Byte 8 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned char sense_len; /* Byte 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned char cdb[12]; /* Bytes 10-21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned char sense[64]; /* Bytes 22-85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned char status; /* Byte 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned char rsvd2; /* Byte 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *32 Bit Byte Count structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct myrb_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 sge_addr; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 sge_count; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * 13 Byte DAC960 V1 Firmware Command Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Bytes 13-15 are not used. The structure is padded to 16 bytes for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * efficient access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) union myrb_cmd_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int words[4]; /* Words 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned char bytes[16]; /* Bytes 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned char rsvd[14]; /* Bytes 2-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } __packed common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned char rsvd1[6]; /* Bytes 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned char rsvd2[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } __packed type3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned char optype; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned char rsvd1[5]; /* Bytes 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned char rsvd2[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } __packed type3B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned char rsvd1[5]; /* Bytes 2-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned char ldev_num:6; /* Byte 7 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned char auto_restore:1; /* Byte 7 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned char rsvd2[8]; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } __packed type3C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned char channel; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned char target; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) enum myrb_devstate state; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned char rsvd1[3]; /* Bytes 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned char rsvd2[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } __packed type3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned char optype; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned char opqual; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned short ev_seq; /* Bytes 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned char rsvd1[2]; /* Bytes 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned char rsvd2[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } __packed type3E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned char rsvd1[2]; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned char rbld_rate; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned char rsvd2[3]; /* Bytes 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned char rsvd3[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) } __packed type3R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned short xfer_len; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int lba; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned char ldev_num; /* Byte 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned char rsvd[3]; /* Bytes 13-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) } __packed type4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned short xfer_len:11; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned char ldev_num:5; /* Byte 3 Bits 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } __packed ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned int lba; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned char sg_count:6; /* Byte 12 Bits 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MYRB_SGL_ADDR32_COUNT32 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MYRB_SGL_ADDR32_COUNT16 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MYRB_SGL_COUNT32_ADDR32 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MYRB_SGL_COUNT16_ADDR32 = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } __packed sg_type:2; /* Byte 12 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) unsigned char rsvd[3]; /* Bytes 13-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } __packed type5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) enum myrb_cmd_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned char id; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned char opcode2; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned char rsvd1:8; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 cmd_mbox_addr; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 stat_mbox_addr; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned char rsvd2[4]; /* Bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } __packed typeX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * DAC960 V1 Firmware Controller Status Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct myrb_stat_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned char id; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned char rsvd:7; /* Byte 1 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned char valid:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned short status; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct myrb_cmdblk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) union myrb_cmd_mbox mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct completion *completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct myrb_dcdb *dcdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dma_addr_t dcdb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct myrb_sge *sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dma_addr_t sgl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct myrb_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned int ldev_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned char ldev_geom_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned char ldev_geom_sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned char bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned short stripe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned short segment_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned short new_ev_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned short old_ev_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) bool dual_mode_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bool bgi_status_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bool safte_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) bool need_ldev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bool need_err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) bool need_rbld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bool need_cc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bool need_bgi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bool rbld_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct workqueue_struct *work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) char work_q_name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct delayed_work monitor_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned long primary_monitor_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long secondary_monitor_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct dma_pool *sg_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct dma_pool *dcdb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) void (*qcmd)(struct myrb_hba *cs, struct myrb_cmdblk *cmd_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void (*write_cmd_mbox)(union myrb_cmd_mbox *next_mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) union myrb_cmd_mbox *cmd_mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) void (*get_cmd_mbox)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) void (*disable_intr)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) void (*reset)(void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int ctlr_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned char model_name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned char fw_version[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) phys_addr_t io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) phys_addr_t pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) size_t cmd_mbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dma_addr_t cmd_mbox_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) union myrb_cmd_mbox *first_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) union myrb_cmd_mbox *last_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) union myrb_cmd_mbox *next_cmd_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) union myrb_cmd_mbox *prev_cmd_mbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) union myrb_cmd_mbox *prev_cmd_mbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) size_t stat_mbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dma_addr_t stat_mbox_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct myrb_stat_mbox *first_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct myrb_stat_mbox *last_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct myrb_stat_mbox *next_stat_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct myrb_cmdblk dcmd_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct myrb_cmdblk mcmd_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct mutex dcmd_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct myrb_enquiry *enquiry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dma_addr_t enquiry_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct myrb_error_entry *err_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dma_addr_t err_table_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned short last_rbld_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct myrb_ldev_info *ldev_info_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dma_addr_t ldev_info_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct myrb_bgi_status bgi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct mutex dma_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * DAC960 LA Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define DAC960_LA_mmio_size 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) enum DAC960_LA_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DAC960_LA_IRQMASK_OFFSET = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DAC960_LA_CMDOP_OFFSET = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DAC960_LA_CMDID_OFFSET = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DAC960_LA_MBOX2_OFFSET = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DAC960_LA_MBOX3_OFFSET = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DAC960_LA_MBOX4_OFFSET = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DAC960_LA_MBOX5_OFFSET = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DAC960_LA_MBOX6_OFFSET = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DAC960_LA_MBOX7_OFFSET = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DAC960_LA_MBOX8_OFFSET = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DAC960_LA_MBOX9_OFFSET = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DAC960_LA_MBOX10_OFFSET = 0x5A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DAC960_LA_MBOX11_OFFSET = 0x5B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DAC960_LA_MBOX12_OFFSET = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DAC960_LA_STSID_OFFSET = 0x5D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DAC960_LA_STS_OFFSET = 0x5E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DAC960_LA_IDB_OFFSET = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DAC960_LA_ODB_OFFSET = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DAC960_LA_ERRSTS_OFFSET = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * DAC960 LA Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define DAC960_LA_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define DAC960_LA_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define DAC960_LA_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define DAC960_LA_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define DAC960_LA_IDB_MMBOX_NEW_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define DAC960_LA_IDB_HWMBOX_EMPTY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define DAC960_LA_IDB_INIT_DONE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * DAC960 LA Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define DAC960_LA_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define DAC960_LA_ODB_MMBOX_ACK_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DAC960_LA_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DAC960_LA_ODB_MMBOX_STS_AVAIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * DAC960 LA Series Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define DAC960_LA_IRQMASK_DISABLE_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * DAC960 LA Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DAC960_LA_ERRSTS_PENDING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * DAC960 PG Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define DAC960_PG_mmio_size 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) enum DAC960_PG_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DAC960_PG_IDB_OFFSET = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) DAC960_PG_ODB_OFFSET = 0x002C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) DAC960_PG_IRQMASK_OFFSET = 0x0034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) DAC960_PG_CMDOP_OFFSET = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) DAC960_PG_CMDID_OFFSET = 0x1001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) DAC960_PG_MBOX2_OFFSET = 0x1002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DAC960_PG_MBOX3_OFFSET = 0x1003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DAC960_PG_MBOX4_OFFSET = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DAC960_PG_MBOX5_OFFSET = 0x1005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DAC960_PG_MBOX6_OFFSET = 0x1006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) DAC960_PG_MBOX7_OFFSET = 0x1007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) DAC960_PG_MBOX8_OFFSET = 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) DAC960_PG_MBOX9_OFFSET = 0x1009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DAC960_PG_MBOX10_OFFSET = 0x100A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DAC960_PG_MBOX11_OFFSET = 0x100B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DAC960_PG_MBOX12_OFFSET = 0x100C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DAC960_PG_STSID_OFFSET = 0x1018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DAC960_PG_STS_OFFSET = 0x101A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) DAC960_PG_ERRSTS_OFFSET = 0x103F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * DAC960 PG Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define DAC960_PG_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define DAC960_PG_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define DAC960_PG_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define DAC960_PG_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define DAC960_PG_IDB_MMBOX_NEW_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define DAC960_PG_IDB_HWMBOX_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DAC960_PG_IDB_INIT_IN_PROGRESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * DAC960 PG Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DAC960_PG_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DAC960_PG_ODB_MMBOX_ACK_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DAC960_PG_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define DAC960_PG_ODB_MMBOX_STS_AVAIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * DAC960 PG Series Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DAC960_PG_IRQMASK_MSI_MASK1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DAC960_PG_IRQMASK_DISABLE_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define DAC960_PG_IRQMASK_MSI_MASK2 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * DAC960 PG Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define DAC960_PG_ERRSTS_PENDING 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * DAC960 PD Series Controller Interface Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DAC960_PD_mmio_size 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) enum DAC960_PD_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DAC960_PD_CMDOP_OFFSET = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DAC960_PD_CMDID_OFFSET = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DAC960_PD_MBOX2_OFFSET = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DAC960_PD_MBOX3_OFFSET = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DAC960_PD_MBOX4_OFFSET = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DAC960_PD_MBOX5_OFFSET = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DAC960_PD_MBOX6_OFFSET = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DAC960_PD_MBOX7_OFFSET = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DAC960_PD_MBOX8_OFFSET = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DAC960_PD_MBOX9_OFFSET = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DAC960_PD_MBOX10_OFFSET = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DAC960_PD_MBOX11_OFFSET = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DAC960_PD_MBOX12_OFFSET = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) DAC960_PD_STSID_OFFSET = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) DAC960_PD_STS_OFFSET = 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) DAC960_PD_ERRSTS_OFFSET = 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DAC960_PD_IDB_OFFSET = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DAC960_PD_ODB_OFFSET = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DAC960_PD_IRQEN_OFFSET = 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * DAC960 PD Series Inbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define DAC960_PD_IDB_HWMBOX_NEW_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define DAC960_PD_IDB_HWMBOX_ACK_STS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define DAC960_PD_IDB_GEN_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define DAC960_PD_IDB_CTRL_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define DAC960_PD_IDB_HWMBOX_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define DAC960_PD_IDB_INIT_IN_PROGRESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * DAC960 PD Series Outbound Door Bell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DAC960_PD_ODB_HWMBOX_ACK_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DAC960_PD_ODB_HWMBOX_STS_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * DAC960 PD Series Interrupt Enable Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define DAC960_PD_IRQMASK_ENABLE_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * DAC960 PD Series Error Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define DAC960_PD_ERRSTS_PENDING 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) typedef int (*myrb_hw_init_t)(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct myrb_hba *cb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) typedef unsigned short (*mbox_mmio_init_t)(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) union myrb_cmd_mbox *mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct myrb_privdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) myrb_hw_init_t hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) irq_handler_t irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unsigned int mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #endif /* MYRB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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