Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)   * Marvell UMI head file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)   *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)   * Copyright 2011 Marvell. <jyli@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef MVUMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define MVUMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MAX_BASE_ADDRESS	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define VER_MAJOR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define VER_MINOR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define VER_OEM			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define VER_BUILD		1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MV_DRIVER_NAME			"mvumi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PCI_DEVICE_ID_MARVELL_MV9143	0x9143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PCI_DEVICE_ID_MARVELL_MV9580	0x9580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MVUMI_INTERNAL_CMD_WAIT_TIME	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MVUMI_INQUIRY_LENGTH		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MVUMI_INQUIRY_UUID_OFF		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MVUMI_INQUIRY_UUID_LEN		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IS_DMA64			(sizeof(dma_addr_t) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) enum mvumi_qc_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	MV_QUEUE_COMMAND_RESULT_SENT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct mvumi_hw_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* For CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void *main_int_cause_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void *enpointa_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void *enpointb_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	void *rstoutn_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	void *ctrl_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void *rstoutn_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void *sys_soft_rst_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* For Doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	void *pciea_to_arm_drbl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void *arm_to_pciea_drbl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	void *arm_to_pciea_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	void *pciea_to_arm_msg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void *pciea_to_arm_msg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void *arm_to_pciea_msg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void *arm_to_pciea_msg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void *reset_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	void *reset_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* For Message Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	void *inb_list_basel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void *inb_list_baseh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	void *inb_aval_count_basel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	void *inb_aval_count_baseh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void *inb_write_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	void *inb_read_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void *outb_list_basel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	void *outb_list_baseh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	void *outb_copy_basel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	void *outb_copy_baseh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void *outb_copy_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void *outb_read_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	void *inb_isr_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	void *outb_isr_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	void *outb_coal_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	void *outb_coal_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* Bit setting for HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 int_comaout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 int_comaerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 int_dl_cpu2pciea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 int_mu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 int_drbl_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 int_main_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 cl_pointer_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 cl_slot_num_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 clic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 clic_in_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 clic_out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct mvumi_dyn_list_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 src_low_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 src_high_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 if_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SCSI_CMD_MARVELL_SPECIFIC	0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CDB_CORE_MODULE			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CDB_CORE_SHUTDOWN		0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	DRBL_HANDSHAKE			= 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DRBL_SOFT_RESET			= 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	DRBL_BUS_CHANGE			= 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	DRBL_EVENT_NOTIFY		= 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	DRBL_MU_RESET			= 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	DRBL_HANDSHAKE_ISR		= DRBL_HANDSHAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	* Command flag is the flag for the CDB command itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* 1-non data; 0-data command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	CMD_FLAG_NON_DATA		= 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	CMD_FLAG_DMA			= 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	CMD_FLAG_PIO			= 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* 1-host read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	CMD_FLAG_DATA_IN		= 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* 1-host write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	CMD_FLAG_DATA_OUT		= 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	CMD_FLAG_PRDT_IN_HOST		= 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define APICDB0_EVENT			0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define APICDB1_EVENT_GETEVENT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define APICDB1_HOST_GETEVENT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAX_EVENTS_RETURNED		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DEVICE_OFFLINE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DEVICE_ONLINE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mvumi_hotplug_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 dummy[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u8 bitmap[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mvumi_driver_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32	time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32	sequence_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32	event_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8	severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8	param_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u16	device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32	params[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u8	sense_data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u8	Reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u8	sense_data[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct mvumi_event_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned char	count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned char	reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct mvumi_driver_event  events[MAX_EVENTS_RETURNED];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mvumi_events_wq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct work_struct work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct mvumi_hba *mhba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned int event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	void *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HS_CAPABILITY_SUPPORT_COMPACT_SG	(1U << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HS_CAPABILITY_SUPPORT_PRD_HOST		(1U << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HS_CAPABILITY_SUPPORT_DYN_SRC		(1U << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF	(1U << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MVUMI_MAX_SG_ENTRY	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SGD_EOT			(1L << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SGD_EOT_CP		(1L << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mvumi_sgl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32	baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32	baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32	size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct mvumi_compact_sgl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32	baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32	baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GET_COMPACT_SGD_SIZE(sgd)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SET_COMPACT_SGD_SIZE(sgd, sz) do {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	(((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	(((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define sgd_getsz(_mhba, sgd, sz) do {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		(sz) = GET_COMPACT_SGD_SIZE(sgd);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		(sz) = (sgd)->size;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define sgd_setsz(_mhba, sgd, sz) do {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		SET_COMPACT_SGD_SIZE(sgd, sz);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		(sgd)->size = (sz);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define sgd_inc(_mhba, sgd) do {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mvumi_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	dma_addr_t bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	void *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned short type;	/* enum Resource_Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Resource type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum resource_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	RESOURCE_CACHED_MEMORY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	RESOURCE_UNCACHED_MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mvumi_sense_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u8 error_code:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u8 valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u8 segment_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u8 sense_key:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u8 reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u8 incorrect_length:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u8 end_of_media:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u8 file_mark:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u8 information[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	u8 additional_sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u8 command_specific_information[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u8 additional_sense_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u8 additional_sense_code_qualifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	u8 field_replaceable_unit_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u8 sense_key_specific[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Request initiator must set the status to REQ_STATUS_PENDING. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define REQ_STATUS_PENDING		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mvumi_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct list_head queue_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct mvumi_msg_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dma_addr_t frame_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct scsi_cmnd *scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	atomic_t sync_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	void *data_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	unsigned short request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unsigned char cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * the function type of the in bound frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CL_FUN_SCSI_CMD			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mvumi_msg_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u8 cmd_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u8 req_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u8 cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u8 sg_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	u32 data_transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u16 request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u8 cdb[MAX_COMMAND_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	u32 payload[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * the respond flag for data_payload of the out bound frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CL_RSP_FLAG_NODATA		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CL_RSP_FLAG_SENSEDATA		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct mvumi_rsp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	u8 req_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u8 rsp_flag;	/* Indicates the type of Data_Payload.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u16 request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	u32 payload[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct mvumi_ob_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	unsigned char data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct version_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	u32 ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u32 ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u32 ver_oem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u32 ver_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FW_MAX_DELAY			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MVUMI_FW_BUSY			(1U << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MVUMI_FW_ATTACH			(1U << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MVUMI_FW_ALLOC			(1U << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * State is the state of the MU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define FW_STATE_IDLE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define FW_STATE_STARTING		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define FW_STATE_HANDSHAKING		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define FW_STATE_STARTED		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define FW_STATE_ABORT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HANDSHAKE_SIGNATURE		0x5A5A5A5AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HANDSHAKE_READYSTATE		0x55AA5AA5L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HANDSHAKE_DONESTATE		0x55AAA55AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* HandShake Status definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HS_STATUS_OK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HS_STATUS_ERR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HS_STATUS_INVALID		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* HandShake State/Cmd definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HS_S_START			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HS_S_RESET			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HS_S_PAGE_ADDR			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define HS_S_QUERY_PAGE			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HS_S_SEND_PAGE			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HS_S_END			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HS_S_ABORT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HS_PAGE_VERIFY_SIZE		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define HS_GET_STATE(a)			(a & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define HS_GET_STATUS(a)		((a & 0xFFFF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HS_SET_STATE(a, b)		(a |= (b & 0xFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HS_SET_STATUS(a, b)		(a |= ((b & 0xFFFF) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* handshake frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct mvumi_hs_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* host information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u8 host_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u8 reserved_1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct version_info host_ver; /* bios or driver version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* controller information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	u32 system_io_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u32 slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u32 intr_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u32 intr_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* communication list configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	u32 ib_baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	u32 ib_baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u32 ob_baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	u32 ob_baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	u8 ib_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	u8 ob_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	u8 ob_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	u8 ib_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	/* system time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	u64 seconds_since1970;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct mvumi_hs_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	u8	page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	u8	checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	u16	frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	u32	frame_content[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  * the page code type of the handshake header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define HS_PAGE_FIRM_CAP	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HS_PAGE_HOST_INFO	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HS_PAGE_FIRM_CTL	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HS_PAGE_CL_INFO		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HS_PAGE_TOTAL		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define HSP_SIZE(i)	sizeof(struct mvumi_hs_page##i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HSP_MAX_SIZE ({					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	int size, m1, m2;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	m1 = max(HSP_SIZE(1), HSP_SIZE(3));		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	m2 = max(HSP_SIZE(2), HSP_SIZE(4));		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	size = max(m1, m2);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	size;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* The format of the page code for Firmware capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct mvumi_hs_page1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	u8 pagecode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	u16 frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	u16 number_of_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	u16 max_devices_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	u16 max_io_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	u16 umi_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	u32 max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct version_info fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	u8 cl_in_max_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	u8 cl_out_max_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	u8 cl_inout_list_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	u8 total_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	u16 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* The format of the page code for Host information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mvumi_hs_page2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	u8 pagecode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	u16 frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u8 host_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u8 host_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	struct version_info host_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	u32 system_io_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	u32 slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	u32 intr_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	u32 intr_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	u64 seconds_since1970;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* The format of the page code for firmware control  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct mvumi_hs_page3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	u8	pagecode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	u8	checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	u16	frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	u16	control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	u8	reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	u32	host_bufferaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	u32	host_bufferaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	u32	host_eventaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	u32	host_eventaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct mvumi_hs_page4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	u8	pagecode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	u8	checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	u16	frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	u32	ib_baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	u32	ib_baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	u32	ob_baseaddr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	u32	ob_baseaddr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	u8	ib_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	u8	ob_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	u8	ob_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	u8	ib_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct mvumi_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	unsigned short *stack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	unsigned short top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	unsigned short size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct mvumi_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	u64	wwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	u8	dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	int	id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct mvumi_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	void *base_addr[MAX_BASE_ADDRESS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	u32 pci_base[MAX_BASE_ADDRESS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	void *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	struct list_head cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	wait_queue_head_t int_cmd_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	unsigned int unique_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	atomic_t fw_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	struct mvumi_instance_template *instancet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	void *ib_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	dma_addr_t ib_list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	void *ib_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	dma_addr_t ib_frame_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	void *ob_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	dma_addr_t ob_list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	void *ib_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	dma_addr_t ib_shadow_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	void *ob_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	dma_addr_t ob_shadow_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	void *handshake_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	dma_addr_t handshake_page_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	unsigned int global_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	unsigned int isr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	unsigned short max_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	unsigned short max_target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	unsigned char *target_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	unsigned int max_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	unsigned int list_num_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	unsigned int ib_max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	unsigned int ob_max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	unsigned int ib_max_size_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	unsigned int ob_max_size_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	unsigned int max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	unsigned char hba_total_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	unsigned char fw_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	unsigned char request_id_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	unsigned char eot_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	unsigned short hba_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	unsigned short io_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	unsigned int ib_cur_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	unsigned int ob_cur_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	unsigned int fw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	struct mutex sas_discovery_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	struct list_head ob_data_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	struct list_head free_ob_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	struct list_head res_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	struct list_head waiting_req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	struct mvumi_tag tag_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	struct mvumi_cmd **tag_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	struct mvumi_hw_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	struct mutex device_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	struct list_head mhba_dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	struct list_head shost_dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	struct task_struct *dm_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	atomic_t pnp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct mvumi_instance_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	void (*enable_intr) (struct mvumi_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	void (*disable_intr) (struct mvumi_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	int (*clear_intr) (void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	unsigned int (*check_ib_list) (struct mvumi_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 			      unsigned int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	int (*reset_host) (struct mvumi_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) extern struct timezone sys_tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #endif