^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE64xx/88SE94xx main function head file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MV_SAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MV_SAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <scsi/libsas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/sas_ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "mv_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRV_NAME "mvsas"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRV_VERSION "0.8.16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MVS_ID_NOT_MAPPED 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WIDE_PORT_MAX_PHY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define mv_printk(fmt, arg ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef MV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define mv_dprintk(format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define mv_dprintk(format, arg...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV_MAX_U32 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int interrupt_coalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern struct mvs_tgt_initiator mvs_tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern struct mvs_info *tgt_mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern const struct mvs_dispatch mvs_64xx_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern const struct mvs_dispatch mvs_94xx_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define bit(n) ((u64)1 << n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define for_each_phy(__lseq_mask, __mc, __lseq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for ((__mc) = (__lseq_mask), (__lseq) = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (__mc) != 0 ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (++__lseq), (__mc) >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MVS_PHY_ID (1U << sas_phy->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UNASSOC_D2H_FIS(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ((void *) mvi->rx_fis + 0x100 * id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SATA_RECEIVED_FIS_LIST(reg_set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SATA_RECEIVED_SDB_FIS(reg_set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SATA_RECEIVED_D2H_FIS(reg_set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SATA_RECEIVED_PIO_FIS(reg_set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SATA_RECEIVED_DMA_FIS(reg_set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum dev_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MVS_DEV_NORMAL = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MVS_DEV_EH = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum dev_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MVS_SOFT_RESET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MVS_HARD_RESET = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MVS_PHY_TUNE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mvs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mvs_prv_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mvs_dispatch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int (*chip_init)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*spi_init)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*chip_ioremap)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void (*chip_iounmap)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 (*isr_status)(struct mvs_info *mvi, int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void (*interrupt_enable)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void (*interrupt_disable)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 tfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void (*start_delivery)(struct mvs_info *mvi, u32 tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 (*rx_update)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void (*int_full)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 (*prd_size)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 (*prd_count)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void (*detect_porttype)(struct mvs_info *mvi, int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int (*oob_done)(struct mvs_info *mvi, int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void (*fix_phy_info)(struct mvs_info *mvi, int i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sas_identify_frame *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void (*phy_work_around)(struct mvs_info *mvi, int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct sas_phy_linkrates *rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 (*phy_max_link_rate)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void (*clear_active_cmds)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 (*spi_read_data)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void (*spi_write_data)(struct mvs_info *mvi, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int (*spi_buildcmd)(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 *dwCmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int buf_len, int from, void *prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void (*non_spec_ncq_error)(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 reg_index, u8 reg_count, u8 *write_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mvs_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 fis_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 fis_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 srs_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 sg_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const struct mvs_dispatch *dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MVS_MAX_SG (1U << mvi->chip->sg_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MVS_RX_FISL_SZ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MVS_CHIP_DISP (mvi->chip->dispatch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct mvs_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le32 flags2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mvs_cmd_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le32 flags; /* PRD tbl len; SAS, SATA ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 lens; /* cmd, max resp frame len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le32 tags; /* targ port xfer tag; tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le32 data_len; /* data xfer len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __le64 cmd_tbl; /* command table address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __le64 open_frame; /* open addr frame address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le64 status_buf; /* status buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le64 prd_tbl; /* PRD tbl address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __le32 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mvs_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct asd_sas_port sas_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 port_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 wide_port_phymap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mvs_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct mvs_info *mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mvs_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct asd_sas_phy sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct sas_identify identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u64 dev_sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u64 att_dev_sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 att_dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 phy_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 frame_rcvd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 frame_rcvd[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 phy_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 phy_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum sas_linkrate minimum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) enum sas_linkrate maximum_linkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct mvs_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct list_head dev_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum sas_device_type dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct mvs_info *mvi_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct domain_device *sas_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 attached_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 running_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 taskfileset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 dev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Generate PHY tunning parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct phy_tuning {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* 1 bit, transmitter emphasis enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 trans_emp_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 4 bits, transmitter emphasis amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 trans_emp_amp:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* 3 bits, reserved space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 Reserved_2bit_1:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* 5 bits, transmitter amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 trans_amp:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* 2 bits, transmitter amplitude adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 trans_amp_adj:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* 1 bit, reserved space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 resv_2bit_2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* 2 bytes, reserved space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct ffe_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* 4 bits, FFE Capacitor Select (value range 0~F) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 ffe_cap_sel:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* 3 bits, FFE Resistor Select (value range 0~7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 ffe_rss_sel:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 1 bit reserve*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * The data area is valid only Signature="MRVL".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * If any member fills with 0xFF, the member is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct hba_info_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Dword 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* 4 bytes, structure signature,should be "MRVL" at first initial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Dword 1-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 reserved1[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Dword 14-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* 64 bytes, SAS address for each port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u64 sas_addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Dword 30-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* 8 bytes for vanir 8 port PHY FFE seeting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * BIT 0~3 : FFE Capacitor select(value range 0~F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * BIT 4~6 : FFE Resistor select(value range 0~7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * BIT 7: reserve.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct ffe_control ffe_ctl[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Dword 32 -43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 reserved2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Dword 44-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 phy_rate[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Dword 46-53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* 32 bytes, PHY tuning parameters for each PHY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct phy_tuning phy_tuning[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Dword 54-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 reserved3[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }; /* total 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct mvs_slot_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct sas_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void *tdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 n_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 slot_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * and PRD table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_addr_t buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void *response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mvs_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct mvs_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void *open_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct mvs_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* host-wide lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* our device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* enhanced mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* peripheral or soc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void __iomem *regs_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* SCSI/SAS glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct sas_ha_struct *sas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* TX (delivery) DMA ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) __le32 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dma_addr_t tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* cached next-producer idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 tx_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* RX (completion) DMA ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __le32 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dma_addr_t rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* RX consumer idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 rx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* RX'd FIS area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __le32 *rx_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dma_addr_t rx_fis_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* DMA command header slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct mvs_cmd_hdr *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dma_addr_t slot_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct mvs_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int tags_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long *tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* further per-slot information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct mvs_phy phy[MVS_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct mvs_port port[MVS_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 sata_reg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct list_head *hba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct list_head soc_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct list_head wq_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u16 flashid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 flashsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 flashsectSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void *addon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct hba_info_page hba_info_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct mvs_device devices[MVS_MAX_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void *bulk_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dma_addr_t bulk_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void *bulk_buffer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dma_addr_t bulk_buffer_dma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TRASH_BUCKET_SIZE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void *dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct mvs_slot_info slot_info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mvs_prv_info{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 scan_finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mvs_info *mvi[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct tasklet_struct mv_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct mvs_wq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct delayed_work work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct mvs_info *mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mvs_task_exec_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct sas_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mvs_cmd_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct mvs_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int n_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /******************** function prototype *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void mvs_get_sas_addr(void *buf, u32 buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void mvs_tag_free(struct mvs_info *mvi, u32 tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void mvs_tag_init(struct mvs_info *mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) void mvs_iounmap(void __iomem *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void *funcdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 off_hi, u64 sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void mvs_scan_start(struct Scsi_Host *shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int mvs_abort_task(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int mvs_clear_aca(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void mvs_port_formed(struct asd_sas_phy *sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) void mvs_port_deformed(struct asd_sas_phy *sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int mvs_dev_found(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void mvs_dev_gone(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int mvs_lu_reset(struct domain_device *dev, u8 *lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int mvs_I_T_nexus_reset(struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int mvs_query_task(struct sas_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void mvs_release_task(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct domain_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 reg_count, u8 *write_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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