^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE64xx/88SE94xx pci init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mv_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int interrupt_coalescing = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static struct scsi_transport_template *mvs_stt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct mvs_chip_info mvs_chips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct device_attribute *mvst_host_attrs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SOC_SAS_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct scsi_host_template mvs_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .queuecommand = sas_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .dma_need_drain = ata_scsi_dma_need_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .target_alloc = sas_target_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .slave_configure = sas_slave_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .scan_finished = mvs_scan_finished,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .scan_start = mvs_scan_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .change_queue_depth = sas_change_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .bios_param = sas_bios_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .can_queue = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .this_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .sg_tablesize = SG_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .eh_device_reset_handler = sas_eh_device_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .eh_target_reset_handler = sas_eh_target_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .slave_alloc = sas_slave_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .target_destroy = sas_target_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ioctl = sas_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .compat_ioctl = sas_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .shost_attrs = mvst_host_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .track_queue_depth = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct sas_domain_function_template mvs_transport_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .lldd_dev_found = mvs_dev_found,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .lldd_dev_gone = mvs_dev_gone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .lldd_execute_task = mvs_queue_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .lldd_control_phy = mvs_phy_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .lldd_abort_task = mvs_abort_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .lldd_abort_task_set = mvs_abort_task_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .lldd_clear_aca = mvs_clear_aca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .lldd_clear_task_set = mvs_clear_task_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .lldd_lu_reset = mvs_lu_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .lldd_query_task = mvs_query_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .lldd_port_formed = mvs_port_formed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .lldd_port_deformed = mvs_port_deformed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .lldd_write_gpio = mvs_gpio_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mvs_phy *phy = &mvi->phy[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct asd_sas_phy *sas_phy = &phy->sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) phy->mvi = mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) phy->port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) timer_setup(&phy->timer, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sas_phy->class = SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) sas_phy->iproto = SAS_PROTOCOL_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sas_phy->tproto = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sas_phy->type = PHY_TYPE_PHYSICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sas_phy->role = PHY_ROLE_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sas_phy->oob_mode = OOB_NOT_CONNECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sas_phy->id = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sas_phy->sas_addr = &mvi->sas_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sas_phy->frame_rcvd = &phy->frame_rcvd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sas_phy->lldd_phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void mvs_free(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mvs_wq *mwq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int slot_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (mvi->flags & MVF_FLAG_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) slot_nr = MVS_SOC_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) slot_nr = MVS_CHIP_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dma_pool_destroy(mvi->dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (mvi->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_free_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mvi->tx, mvi->tx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (mvi->rx_fis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mvi->rx_fis, mvi->rx_fis_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (mvi->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dma_free_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mvi->rx, mvi->rx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (mvi->slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dma_free_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) sizeof(*mvi->slot) * slot_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mvi->slot, mvi->slot_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (mvi->bulk_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mvi->bulk_buffer, mvi->bulk_buffer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (mvi->bulk_buffer1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MVS_CHIP_DISP->chip_iounmap(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (mvi->shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) scsi_host_put(mvi->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) list_for_each_entry(mwq, &mvi->wq_list, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cancel_delayed_work(&mwq->work_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) kfree(mvi->tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) kfree(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void mvs_tasklet(unsigned long opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 core_nr, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mvs_info *mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (unlikely(!mvi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < core_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MVS_CHIP_DISP->interrupt_enable(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static irqreturn_t mvs_interrupt(int irq, void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct mvs_info *mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sas_ha_struct *sha = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifndef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 core_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (unlikely(!mvi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MVS_CHIP_DISP->interrupt_disable(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) stat = MVS_CHIP_DISP->isr_status(mvi, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MVS_CHIP_DISP->interrupt_enable(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < core_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MVS_CHIP_DISP->isr(mvi, irq, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i = 0, slot_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) char pool_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (mvi->flags & MVF_FLAG_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) slot_nr = MVS_SOC_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) slot_nr = MVS_CHIP_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock_init(&mvi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mvs_phy_init(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mvi->port[i].wide_port_phymap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mvi->port[i].port_attached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) INIT_LIST_HEAD(&mvi->port[i].list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < MVS_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mvi->devices[i].dev_type = SAS_PHY_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mvi->devices[i].device_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mvi->devices[i].dev_status = MVS_DEV_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * alloc and init our DMA areas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mvi->tx = dma_alloc_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &mvi->tx_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!mvi->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &mvi->rx_fis_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!mvi->rx_fis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mvi->rx = dma_alloc_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) &mvi->rx_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!mvi->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mvi->rx[0] = cpu_to_le32(0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mvi->rx_cons = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mvi->slot = dma_alloc_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sizeof(*mvi->slot) * slot_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) &mvi->slot_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!mvi->slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) TRASH_BUCKET_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) &mvi->bulk_buffer_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!mvi->bulk_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TRASH_BUCKET_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) &mvi->bulk_buffer_dma1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!mvi->bulk_buffer1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MVS_SLOT_BUF_SZ, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!mvi->dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mvi->tags_num = slot_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Initialize tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mvs_tag_init(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long res_start, res_len, res_flag_ex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct pci_dev *pdev = mvi->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (bar_ex != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * ioremap main and peripheral registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) res_start = pci_resource_start(pdev, bar_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) res_len = pci_resource_len(pdev, bar_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!res_start || !res_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) res_flag_ex = pci_resource_flags(pdev, bar_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (res_flag_ex & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mvi->regs_ex = ioremap(res_start, res_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mvi->regs_ex = (void *)res_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!mvi->regs_ex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) res_start = pci_resource_start(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) res_len = pci_resource_len(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!res_start || !res_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) iounmap(mvi->regs_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mvi->regs_ex = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mvi->regs = ioremap(res_start, res_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!mvi->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) iounmap(mvi->regs_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mvi->regs_ex = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void mvs_iounmap(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const struct pci_device_id *ent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct Scsi_Host *shost, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mvs_info *mvi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mvi = kzalloc(sizeof(*mvi) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (1L << mvs_chips[ent->driver_data].slot_width) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sizeof(struct mvs_slot_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mvi->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mvi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mvi->chip_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mvi->chip = &mvs_chips[mvi->chip_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) INIT_LIST_HEAD(&mvi->wq_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mvi->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mvi->sas = sha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mvi->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!mvi->tags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (MVS_CHIP_DISP->chip_ioremap(mvi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!mvs_alloc(mvi, shost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mvs_free(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int pci_go_64(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_printk(KERN_ERR, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "32-bit DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const struct mvs_chip_info *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int phy_nr, port_nr; unsigned short core_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct asd_sas_phy **arr_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct asd_sas_port **arr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) core_nr = chip_info->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) phy_nr = core_nr * chip_info->n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) port_nr = phy_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) memset(sha, 0x00, sizeof(struct sas_ha_struct));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!arr_phy || !arr_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sha->sas_phy = arr_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sha->sas_port = arr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sha->core.shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!sha->lldd_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) shost->transportt = mvs_stt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) shost->max_id = MVS_MAX_DEVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) shost->max_lun = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) shost->max_channel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) shost->max_cmd_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) exit_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) kfree(arr_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) kfree(arr_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct mvs_chip_info *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int can_queue, i = 0, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct mvs_info *mvi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (j = 0; j < nr_core; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < chip_info->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sha->sas_phy[j * chip_info->n_phy + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &mvi->phy[i].sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sha->sas_port[j * chip_info->n_phy + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &mvi->port[i].sas_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sha->sas_ha_name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sha->dev = mvi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sha->lldd_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sha->sas_addr = &mvi->sas_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sha->num_phys = nr_core * chip_info->n_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (mvi->flags & MVF_FLAG_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) can_queue = MVS_SOC_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) can_queue = MVS_CHIP_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) shost->can_queue = can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sha->core.shost = mvi->shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void mvs_init_sas_add(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mvi->phy[i].dev_sas_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int rc, nhost = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct mvs_info *mvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct mvs_prv_info *mpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) irq_handler_t irq_handler = mvs_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct Scsi_Host *shost = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct mvs_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "mvsas: driver version %s\n", DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto err_out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rc = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rc = pci_go_64(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!shost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) chip = &mvs_chips[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SHOST_TO_SAS_HA(shost) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!SHOST_TO_SAS_HA(shost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) rc = mvs_prep_sas_ha_init(shost, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!mvi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) memset(&mvi->hba_info_param, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sizeof(struct hba_info_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mvs_init_sas_add(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mvi->instance = nhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rc = MVS_CHIP_DISP->chip_init(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mvs_free(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto err_out_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) nhost++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } while (nhost < chip->n_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) (unsigned long)SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mvs_post_sas_ha_init(shost, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rc = scsi_add_host(shost, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err_out_shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto err_out_shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DRV_NAME, SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err_not_sas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MVS_CHIP_DISP->interrupt_enable(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) scsi_scan_host(mvi->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err_not_sas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sas_unregister_ha(SHOST_TO_SAS_HA(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) err_out_shost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) scsi_remove_host(mvi->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err_out_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err_out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) err_out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void mvs_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned short core_nr, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct sas_ha_struct *sha = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct mvs_info *mvi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef CONFIG_SCSI_MVSAS_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sas_unregister_ha(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sas_remove_host(mvi->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MVS_CHIP_DISP->interrupt_disable(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) free_irq(mvi->pdev->irq, sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (i = 0; i < core_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mvs_free(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kfree(sha->sas_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) kfree(sha->sas_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) kfree(sha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct pci_device_id mvs_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .vendor = PCI_VENDOR_ID_MARVELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .device = 0x6440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .subdevice = 0x6480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .driver_data = chip_6485,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .vendor = PCI_VENDOR_ID_MARVELL_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .device = 0x9480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .subdevice = 0x9480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .driver_data = chip_9480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .vendor = PCI_VENDOR_ID_MARVELL_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .device = 0x9445,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .subdevice = 0x9480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .driver_data = chip_9445,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct pci_driver mvs_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .id_table = mvs_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .probe = mvs_pci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .remove = mvs_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mvs_show_driver_version(struct device *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct device_attribute *attr, char *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static DEVICE_ATTR(driver_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mvs_show_driver_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mvs_store_interrupt_coalescing(struct device *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) const char *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct mvs_info *mvi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct Scsi_Host *shost = class_to_shost(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 i, core_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (buffer == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (sscanf(buffer, "%u", &val) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (val >= 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mv_dprintk("interrupt coalescing timer %d us is"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "too long\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return strlen(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) interrupt_coalescing = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (unlikely(!mvi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) for (i = 0; i < core_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (MVS_CHIP_DISP->tune_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MVS_CHIP_DISP->tune_interrupt(mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) interrupt_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mv_dprintk("set interrupt coalescing time to %d us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) interrupt_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return strlen(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct device_attribute *attr, char *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static DEVICE_ATTR(interrupt_coalescing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mvs_show_interrupt_coalescing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mvs_store_interrupt_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int __init mvs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!mvs_stt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rc = pci_register_driver(&mvs_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) sas_release_transport(mvs_stt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static void __exit mvs_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pci_unregister_driver(&mvs_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) sas_release_transport(mvs_stt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct device_attribute *mvst_host_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) &dev_attr_driver_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &dev_attr_interrupt_coalescing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) module_init(mvs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) module_exit(mvs_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MODULE_DEVICE_TABLE(pci, mvs_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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