^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE64xx/88SE94xx const head file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MV_DEFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MV_DEFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCI_DEVICE_ID_ARECA_1300 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCI_DEVICE_ID_ARECA_1320 0x1320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum chip_flavors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) chip_6320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) chip_6440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) chip_6485,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) chip_9480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) chip_9180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) chip_9445,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) chip_9485,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) chip_1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) chip_1320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* driver compile-time configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum driver_configuration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* software requires power-of-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MVS_SOC_SLOTS = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MVS_OAF_SZ = 64, /* Open address frame buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MVS_QUEUE_SIZE = 64, /* Support Queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* unchangeable hardware details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum hardware_details {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MVS_MAX_PHYS = 8, /* max. possible phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MVS_MAX_PORTS = 8, /* max. possible ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MVS_SOC_PHYS = 4, /* soc phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MVS_SOC_PORTS = 4, /* soc phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MVS_MAX_DEVICES = 1024, /* max supported device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* peripheral registers (BAR2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum peripheral_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SPI_CTL = 0x10, /* EEPROM control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SPI_CMD = 0x14, /* EEPROM command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SPI_DATA = 0x18, /* EEPROM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum peripheral_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TWSI_RDY = (1U << 7), /* EEPROM interface ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TWSI_RD = (1U << 4), /* EEPROM read access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum hw_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* MVS_GBL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) INT_EN = (1U << 1), /* Global int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HBA_RST = (1U << 0), /* HBA reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* MVS_GBL_INT_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) INT_XOR = (1U << 4), /* XOR engine event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SATA_TARGET = (1U << 16), /* port0 SATA target enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODE_AUTO_DET_PORT6 = (1U << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODE_AUTO_DET_PORT5 = (1U << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODE_AUTO_DET_PORT4 = (1U << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODE_AUTO_DET_PORT3 = (1U << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODE_AUTO_DET_PORT2 = (1U << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODE_AUTO_DET_PORT1 = (1U << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODE_AUTO_DET_PORT0 = (1U << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODE_SAS_PORT6_MASK = (1U << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODE_SAS_PORT5_MASK = (1U << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MODE_SAS_PORT4_MASK = (1U << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODE_SAS_PORT3_MASK = (1U << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODE_SAS_PORT2_MASK = (1U << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MODE_SAS_PORT1_MASK = (1U << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODE_SAS_PORT0_MASK = (1U << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* SAS_MODE value may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * dictated (in hw) by values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * of SATA_TARGET & AUTO_DET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* MVS_TX_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TX_EN = (1U << 16), /* Enable TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* MVS_RX_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RX_EN = (1U << 16), /* Enable RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* MVS_INT_COAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) COAL_EN = (1U << 16), /* Enable int coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* MVS_INT_STAT, MVS_INT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CINT_I2C = (1U << 31), /* I2C event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CINT_SW0 = (1U << 30), /* software event 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CINT_SW1 = (1U << 29), /* software event 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CINT_MEM = (1U << 26), /* int mem parity err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CINT_NON_SPEC_NCQ_ERROR = (1U << 25), /* Non specific NCQ error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CINT_SRS = (1U << 3), /* SRS event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CINT_DONE = (1U << 0), /* cmd completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* shl for ports 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CINT_PORT = (1U << 8), /* port0 event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CINT_PORT_MASK_OFFSET = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CINT_PHY_MASK_OFFSET = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* TX (delivery) ring bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) TXQ_CMD_SHIFT = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) TXQ_CMD_SSP = 1, /* SSP protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TXQ_CMD_SMP = 2, /* SMP protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TXQ_CMD_STP = 3, /* STP/SATA protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP target free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TXQ_MODE_TARGET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) TXQ_MODE_INITIATOR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) TXQ_PRI_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TXQ_PRI_HIGH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TXQ_SRS_SHIFT = 20, /* SATA register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TXQ_SRS_MASK = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TXQ_PHY_SHIFT = 12, /* PHY bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TXQ_PHY_MASK = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TXQ_SLOT_MASK = 0xfff, /* slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* RX (completion) ring bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) RXQ_GOOD = (1U << 23), /* Response good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RXQ_CMD_RX = (1U << 20), /* target cmd received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RXQ_ATTN = (1U << 19), /* attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RXQ_RSP = (1U << 18), /* response frame xfer'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RXQ_ERR = (1U << 17), /* err info rec xfer'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) RXQ_DONE = (1U << 16), /* cmd complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RXQ_SLOT_MASK = 0xfff, /* slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* mvs_cmd_hdr bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* SSP initiator only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* SSP initiator or target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MCH_SSP_FR_TASK = 0x1, /* TASK frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* SSP target only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MCH_SSP_MODE_PASSTHRU = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MCH_SSP_MODE_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MCH_FBURST = (1U << 11), /* first burst (SSP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CCTL_RST = (1U << 5), /* port logic reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* 0(LSB first), 1(MSB first) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CCTL_ENDIAN_CMD = (1U << 0), /* command table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* MVS_Px_SER_CTLSTAT (per-phy control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PHY_RST = (1U << 0), /* phy reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PHY_READY_MASK = (1U << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PHYEV_AN = (1U << 18), /* SATA async notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PHYEV_IU_BIG = (1U << 11), /* IU too long err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PHYEV_PORT_SEL = (1U << 6), /* port selector present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PHYEV_ID_FAIL = (1U << 3), /* identify failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PHYEV_ID_DONE = (1U << 2), /* identify done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* MVS_PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6485 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PCS_CMD_RST = (1U << 1), /* reset cmd issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PCS_CMD_EN = (1U << 0), /* enable cmd issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Port n Attached Device Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PORT_DEV_SSP_TRGT = (1U << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PORT_DEV_SMP_TRGT = (1U << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PORT_DEV_STP_TRGT = (1U << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PORT_DEV_SSP_INIT = (1U << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PORT_DEV_SMP_INIT = (1U << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PORT_DEV_STP_INIT = (1U << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PORT_PHY_ID_MASK = (0xFFU << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PORT_SSP_TRGT_MASK = (0x1U << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PORT_SSP_INIT_MASK = (0x1U << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PORT_DEV_TRGT_MASK = (0x7U << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PORT_DEV_INIT_MASK = (0x7U << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PORT_DEV_TYPE_MASK = (0x7U << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Port n PHY Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PHY_RDY = (1U << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PHY_DW_SYNC = (1U << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PHY_OOB_DTCTD = (1U << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* VSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* PHYMODE 6 (CDB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* SAS/SATA configuration port registers, aka phy registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) enum sas_sata_config_port_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PHYR_SATA_CTL = 0x18, /* SATA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PHYR_PHY_STAT = 0x1C, /* PHY status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PHYR_WIDE_PORT = 0x38, /* wide port participating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PHYR_CURRENT0 = 0x80, /* current connection info 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PHYR_CURRENT1 = 0x84, /* current connection info 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PHYR_CURRENT2 = 0x88, /* current connection info 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CONFIG_ID_FRAME0 = 0x100, /* Port device ID frame register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CONFIG_ID_FRAME1 = 0x104, /* Port device ID frame register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CONFIG_ID_FRAME2 = 0x108, /* Port device ID frame register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CONFIG_ID_FRAME3 = 0x10c, /* Port device ID frame register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CONFIG_ID_FRAME4 = 0x110, /* Port device ID frame register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CONFIG_ID_FRAME5 = 0x114, /* Port device ID frame register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CONFIG_ID_FRAME6 = 0x118, /* Port device ID frame register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CONFIG_ATT_ID_FRAME0 = 0x11c, /* attached ID frame register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) CONFIG_ATT_ID_FRAME1 = 0x120, /* attached ID frame register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CONFIG_ATT_ID_FRAME2 = 0x124, /* attached ID frame register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CONFIG_ATT_ID_FRAME3 = 0x128, /* attached ID frame register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CONFIG_ATT_ID_FRAME4 = 0x12c, /* attached ID frame register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CONFIG_ATT_ID_FRAME5 = 0x130, /* attached ID frame register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CONFIG_ATT_ID_FRAME6 = 0x134, /* attached ID frame register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum sas_cmd_port_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CMD_OOB_SPACE = 0x110, /* OOB space control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CMD_OOB_BURST = 0x114, /* OOB burst control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CMD_PHY_TIMER = 0x118, /* PHY timer control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CMD_ID_TEST = 0x134, /* ID test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CMD_PL_TIMER = 0x138, /* PL timer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CMD_WD_TIMER = 0x13c, /* WD timer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) CMD_RESET_COUNT = 0x188, /* Reset Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) CMD_PHY_CTL = 0x194, /* PHY Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CMD_HOST_CTL = 0x1AC, /* Host Control Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CMD_PORT_LAYER_TIMER1 = 0x1E0, /* Port Layer Timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CMD_LINK_TIMER = 0x1E4, /* Link Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) enum mvs_info_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum mvs_event_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PHY_PLUG_EVENT = (3U),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PHY_PLUG_IN = (1U << 0), /* phy plug in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PHY_PLUG_OUT = (1U << 1), /* phy plug out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EXP_BRCT_CHG = (1U << 2), /* broadcast change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum mvs_port_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PORT_TGT_MASK = (1U << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PORT_INIT_PORT = (1U << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PORT_TGT_PORT = (1U << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PORT_TYPE_SAS = (1U << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PORT_TYPE_SATA = (1U << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Command Table Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) enum ct_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SSP_F_H = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SSP_F_IU = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SSP_F_MAX = 0x4D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* STP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) STP_CMD_FIS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) STP_ATAPI_CMD = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) STP_F_MAX = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SMP_F_T = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SMP_F_DEP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SMP_F_MAX = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum status_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SB_EIR_OFF = 0x00, /* Error Information Record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SB_RFB_OFF = 0x08, /* Response Frame Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SB_RFB_MAX = 0x400, /* RFB size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) enum error_info_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RSP_OVER = (1U << 29), /* rsp buffer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) UNK_FIS = (1U << 27), /* unknown FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) R_ERR = (1U << 23), /* SATA returned R_ERR prim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) INTERLOCK = (1U << 15), /* interlock error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) NAK = (1U << 14), /* NAK rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) STP_RES_BSY = (1U << 8), /* STP resources busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BREAK = (1U << 7), /* break received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BAD_DEST = (1U << 6), /* bad destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BAD_PROTO = (1U << 5), /* protocol not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BAD_RATE = (1U << 4), /* cxn rate not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) WRONG_DEST = (1U << 3), /* wrong destination error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CREDIT_TO = (1U << 2), /* credit timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) WDOG_TO = (1U << 1), /* watchdog timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BUF_PAR = (1U << 0), /* buffer parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) enum error_info_rec_2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) APP_CHK_ERR = (1U << 13), /* Application Check error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) REF_CHK_ERR = (1U << 12), /* Reference Check Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) USR_BLK_NM = (1U << 0), /* User Block Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) enum pci_cfg_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PCTL_PWR_OFF = (0xFU << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PCTL_COM_ON = (0xFU << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PCTL_LINK_RST = (0xFU << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PCTL_LINK_OFFS = (16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PCTL_PHY_DSBL = (0xFU << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PCTL_PHY_DSBL_OFFS = (12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PRD_REQ_SIZE = (0x4000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PRD_REQ_MASK = (0x00007000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PLS_NEG_LINK_WD = (0x3FU << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PLS_NEG_LINK_WD_OFFS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PLS_LINK_SPD = (0x0FU << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PLS_LINK_SPD_OFFS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) enum open_frame_protocol {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PROTOCOL_SMP = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PROTOCOL_SSP = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PROTOCOL_STP = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* define for response frame datapres field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) enum datapres_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) NO_DATA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RESPONSE_DATA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SENSE_DATA = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* define task management IU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mvs_tmf_task{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 tmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 tag_of_task_to_be_managed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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