Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell 88SE64xx/88SE94xx register IO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _MV_CHIPS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _MV_CHIPS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define mr32(reg)	readl(regs + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define mw32(reg, val)	writel((val), regs + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define mw32_f(reg, val)	do {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 				mw32(reg, val);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 				mr32(reg);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 			} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define iow32(reg, val) 	outl(val, (unsigned long)(regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ior32(reg) 		inl((unsigned long)(regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define iow16(reg, val) 	outw((unsigned long)(val, regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ior16(reg) 		inw((unsigned long)(regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define iow8(reg, val) 		outb((unsigned long)(val, regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ior8(reg) 		inb((unsigned long)(regs + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	mw32(MVS_CMD_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	return mr32(MVS_CMD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	mw32(MVS_CMD_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	mw32(MVS_CMD_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (port < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				u32 off2, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	void __iomem *regs = mvi->regs + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem *regs2 = mvi->regs + off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return (port < 4) ? readl(regs + port * 8) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		readl(regs2 + (port - 4) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	void __iomem *regs = mvi->regs + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	void __iomem *regs2 = mvi->regs + off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (port < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		writel(val, regs + port * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		writel(val, regs2 + (port - 4) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return mvs_read_port(mvi, MVS_P0_CFG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			MVS_P4_CFG_DATA, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 						u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mvs_write_port(mvi, MVS_P0_CFG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			MVS_P4_CFG_DATA, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 						u32 port, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mvs_write_port(mvi, MVS_P0_CFG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			MVS_P4_CFG_ADDR, port, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return mvs_read_port(mvi, MVS_P0_VSR_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			MVS_P4_VSR_DATA, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mvs_write_port(mvi, MVS_P0_VSR_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			MVS_P4_VSR_DATA, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 						u32 port, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mvs_write_port(mvi, MVS_P0_VSR_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			MVS_P4_VSR_ADDR, port, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return mvs_read_port(mvi, MVS_P0_INT_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			MVS_P4_INT_STAT, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mvs_write_port(mvi, MVS_P0_INT_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			MVS_P4_INT_STAT, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return mvs_read_port(mvi, MVS_P0_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			MVS_P4_INT_MASK, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 						u32 port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mvs_write_port(mvi, MVS_P0_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			MVS_P4_INT_MASK, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline void mvs_phy_hacks(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	tmp &= ~(1 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tmp |= (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* enable retry 127 times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* extend open frame timeout to max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tmp &= ~0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	tmp |= 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* not to halt for different port op during wideport link change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline void mvs_int_sata(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tmp = mr32(MVS_INT_STAT_SRS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		mw32(MVS_INT_STAT_SRS_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	MVS_CHIP_DISP->clear_active_cmds(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void mvs_int_full(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 tmp, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	stat = mr32(MVS_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mvs_int_rx(mvi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			mvs_int_port(mvi, i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (stat & CINT_NON_SPEC_NCQ_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		MVS_CHIP_DISP->non_spec_ncq_error(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (stat & CINT_SRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		mvs_int_sata(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mw32(MVS_INT_STAT, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mw32(MVS_TX_PROD_IDX, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline u32 mvs_rx_update(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return mr32(MVS_RX_CONS_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline u32 mvs_get_prd_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return sizeof(struct mvs_prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline u32 mvs_get_prd_count(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return MAX_SG_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u16 link_stat, link_spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	const char *spd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		"UnKnown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		"2.5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		"5.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (link_spd >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		link_spd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dev_printk(KERN_INFO, mvi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	       (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	       spd[link_spd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline u32 mvs_hw_max_link_rate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return MAX_LINK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif  /* _MV_CHIPS_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)