^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE94xx hardware specific head file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MVS94XX_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MVS94XX_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum VANIR_REVISION_ID {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) VANIR_A0_REV = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) VANIR_B0_REV = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) VANIR_C0_REV = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) VANIR_C1_REV = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) VANIR_C2_REV = 0xC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum host_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MVS_HST_CHIP_CONFIG = 0x10104, /* chip configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum hw_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MVS_GBL_CTL = 0x04, /* global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MVS_GBL_INT_STAT = 0x00, /* global irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MVS_PHY_CTL = 0x40, /* SOC PHY Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MVS_GBL_PORT_TYPE = 0xa0, /* port type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MVS_CTL = 0x100, /* SAS/SATA port configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MVS_PCS = 0x104, /* SAS/SATA port control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MVS_CMD_LIST_HI = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MVS_RX_FIS_HI = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MVS_STP_REG_SET_1 = 0x11C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MVS_TX_CFG = 0x120, /* TX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MVS_TX_HI = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MVS_RX_CFG = 0x134, /* RX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MVS_RX_LO = 0x138, /* RX (completion) ring addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MVS_RX_HI = 0x13C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MVS_INT_COAL = 0x148, /* Int coalescing config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MVS_INT_STAT = 0x150, /* Central int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MVS_INT_MASK = 0x154, /* Central int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MVS_INT_MASK_SRS_0 = 0x15C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MVS_INT_STAT_SRS_1 = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MVS_INT_MASK_SRS_1 = 0x164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MVS_NON_NCQ_ERR_1 = 0x16C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MVS_CMD_ADDR = 0x170, /* Command register port (addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MVS_CMD_DATA = 0x174, /* Command register port (data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MVS_MEM_PARITY_ERR = 0x178, /* Memory parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MVS_P0_INT_STAT = 0x180, /* port0 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MVS_P0_INT_MASK = 0x184, /* port0 interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MVS_P4_INT_STAT = 0x1A0, /* Port4 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MVS_P0_SER_CTLSTAT = 0x1D0, /* port0 serial control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MVS_P4_SER_CTLSTAT = 0x1E0, /* port4 serial control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MVS_P0_CFG_ADDR = 0x200, /* port0 phy register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MVS_P0_CFG_DATA = 0x204, /* port0 phy register data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MVS_P4_CFG_ADDR = 0x220, /* Port4 config address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MVS_P4_CFG_DATA = 0x224, /* Port4 config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* phys 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MVS_P0_VSR_ADDR = 0x250, /* phy0 VSR address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* phys 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* multiplexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MVS_COMMAND_ACTIVE = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum pci_cfg_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PCR_PHY_CTL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PCR_PHY_CTL2 = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PCR_DEV_CTRL = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PCR_LINK_STAT = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* SAS/SATA Vendor Specific Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum sas_sata_vsp_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) VSR_PHY_STAT = 0x00 * 4, /* Phy Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) VSR_PHY_MODE2 = 0x02 * 4, /* Phy Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) VSR_PHY_MODE3 = 0x03 * 4, /* Phy Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) VSR_PHY_MODE4 = 0x04 * 4, /* Phy Counter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) VSR_PHY_MODE6 = 0x06 * 4, /* Event Counter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) VSR_PHY_MODE7 = 0x07 * 4, /* Event Counter Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) VSR_PHY_MODE8 = 0x08 * 4, /* Event Counter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) VSR_PHY_ACT_LED = 0x0C * 4, /* Activity LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) VSR_PHY_FFE_CONTROL = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) VSR_PHY_DFE_UPDATE_CRTL = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) VSR_REF_CLOCK_CRTL = 0x1A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum chip_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum pci_interrupt_cause {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* MAIN_IRQ_CAUSE (R10200) Bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MVS_IRQ_PCIF_DRBL0 = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MVS_IRQ_PCIF_DRBL1 = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MVS_IRQ_PCIF_DRBL2 = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MVS_IRQ_PCIF_DRBL3 = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MVS_IRQ_XOR_A = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MVS_IRQ_XOR_B = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MVS_IRQ_SAS_A = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MVS_IRQ_SAS_B = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MVS_IRQ_CPU_CNTRL = (1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MVS_IRQ_GPIO = (1 << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MVS_IRQ_UART = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MVS_IRQ_SPI = (1 << 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MVS_IRQ_I2C = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MVS_IRQ_SGPIO = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MVS_IRQ_COM_ERR = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MVS_IRQ_I2O_ERR = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MVS_IRQ_PCIE_ERR = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) union reg_phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 phy_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 sas_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 sata_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 sata_host_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * bit 2: 6Gbps support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * bit 1: 3Gbps support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * bit 0: 1.5Gbps support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 speed_support:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 snw_3_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 tx_lnk_parity:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * bit 5: G1 (1.5Gbps) Without SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * bit 4: G1 (1.5Gbps) with SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * bit 3: G2 (3.0Gbps) Without SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * bit 2: G2 (3.0Gbps) with SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * bit 1: G3 (6.0Gbps) without SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * bit 0: G3 (6.0Gbps) with SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 tx_spt_phs_lnk_rate:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 tx_lgcl_lnk_rate:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 tx_ssc_type:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 sata_spin_up_spt:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 sata_spin_up_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 bypass_oob:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 disable_phy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MAX_SG_ENTRY 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct mvs_prd_imt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifndef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __le32 len:22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 _r_a:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 misc_ctl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 inter_sel:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 inter_sel:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 misc_ctl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 _r_a:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 len:22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mvs_prd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* 64-bit buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 22-bit length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __le32 im_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) enum sgpio_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MVS_SGPIO_HOST_OFFSET = 0x100, /* offset between hosts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MVS_SGPIO_CFG0 = 0xc200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MVS_SGPIO_CFG0_ENABLE = (1 << 0), /* enable pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MVS_SGPIO_CFG0_BLINKB = (1 << 1), /* blink generators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MVS_SGPIO_CFG0_BLINKA = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MVS_SGPIO_CFG0_INVSCLK = (1 << 3), /* invert signal? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MVS_SGPIO_CFG0_INVSLOAD = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MVS_SGPIO_CFG0_INVSDOUT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6), /* rise/fall edge? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MVS_SGPIO_CFG0_MAN_BITLEN_SHIFT = 18, /* bits/frame manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT = 24, /* bits/frame auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MVS_SGPIO_CFG1 = 0xc204, /* blink timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MVS_SGPIO_CFG1_LOWA_SHIFT = 0, /* A off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MVS_SGPIO_CFG1_HIA_SHIFT = 4, /* A on time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MVS_SGPIO_CFG1_LOWB_SHIFT = 8, /* B off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MVS_SGPIO_CFG1_HIB_SHIFT = 12, /* B on time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MVS_SGPIO_CFG1_MAXACTON_SHIFT = 16, /* max activity on time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* force activity off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* stretch activity on time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MVS_SGPIO_CFG1_STRCHACTON_SHIFT = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* stretch activiity off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MVS_SGPIO_CFG1_STRCHACTOFF_SHIFT = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MVS_SGPIO_CFG2 = 0xc208, /* clock speed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MVS_SGPIO_CFG2_CLK_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MVS_SGPIO_CFG2_BLINK_SHIFT = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MVS_SGPIO_CTRL = 0xc20c, /* SDOUT/SDIN mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MVS_SGPIO_CTRL_SDOUT_AUTO = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MVS_SGPIO_CTRL_SDOUT_SHIFT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MVS_SGPIO_DSRC = 0xc220, /* map ODn bits to drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MVS_SGPIO_DCTRL = 0xc238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MVS_SGPIO_DCTRL_ERR_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MVS_SGPIO_DCTRL_LOC_SHIFT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MVS_SGPIO_DCTRL_ACT_SHIFT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) enum sgpio_led_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LED_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LED_ON = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LED_BLINKA = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LED_BLINKA_INV = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LED_BLINKA_SOF = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LED_BLINKA_EOF = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LED_BLINKB = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LED_BLINKB_INV = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DEFAULT_SGPIO_BITS ((LED_BLINKA_SOF << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (LED_BLINKA_SOF << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (LED_BLINKA_SOF << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (LED_BLINKA_SOF << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * these registers are accessed through port vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * specific address/data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) enum sas_sata_phy_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GENERATION_1_SETTING = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) GENERATION_1_2_SETTING = 0x11C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GENERATION_2_3_SETTING = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GENERATION_3_4_SETTING = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SPI_CTRL_REG_94XX 0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SPI_ADDR_REG_94XX 0xc804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SPI_WR_DATA_REG_94XX 0xc808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SPI_RD_DATA_REG_94XX 0xc80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SPI_CTRL_READ_94XX (1U << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SPI_ADDR_VLD_94XX (1U << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SPI_CTRL_SpiStart_94XX (1U << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mv_ffc64(u64 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u64 x = ~v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return x ? __ffs64(x) : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define r_reg_set_enable(i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mr32(MVS_STP_REG_SET_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define w_reg_set_enable(i, tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mw32(MVS_STP_REG_SET_0, tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) extern const struct mvs_dispatch mvs_94xx_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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