^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE64xx hardware specific head file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MVS64XX_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MVS64XX_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* enhanced mode registers (BAR4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum hw_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MVS_GBL_CTL = 0x04, /* global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MVS_GBL_INT_STAT = 0x08, /* global irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MVS_PHY_CTL = 0x40, /* SOC PHY Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MVS_GBL_PORT_TYPE = 0xa0, /* port type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MVS_CTL = 0x100, /* SAS/SATA port configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MVS_PCS = 0x104, /* SAS/SATA port control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MVS_CMD_LIST_HI = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MVS_RX_FIS_HI = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MVS_TX_CFG = 0x120, /* TX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MVS_TX_HI = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MVS_RX_CFG = 0x134, /* RX configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MVS_RX_LO = 0x138, /* RX (completion) ring addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MVS_RX_HI = 0x13C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MVS_INT_COAL = 0x148, /* Int coalescing config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MVS_INT_STAT = 0x150, /* Central int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MVS_INT_MASK = 0x154, /* Central int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MVS_INT_MASK_SRS_0 = 0x15C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MVS_P4_CFG_DATA = 0x234, /* Port4 config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ports 1-3 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* ports 5-7 follow after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum pci_cfg_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PCR_PHY_CTL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PCR_PHY_CTL2 = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PCR_DEV_CTRL = 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PCR_LINK_STAT = 0xF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* SAS/SATA Vendor Specific Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum sas_sata_vsp_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) VSR_PHY_STAT = 0x00, /* Phy Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) VSR_PHY_MODE1 = 0x01, /* phy tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VSR_PHY_MODE2 = 0x02, /* tx scc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) VSR_PHY_MODE3 = 0x03, /* pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) VSR_PHY_MODE4 = 0x04, /* VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) VSR_PHY_MODE5 = 0x05, /* Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VSR_PHY_MODE6 = 0x06, /* CDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) VSR_PHY_MODE7 = 0x07, /* Impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) VSR_PHY_MODE8 = 0x08, /* Voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) VSR_PHY_MODE9 = 0x09, /* Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) VSR_PHY_MODE10 = 0x0A, /* Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum chip_register_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MAX_SG_ENTRY 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mvs_prd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __le64 addr; /* 64-bit buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __le32 len; /* 16-bit length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPI_CTRL_REG 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPI_CTRL_VENDOR_ENABLE (1U<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPI_CTRL_SPIRDY (1U<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPI_CTRL_SPISTART (1U<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SPI_CMD_REG 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SPI_DATA_REG 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPI_CTRL_REG_64XX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SPI_CMD_REG_64XX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SPI_DATA_REG_64XX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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