^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88SE64xx hardware specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Marvell. <kewei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mv_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mv_64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mv_chips.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct mvs_phy *phy = &mvi->phy[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = mr32(MVS_GBL_PORT_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (reg & MODE_SAS_SATA & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) phy->phy_type |= PORT_TYPE_SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) phy->phy_type |= PORT_TYPE_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) tmp = mr32(MVS_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (mvi->chip->n_phy <= MVS_SOC_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mw32(MVS_PCS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void mvs_64xx_phy_hacks(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mvs_phy_hacks(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) for (i = 0; i < MVS_SOC_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mvs_write_port_vsr_data(mvi, i, 0x2F0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* disable auto port detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mw32(MVS_GBL_PORT_TYPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mvs_write_port_vsr_data(mvi, i, 0x90000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mvs_write_port_vsr_data(mvi, i, 0x50f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mvs_write_port_vsr_data(mvi, i, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 reg, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (phy_id < MVS_SOC_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = mr32(MVS_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (phy_id < MVS_SOC_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (phy_id < MVS_SOC_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mw32(MVS_PHY_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tmp = mvs_read_port_irq_stat(mvi, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tmp &= ~PHYEV_RDY_CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mvs_write_port_irq_stat(mvi, phy_id, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tmp = mvs_read_phy_ctl(mvi, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (hard == MVS_HARD_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tmp |= PHY_RST_HARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else if (hard == MVS_SOFT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp |= PHY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mvs_write_phy_ctl(mvi, phy_id, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (hard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tmp = mvs_read_phy_ctl(mvi, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } while (tmp & PHY_RST_HARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (clear_all) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmp = mr32(MVS_INT_STAT_SRS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mw32(MVS_INT_STAT_SRS_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tmp = mr32(MVS_INT_STAT_SRS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (tmp & (1 << (reg_set % 32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) printk(KERN_DEBUG "register set 0x%x was stopped.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int mvs_64xx_chip_reset(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* make sure interrupts are masked immediately (paranoia) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mw32(MVS_GBL_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tmp = mr32(MVS_GBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Reset Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!(tmp & HBA_RST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (mvi->flags & MVF_PHY_PWR_FIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp &= ~PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tmp |= PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tmp &= ~PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tmp |= PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* make sure interrupts are masked immediately (paranoia) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mw32(MVS_GBL_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tmp = mr32(MVS_GBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Reset Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!(tmp & HBA_RST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mw32_f(MVS_GBL_CTL, HBA_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* wait for reset to finish; timeout is just a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) i = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (i-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!(mr32(MVS_GBL_CTL) & HBA_RST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (mr32(MVS_GBL_CTL) & HBA_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (phy_id < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) offs = PCR_PHY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) offs = PCR_PHY_CTL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) phy_id -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_read_config_dword(mvi->pdev, offs, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_write_config_dword(mvi->pdev, offs, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tmp = mr32(MVS_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (phy_id < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) offs = PCR_PHY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) offs = PCR_PHY_CTL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) phy_id -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_read_config_dword(mvi->pdev, offs, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_write_config_dword(mvi->pdev, offs, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tmp = mr32(MVS_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int mvs_64xx_init(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 tmp, cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (mvi->pdev && mvi->pdev->revision == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mvi->flags |= MVF_PHY_PWR_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mvs_show_pcie_usage(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp = mvs_64xx_chip_reset(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tmp = mr32(MVS_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tmp &= ~PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tmp |= PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Init Chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* make sure RST is set; HBA_RST /should/ have done that for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cctl = mr32(MVS_CTL) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (cctl & CCTL_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cctl &= ~CCTL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mw32_f(MVS_CTL, cctl | CCTL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* write to device control _AND_ device status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tmp &= ~PRD_REQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tmp |= PRD_REQ_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tmp &= ~PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) tmp &= ~PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tmp &= PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tmp &= ~PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tmp = mr32(MVS_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp &= ~PCTL_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tmp |= PCTL_COM_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tmp &= ~PCTL_PHY_DSBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tmp |= PCTL_LINK_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tmp &= ~PCTL_LINK_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mw32(MVS_PHY_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mw32(MVS_PCS, 0); /* MVS_PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* init phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mvs_64xx_phy_hacks(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp &= 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmp |= 0x00fa0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* enable auto port detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mw32(MVS_TX_LO, mvi->tx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mw32(MVS_RX_LO, mvi->rx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* set phy local SAS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* should set little endian SAS address to 64xx chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cpu_to_be64(mvi->phy[i].dev_sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mvs_64xx_enable_xmt(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mvs_64xx_detect_porttype(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (mvi->flags & MVF_FLAG_SOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* set select registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(0x0E008000, regs + 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(0x59000008, regs + 0x004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(0x20, regs + 0x008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(0x20, regs + 0x00c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(0x20, regs + 0x010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(0x20, regs + 0x014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(0x20, regs + 0x018);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(0x20, regs + 0x01c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (i = 0; i < mvi->chip->n_phy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* clear phy int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp = mvs_read_port_irq_stat(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp &= ~PHYEV_SIG_FIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mvs_write_port_irq_stat(mvi, i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* set phy int mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PHYEV_DEC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mvs_write_port_irq_mask(mvi, i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mvs_update_phyinfo(mvi, i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* little endian for open address and command table, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cctl = mr32(MVS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cctl |= CCTL_ENDIAN_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cctl |= CCTL_ENDIAN_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cctl &= ~CCTL_ENDIAN_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cctl |= CCTL_ENDIAN_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mw32_f(MVS_CTL, cctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* reset CMD queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp = mr32(MVS_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tmp |= PCS_CMD_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tmp &= ~PCS_SELF_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mw32(MVS_PCS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * the max count is 0x1ff, while our max slot is 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * it will make count 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (MVS_CHIP_SLOT_SZ > 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mw32(MVS_INT_COAL, 0x1ff | COAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tmp = 0x10000 | interrupt_coalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mw32(MVS_INT_COAL_TMOUT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* ladies and gentlemen, start your engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mw32(MVS_TX_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* enable CMD/CMPL_Q/RESP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PCS_CMD_EN | PCS_CMD_STOP_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* enable completion queue interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CINT_DMA_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mw32(MVS_INT_MASK, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Enable SRS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int mvs_64xx_ioremap(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!mvs_ioremap(mvi, 4, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void mvs_64xx_iounmap(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mvs_iounmap(mvi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mvs_iounmap(mvi->regs_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tmp = mr32(MVS_GBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mw32(MVS_GBL_CTL, tmp | INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tmp = mr32(MVS_GBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mw32(MVS_GBL_CTL, tmp & ~INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!(mvi->flags & MVF_FLAG_SOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) stat = mr32(MVS_GBL_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (stat == 0 || stat == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) stat = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* clear CMD_CMPLT ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mw32_f(MVS_INT_STAT, CINT_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock(&mvi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mvs_int_full(mvi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spin_unlock(&mvi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } while (tmp & 1 << (slot_idx % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } while (tmp & 1 << (slot_idx % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 tfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (type == PORT_TYPE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mw32(MVS_INT_STAT_SRS_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mw32(MVS_INT_STAT, CINT_CI_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tmp = mr32(MVS_PCS) | 0xFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mw32(MVS_PCS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 tmp, offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (*tfs == MVS_ID_NOT_MAPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (*tfs < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tmp = mr32(MVS_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mw32(MVS_PCS, tmp & ~offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tmp = mr32(MVS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mw32(MVS_CTL, tmp & ~offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mw32(MVS_INT_STAT_SRS_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *tfs = MVS_ID_NOT_MAPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 tmp, offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (*tfs != MVS_ID_NOT_MAPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tmp = mr32(MVS_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) for (i = 0; i < mvi->chip->srs_sz; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (i == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tmp = mr32(MVS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!(tmp & offs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *tfs = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (i < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mw32(MVS_PCS, tmp | offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mw32(MVS_CTL, tmp | offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mw32(MVS_INT_STAT_SRS_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return MVS_ID_NOT_MAPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mvs_prd *buf_prd = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for_each_sg(scatter, sg, nr, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) buf_prd->len = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) buf_prd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 phy_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mvs_write_port_cfg_addr(mvi, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PHYR_PHY_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) phy_st = mvs_read_port_cfg_data(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (phy_st & PHY_OOB_DTCTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct sas_identify_frame *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct mvs_phy *phy = &mvi->phy[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct asd_sas_phy *sas_phy = &phy->sas_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sas_phy->linkrate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) phy->minimum_linkrate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (phy->phy_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) phy->maximum_linkrate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) (phy->phy_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) phy->dev_info = mvs_read_port_cfg_data(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) phy->att_dev_sas_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) (u64) mvs_read_port_cfg_data(mvi, i) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct mvs_phy *phy = &mvi->phy[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tmp = mvs_read_port_vsr_data(mvi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SAS_LINK_RATE_1_5_GBPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tmp &= ~PHY_MODE6_LATECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tmp |= PHY_MODE6_LATECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mvs_write_port_vsr_data(mvi, i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct sas_phy_linkrates *rates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 lrmin = 0, lrmax = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tmp = mvs_read_phy_ctl(mvi, phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) lrmin = (rates->minimum_linkrate << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) lrmax = (rates->maximum_linkrate << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (lrmin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tmp &= ~(0xf << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tmp |= lrmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (lrmax) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tmp &= ~(0xf << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tmp |= lrmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mvs_write_phy_ctl(mvi, phy_id, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tmp = mr32(MVS_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mw32(MVS_PCS, tmp & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mw32(MVS_PCS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tmp = mr32(MVS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mw32(MVS_CTL, tmp & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mw32(MVS_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void __iomem *regs = mvi->regs_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ior32(SPI_DATA_REG_64XX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void __iomem *regs = mvi->regs_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iow32(SPI_DATA_REG_64XX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 *dwCmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u8 cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 dwTmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dwTmp = ((u32)cmd << 24) | ((u32)length << 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dwTmp |= 1U<<23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (addr != MV_MAX_U32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dwTmp |= 1U<<22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dwTmp |= (addr & 0x0003FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *dwCmd = dwTmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void __iomem *regs = mvi->regs_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (retry = 0; retry < 1; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) iow32(SPI_CMD_REG_64XX, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) iow32(SPI_CTRL_REG_64XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) void __iomem *regs = mvi->regs_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 i, dwTmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) for (i = 0; i < timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dwTmp = ior32(SPI_CTRL_REG_64XX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!(dwTmp & SPI_CTRL_SPISTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int buf_len, int from, void *prd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct mvs_prd *buf_prd = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dma_addr_t buf_dma = mvi->bulk_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) buf_prd += from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (i = 0; i < MAX_SG_ENTRY - from; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) buf_prd->addr = cpu_to_le64(buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) buf_prd->len = cpu_to_le32(buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ++buf_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void __iomem *regs = mvi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * the max count is 0x1ff, while our max slot is 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * it will make count 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (time == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mw32(MVS_INT_COAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mw32(MVS_INT_COAL_TMOUT, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (MVS_CHIP_SLOT_SZ > 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mw32(MVS_INT_COAL, 0x1ff|COAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tmp = 0x10000 | time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mw32(MVS_INT_COAL_TMOUT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) const struct mvs_dispatch mvs_64xx_dispatch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "mv64xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mvs_64xx_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mvs_64xx_ioremap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mvs_64xx_iounmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mvs_64xx_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mvs_64xx_isr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mvs_64xx_interrupt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mvs_64xx_interrupt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mvs_read_phy_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mvs_write_phy_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mvs_read_port_cfg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mvs_write_port_cfg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mvs_write_port_cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mvs_read_port_vsr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mvs_write_port_vsr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mvs_write_port_vsr_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mvs_read_port_irq_stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mvs_write_port_irq_stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mvs_read_port_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mvs_write_port_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mvs_64xx_command_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mvs_64xx_clear_srs_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mvs_64xx_issue_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mvs_start_delivery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mvs_rx_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mvs_int_full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mvs_64xx_assign_reg_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mvs_64xx_free_reg_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mvs_get_prd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mvs_get_prd_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mvs_64xx_make_prd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mvs_64xx_detect_porttype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mvs_64xx_oob_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mvs_64xx_fix_phy_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mvs_64xx_phy_work_around,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mvs_64xx_phy_set_link_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mvs_hw_max_link_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mvs_64xx_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mvs_64xx_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mvs_64xx_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mvs_64xx_stp_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mvs_64xx_clear_active_cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mvs_64xx_spi_read_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mvs_64xx_spi_write_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mvs_64xx_spi_buildcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mvs_64xx_spi_issuecmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mvs_64xx_spi_waitdataready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mvs_64xx_fix_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mvs_64xx_tune_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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