^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This is the Fusion MPT base driver providing common API layer interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * for access to MPT (Message Passing Technology) firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012-2014 LSI Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013-2014 Avago Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (mailto: MPT-FusionLinux.pdl@avagotech.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as published by the Free Software Foundation; either version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <asm/page.h> /* To get host page size per arch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include "mpt3sas_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* maximum controller queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX_HBA_QUEUE_DEPTH 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX_CHAIN_DEPTH 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int max_queue_depth = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) module_param(max_queue_depth, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int max_sgl_entries = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) module_param(max_sgl_entries, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int msix_disable = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_param(msix_disable, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int smp_affinity_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) module_param(smp_affinity_enable, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int max_msix_vectors = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_param(max_msix_vectors, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_PARM_DESC(max_msix_vectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) " max msix vectors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int irqpoll_weight = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) module_param(irqpoll_weight, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_PARM_DESC(irqpoll_weight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "irq poll weight (default= one fourth of HBA queue depth)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int mpt3sas_fwfault_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_PARM_DESC(mpt3sas_fwfault_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) " enable detection of firmware fault and halt firmware - (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int perf_mode = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) module_param(perf_mode, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_PARM_DESC(perf_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "0 - balanced: high iops mode is enabled &\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "interrupt coalescing is enabled only on high iops queues,\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "1 - iops: high iops mode is disabled &\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "interrupt coalescing is enabled on all queues,\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "2 - latency: high iops mode is disabled &\n\t\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "\t\tdefault - default perf_mode is 'balanced'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum mpt3sas_perf_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MPT_PERF_MODE_DEFAULT = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MPT_PERF_MODE_BALANCED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MPT_PERF_MODE_IOPS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MPT_PERF_MODE_LATENCY = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 ioc_state, int timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * mpt3sas_base_check_cmd_timeout - Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * to check timeout and command termination due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * to Host reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @ioc: per adapter object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @status: Status of issued command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @mpi_request:mf request pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @sz: size of buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @Returns - 1/0 Reset to be done or Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 status, void *mpi_request, int sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 issue_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!(status & MPT3_CMD_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) issue_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ioc_err(ioc, "Command %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) _debug_dump_mf(mpi_request, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return issue_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @val: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @kp: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Return: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret = param_set_int(val, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct MPT3SAS_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* global ioc spinlock to protect controller list on list operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_lock(&gioc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ioc->fwfault_debug = mpt3sas_fwfault_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) spin_unlock(&gioc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) param_get_int, &mpt3sas_fwfault_debug, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * _base_readl_aero - retry readl for max three times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @addr: MPT Fusion system interface register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Retry the readl() for max three times if it gets zero value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * while reading the system interface register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) _base_readl_aero(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 i = 0, ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret_val = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } while (ret_val == 0 && i < 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) _base_readl(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * in BAR0 space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @reply: reply message frame(lower 32bit addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @index: System request message index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 256 is offset within sys register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 256 offset MPI frame starts. Max MPI frame supported is 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 cmd_credit = ioc->facts.RequestCredit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MPI_FRAME_START_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (cmd_credit * ioc->request_sz) + (index * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(reply, reply_free_iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * to system/BAR0 region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @dst_iomem: Pointer to the destination location in BAR0 space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @src: Pointer to the Source data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @size: Size of data to be copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 *src_virt_mem = (u32 *)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) for (i = 0; i < size/4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel((u32)src_virt_mem[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (void __iomem *)dst_iomem + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @dst_iomem: Pointer to the destination location in BAR0 space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @src: Pointer to the Source data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @size: Size of data to be copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 *src_virt_mem = (u32 *)(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) for (i = 0; i < size/4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel((u32)src_virt_mem[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (void __iomem *)dst_iomem + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * _base_get_chain - Calculates and Returns virtual chain address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * for the provided smid in BAR0 space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @sge_chain_count: Scatter gather chain count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Return: the chain address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline void __iomem*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 sge_chain_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *base_chain, *chain_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 cmd_credit = ioc->facts.RequestCredit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (cmd_credit * ioc->request_sz) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) REPLY_FREE_POOL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ioc->request_sz) + (sge_chain_count * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return chain_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * _base_get_chain_phys - Calculates and Returns physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * in BAR0 for scatter gather chains, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * the provided smid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @sge_chain_count: Scatter gather chain count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Return: Physical chain address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline phys_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 sge_chain_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) phys_addr_t base_chain_phys, chain_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u16 cmd_credit = ioc->facts.RequestCredit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (cmd_credit * ioc->request_sz) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) REPLY_FREE_POOL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ioc->request_sz) + (sge_chain_count * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return chain_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * buffer address for the provided smid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * (Each smid can have 64K starts from 17024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Return: Pointer to buffer location in BAR0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void __iomem *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 cmd_credit = ioc->facts.RequestCredit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) // Added extra 1 to reach end of chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *chain_end = _base_get_chain(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cmd_credit + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ioc->facts.MaxChainDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return chain_end + (smid * 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Host buffer Physical address for the provided smid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * (Each smid can have 64K starts from 17024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Return: Pointer to buffer location in BAR0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static phys_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u16 cmd_credit = ioc->facts.RequestCredit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cmd_credit + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ioc->facts.MaxChainDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return chain_end_phys + (smid * 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * lookup list and Provides chain_buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * address for the matching dma address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * (Each smid can have 64K starts from 17024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * @chain_buffer_dma: Chain buffer dma address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Return: Pointer to chain buffer. Or Null on Failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dma_addr_t chain_buffer_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 index, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct chain_tracker *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (index = 0; index < ioc->scsiio_depth; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (j = 0; j < ioc->chains_needed_per_io; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ct = &ioc->chain_lookup[index].chains_per_smid[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ct && ct->chain_buffer_dma == chain_buffer_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ct->chain_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * _clone_sg_entries - MPI EP's scsiio and config requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * are handled here. Base function for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * double buffering, before submitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * the requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @ioc: per adapter object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @mpi_request: mf request pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @smid: system request message index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void *mpi_request, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) Mpi2SGESimple32_t *sgel, *sgel_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 sgl_flags, sge_chain_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool is_write = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u16 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void __iomem *buffer_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) phys_addr_t buffer_iomem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void __iomem *buff_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) phys_addr_t buff_ptr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) phys_addr_t dst_addr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MPI2RequestHeader_t *request_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct scsi_cmnd *scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct scatterlist *sg_scmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int is_scsiio_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) request_hdr = (MPI2RequestHeader_t *) mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) Mpi25SCSIIORequest_t *scsiio_request =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (Mpi25SCSIIORequest_t *)mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) is_scsiio_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) Mpi2ConfigRequest_t *config_req =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (Mpi2ConfigRequest_t *)mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* From smid we can get scsi_cmd, once we have sg_scmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * we just need to get sg_virt and sg_next to get virual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * address associated with sgel->Address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (is_scsiio_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Get scsi_cmd using smid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (scmd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ioc_err(ioc, "scmd is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Get sg_scmd from scmd provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sg_scmd = scsi_sglist(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * 0 - 255 System register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * 256 - 4352 MPI Frame. (This is based on maxCredit 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * 4352 - 4864 Reply_free pool (512 byte is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * considering maxCredit 32. Reply need extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * room, for mCPU case kept four times of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * maxCredit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * 4864 - 17152 SGE chain element. (32cmd * 3 chain of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * 128 byte size = 12288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * 17152 - x Host buffer mapped with smid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * (Each smid can have 64K Max IO.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * BAR0+Last 1K MSIX Addr and Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Total size in use 2113664 bytes of 4MB BAR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) buffer_iomem = _base_get_buffer_bar0(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) buff_ptr = buffer_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) buff_ptr_phys = buffer_iomem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) WARN_ON(buff_ptr_phys > U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) is_write = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sgl_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Helper function which on passing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * chain_buffer_dma returns chain_buffer. Get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * the virtual address for sgel->Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sgel_next =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) _base_get_chain_buffer_dma_to_chain_buffer(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) le32_to_cpu(sgel->Address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (sgel_next == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * This is coping 128 byte chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * frame (not a host buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dst_chain_addr[sge_chain_count] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) _base_get_chain(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) smid, sge_chain_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) src_chain_addr[sge_chain_count] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (void *) sgel_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dst_addr_phys = _base_get_chain_phys(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) smid, sge_chain_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) WARN_ON(dst_addr_phys > U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sgel->Address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cpu_to_le32(lower_32_bits(dst_addr_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sgel = sgel_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sge_chain_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (is_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (is_scsiio_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) _base_clone_to_sys_mem(buff_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sg_virt(sg_scmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x00ffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * FIXME: this relies on a a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * PCI mem_offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sgel->Address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) cpu_to_le32((u32)buff_ptr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) _base_clone_to_sys_mem(buff_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ioc->config_vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) (le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x00ffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sgel->Address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cpu_to_le32((u32)buff_ptr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x00ffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x00ffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if ((le32_to_cpu(sgel->FlagsLength) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) (MPI2_SGE_FLAGS_END_OF_BUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) << MPI2_SGE_FLAGS_SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto eob_clone_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Every single element in MPT will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * associated sg_next. Better to sanity that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * sg_next is not NULL, but it will be a bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * if it is null.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (is_scsiio_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (sg_scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sgel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto eob_clone_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) eob_clone_chain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) for (i = 0; i < sge_chain_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (is_scsiio_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) _base_clone_to_sys_mem(dst_chain_addr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) src_chain_addr[i], ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @arg: input argument, used to derive ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * 0 if controller is removed from pci subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * -1 for other case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int mpt3sas_remove_dead_ioc_func(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pdev = ioc->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pci_stop_and_remove_bus_device_locked(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * _base_fault_reset_work - workq handling ioc fault conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @work: input argument, used to derive ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Context: sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) _base_fault_reset_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct MPT3SAS_ADAPTER *ioc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct task_struct *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ioc->pci_error_recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto rearm_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) doorbell = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ioc_err(ioc, "SAS host is non-operational !!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* It may be possible that EEH recovery can resolve some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * pci bus failure issues rather removing the dead ioc function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * by considering controller is in a non-operational state. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * here priority is given to the EEH recovery. If it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * not resolve this issue, mpt3sas driver will consider this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * controller to non-operational state and remove the dead ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ioc->non_operational_loop++ < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto rearm_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Call _scsih_flush_pending_cmds callback so that we flush all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * pending commands back to OS. This call is required to aovid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * deadlock at block layer. Dead IOC will fail to do diag reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * and this call is safe since dead ioc will never return any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * command back from HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ioc->schedule_dead_ioc_flush_running_cmds(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * Set remove_host flag early since kernel thread will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * take some time to execute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ioc->remove_host = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*Remove the Dead Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (IS_ERR(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return; /* don't rearm timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ioc->manu_pg11.CoreDumpTOSec :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) timeout /= (FAULT_POLLING_INTERVAL/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ioc->ioc_coredump_loop == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mpt3sas_print_coredump_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) doorbell & MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* do not accept any IOs and disable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ioc->shost_recovery = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mpt3sas_base_mask_interrupts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) _base_clear_outstanding_commands(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ioc_info(ioc, "%s: CoreDump loop %d.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __func__, ioc->ioc_coredump_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Wait until CoreDump completes or times out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ioc->ioc_coredump_loop++ < timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto rearm_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ioc->ioc_coredump_loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __func__, ioc->ioc_coredump_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __func__, ioc->ioc_coredump_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ioc->non_operational_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ioc_warn(ioc, "%s: hard reset: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __func__, rc == 0 ? "success" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) doorbell = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mpt3sas_print_fault_code(ioc, doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MPI2_IOC_STATE_COREDUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mpt3sas_print_coredump_info(ioc, doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MPI2_IOC_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return; /* don't rearm timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ioc->ioc_coredump_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rearm_timer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ioc->fault_reset_work_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) queue_delayed_work(ioc->fault_reset_work_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &ioc->fault_reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) msecs_to_jiffies(FAULT_POLLING_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * mpt3sas_base_start_watchdog - start the fault_reset_work_q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Context: sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ioc->fault_reset_work_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* initialize fault polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) snprintf(ioc->fault_reset_work_q_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ioc->driver_name, ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ioc->fault_reset_work_q =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) create_singlethread_workqueue(ioc->fault_reset_work_q_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!ioc->fault_reset_work_q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ioc->fault_reset_work_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) queue_delayed_work(ioc->fault_reset_work_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &ioc->fault_reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) msecs_to_jiffies(FAULT_POLLING_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Context: sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) wq = ioc->fault_reset_work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ioc->fault_reset_work_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) flush_workqueue(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) destroy_workqueue(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * @fault_code: fault code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * @fault_code: fault code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Return nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * completes or times out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @caller: caller function name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) const char *caller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ioc->manu_pg11.CoreDumpTOSec :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ioc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ioc_err(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "%s: CoreDump timed out. (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) caller, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "%s: CoreDump completed. (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) caller, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * mpt3sas_halt_firmware - halt's mpt controller firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * For debugging timeout related issues. Writing 0xCOFFEE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * to the doorbell register will halt controller firmware. With
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * the purpose to stop both driver and firmware, the enduser can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * obtain a ring buffer from controller UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!ioc->fwfault_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dump_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) doorbell = ioc->base_readl(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mpt3sas_print_fault_code(ioc, doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mpt3sas_print_coredump_info(ioc, doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) writel(0xC0FFEE00, &ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ioc_err(ioc, "Firmware is halted due to command timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ioc->fwfault_debug == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) panic("panic in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * _base_sas_ioc_info - verbose translation of the ioc status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * @mpi_reply: reply mf payload returned from firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * @request_hdr: request mf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MPI2RequestHeader_t *request_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) char *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u16 frame_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) char *func_str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) switch (ioc_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Common IOCStatus values for all replies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case MPI2_IOCSTATUS_INVALID_FUNCTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) desc = "invalid function";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case MPI2_IOCSTATUS_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) desc = "busy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case MPI2_IOCSTATUS_INVALID_SGL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) desc = "invalid sgl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case MPI2_IOCSTATUS_INTERNAL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) desc = "internal error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case MPI2_IOCSTATUS_INVALID_VPID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) desc = "invalid vpid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) desc = "insufficient resources";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) desc = "insufficient power";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case MPI2_IOCSTATUS_INVALID_FIELD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) desc = "invalid field";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case MPI2_IOCSTATUS_INVALID_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) desc = "invalid state";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) desc = "op state not supported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * Config IOCStatus values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) desc = "config invalid action";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) desc = "config invalid type";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) desc = "config invalid page";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) desc = "config invalid data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) desc = "config no defaults";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) desc = "config cant commit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * SCSI IO Reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * For use by SCSI Initiator and SCSI Target end-to-end data protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) desc = "eedp guard error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) desc = "eedp ref tag error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) desc = "eedp app tag error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * SCSI Target values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) desc = "target invalid io index";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case MPI2_IOCSTATUS_TARGET_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) desc = "target aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) desc = "target no conn retryable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) desc = "target no connection";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) desc = "target xfer count mismatch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) desc = "target data offset error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) desc = "target too much write data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) desc = "target iu too short";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) desc = "target ack nak timeout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) desc = "target nak received";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * Serial Attached SCSI values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) desc = "smp request failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) desc = "smp data overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Diagnostic Buffer Post / Diagnostic Release values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) desc = "diagnostic released";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) switch (request_hdr->Function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case MPI2_FUNCTION_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) func_str = "config_page";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case MPI2_FUNCTION_SCSI_TASK_MGMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) func_str = "task_mgmt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) func_str = "sas_iounit_ctl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) frame_sz = sizeof(Mpi2SepRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) func_str = "enclosure";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case MPI2_FUNCTION_IOC_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) frame_sz = sizeof(Mpi2IOCInitRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) func_str = "ioc_init";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case MPI2_FUNCTION_PORT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) frame_sz = sizeof(Mpi2PortEnableRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) func_str = "port_enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case MPI2_FUNCTION_SMP_PASSTHROUGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) func_str = "smp_passthru";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case MPI2_FUNCTION_NVME_ENCAPSULATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) func_str = "nvme_encapsulated";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) frame_sz = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) func_str = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) desc, ioc_status, request_hdr, func_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) _debug_dump_mf(request_hdr, frame_sz/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * _base_display_event_data - verbose translation of firmware asyn events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * @mpi_reply: reply mf payload returned from firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) Mpi2EventNotificationReply_t *mpi_reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) char *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u16 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) event = le16_to_cpu(mpi_reply->Event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case MPI2_EVENT_LOG_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) desc = "Log Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case MPI2_EVENT_STATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) desc = "Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case MPI2_EVENT_HARD_RESET_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) desc = "Hard Reset Received";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case MPI2_EVENT_EVENT_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) desc = "Event Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) desc = "Device Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) case MPI2_EVENT_IR_OPERATION_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) desc = "IR Operation Status";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case MPI2_EVENT_SAS_DISCOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) Mpi2EventDataSasDiscovery_t *event_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ioc_info(ioc, "Discovery: (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "start" : "stop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (event_data->DiscoveryStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pr_cont(" discovery_status(0x%08x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) le32_to_cpu(event_data->DiscoveryStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) desc = "SAS Broadcast Primitive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) desc = "SAS Init Device Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) desc = "SAS Init Table Overflow";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) desc = "SAS Topology Change List";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) desc = "SAS Enclosure Device Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) case MPI2_EVENT_IR_VOLUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) desc = "IR Volume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case MPI2_EVENT_IR_PHYSICAL_DISK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) desc = "IR Physical Disk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) desc = "IR Configuration Change List";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case MPI2_EVENT_LOG_ENTRY_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) desc = "Log Entry Added";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case MPI2_EVENT_TEMP_THRESHOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) desc = "Temperature Threshold";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) desc = "Cable Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) desc = "SAS Device Discovery Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) desc = "PCIE Device Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case MPI2_EVENT_PCIE_ENUMERATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) Mpi26EventDataPCIeEnumeration_t *event_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ioc_info(ioc, "PCIE Enumeration: (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "start" : "stop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (event_data->EnumerationStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pr_cont("enumeration_status(0x%08x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) le32_to_cpu(event_data->EnumerationStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) desc = "PCIE Topology Change List";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ioc_info(ioc, "%s\n", desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * _base_sas_log_info - verbose translation of firmware log info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * @log_info: log info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) union loginfo_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u32 loginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 subcode:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) u32 code:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u32 originator:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) u32 bus_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) union loginfo_type sas_loginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) char *originator_str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sas_loginfo.loginfo = log_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* each nexus loss loginfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (log_info == 0x31170000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* eat the loginfos associated with task aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) 0x31140000 || log_info == 0x31130000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) switch (sas_loginfo.dw.originator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) originator_str = "IOP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) originator_str = "PL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!ioc->hide_ir_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) originator_str = "IR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) originator_str = "WarpDrive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) log_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * _base_display_reply_info -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * @msix_index: MSIX table index supplied by the OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * @reply: reply message frame(lower 32bit addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u32 reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) MPI2DefaultReply_t *mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u16 ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 loginfo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (unlikely(!mpi_reply)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) __FILE__, __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (ioc->logging_level & MPT_DEBUG_REPLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) _base_sas_ioc_info(ioc , mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mpt3sas_base_get_msg_frame(ioc, smid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) _base_sas_log_info(ioc, loginfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (ioc_status || loginfo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ioc_status &= MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * mpt3sas_base_done - base internal command completion routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * @msix_index: MSIX table index supplied by the OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * @reply: reply message frame(lower 32bit addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * 1 meaning mf should be freed from _base_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * 0 means the mf is freed from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) u32 reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) MPI2DefaultReply_t *mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (mpi_reply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) complete(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * _base_async_event - main callback handler for firmware asyn events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * @msix_index: MSIX table index supplied by the OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * @reply: reply message frame(lower 32bit addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * 1 meaning mf should be freed from _base_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * 0 means the mf is freed from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) Mpi2EventNotificationReply_t *mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) Mpi2EventAckRequest_t *ack_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct _event_ack_list *delayed_event_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (!mpi_reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) _base_display_event_data(ioc, mpi_reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!delayed_event_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) INIT_LIST_HEAD(&delayed_event_ack->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) delayed_event_ack->Event = mpi_reply->Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) delayed_event_ack->EventContext = mpi_reply->EventContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) list_add_tail(&delayed_event_ack->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) &ioc->delayed_event_ack_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dewtprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) le16_to_cpu(mpi_reply->Event)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ack_request->Event = mpi_reply->Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ack_request->EventContext = mpi_reply->EventContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ack_request->VF_ID = 0; /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ack_request->VP_ID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* scsih callback handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mpt3sas_scsih_event_callback(ioc, msix_index, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* ctl callback handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mpt3sas_ctl_event_callback(ioc, msix_index, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static struct scsiio_tracker *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (WARN_ON(!smid) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) WARN_ON(smid >= ioc->hi_priority_smid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return scsi_cmd_priv(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * _base_get_cb_idx - obtain the callback index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * Return: callback index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u8 cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (smid < ioc->hi_priority_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct scsiio_tracker *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (smid < ctl_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) st = _get_st_from_smid(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) cb_idx = st->cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) } else if (smid == ctl_smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) cb_idx = ioc->ctl_cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) } else if (smid < ioc->internal_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) i = smid - ioc->hi_priority_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) cb_idx = ioc->hpr_lookup[i].cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) } else if (smid <= ioc->hba_queue_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) i = smid - ioc->internal_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) cb_idx = ioc->internal_lookup[i].cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * mpt3sas_base_mask_interrupts - disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * Disabling ResetIRQ, Reply and Doorbell Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) u32 him_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ioc->mask_interrupts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) writel(him_register, &ioc->chip->HostInterruptMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ioc->base_readl(&ioc->chip->HostInterruptMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * mpt3sas_base_unmask_interrupts - enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * Enabling only Reply Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) u32 him_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) him_register &= ~MPI2_HIM_RIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) writel(him_register, &ioc->chip->HostInterruptMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ioc->mask_interrupts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) union reply_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) u64 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) u32 low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static u32 base_mod64(u64 dividend, u32 divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) u32 remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (!divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) remainder = do_div(dividend, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * _base_process_reply_queue - Process reply descriptors from reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * descriptor post queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * @reply_q: per IRQ's reply queue object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * Return: number of reply descriptors processed from reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * descriptor queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) _base_process_reply_queue(struct adapter_reply_queue *reply_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) union reply_descriptor rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) u64 completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u8 request_descript_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u32 reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) u8 msix_index = reply_q->msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) Mpi2ReplyDescriptorsUnion_t *rpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) u8 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) completed_cmds = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (!atomic_add_unless(&reply_q->busy, 1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) request_descript_type = rpf->Default.ReplyFlags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) atomic_dec(&reply_q->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) rd.word = le64_to_cpu(rpf->Words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) reply = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (request_descript_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) request_descript_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) request_descript_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) cb_idx = _base_get_cb_idx(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) (likely(mpt_callbacks[cb_idx] != NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) rc = mpt_callbacks[cb_idx](ioc, smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) msix_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) mpt3sas_base_free_smid(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) } else if (request_descript_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) reply = le32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) rpf->AddressReply.ReplyFrameAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (reply > ioc->reply_dma_max_address ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) reply < ioc->reply_dma_min_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) reply = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) cb_idx = _base_get_cb_idx(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) (likely(mpt_callbacks[cb_idx] != NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) rc = mpt_callbacks[cb_idx](ioc, smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) msix_index, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) _base_display_reply_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) smid, msix_index, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) mpt3sas_base_free_smid(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) _base_async_event(ioc, msix_index, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* reply free queue handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (reply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ioc->reply_free_host_index =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) (ioc->reply_free_host_index ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) (ioc->reply_free_queue_depth - 1)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) 0 : ioc->reply_free_host_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ioc->reply_free[ioc->reply_free_host_index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) cpu_to_le32(reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) _base_clone_reply_to_sys_mem(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ioc->reply_free_host_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) writel(ioc->reply_free_host_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) &ioc->chip->ReplyFreeHostIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) rpf->Words = cpu_to_le64(ULLONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) reply_q->reply_post_host_index =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) (reply_q->reply_post_host_index ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) (ioc->reply_post_queue_depth - 1)) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) reply_q->reply_post_host_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) request_descript_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) reply_q->reply_post_free[reply_q->reply_post_host_index].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) completed_cmds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* Update the reply post host index after continuously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * processing the threshold number of Reply Descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * So that FW can find enough entries to post the Reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Descriptors in the reply descriptor post queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (completed_cmds >= ioc->thresh_hold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (ioc->combined_reply_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) writel(reply_q->reply_post_host_index |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ((msix_index & 7) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) MPI2_RPHI_MSIX_INDEX_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ioc->replyPostRegisterIndex[msix_index/8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) writel(reply_q->reply_post_host_index |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) (msix_index <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) MPI2_RPHI_MSIX_INDEX_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) &ioc->chip->ReplyPostHostIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!reply_q->irq_poll_scheduled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) reply_q->irq_poll_scheduled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) irq_poll_sched(&reply_q->irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) atomic_dec(&reply_q->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (!reply_q->reply_post_host_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) rpf = reply_q->reply_post_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) rpf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (!completed_cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) atomic_dec(&reply_q->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (ioc->is_warpdrive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) writel(reply_q->reply_post_host_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ioc->reply_post_host_index[msix_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) atomic_dec(&reply_q->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Update Reply Post Host Index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * For those HBA's which support combined reply queue feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * 1. Get the correct Supplemental Reply Post Host Index Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * Index Register address bank i.e replyPostRegisterIndex[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * 2. Then update this register with new reply host index value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * in ReplyPostIndex field and the MSIxIndex field with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * msix_index value reduced to a value between 0 and 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * using a modulo 8 operation. Since each Supplemental Reply Post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * Host Index Register supports 8 MSI-X vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * For other HBA's just update the Reply Post Host Index register with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * new reply host index value in ReplyPostIndex Field and msix_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * value in MSIxIndex field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (ioc->combined_reply_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) MPI2_RPHI_MSIX_INDEX_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ioc->replyPostRegisterIndex[msix_index/8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) writel(reply_q->reply_post_host_index | (msix_index <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) MPI2_RPHI_MSIX_INDEX_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) &ioc->chip->ReplyPostHostIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) atomic_dec(&reply_q->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return completed_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * @irq: irq number (not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * Return: IRQ_HANDLED if processed, else IRQ_NONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) _base_interrupt(int irq, void *bus_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct adapter_reply_queue *reply_q = bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (ioc->mask_interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (reply_q->irq_poll_scheduled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return ((_base_process_reply_queue(reply_q) > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) IRQ_HANDLED : IRQ_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * _base_irqpoll - IRQ poll callback handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * @irqpoll: irq_poll object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * @budget: irq poll weight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * returns number of reply descriptors processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) _base_irqpoll(struct irq_poll *irqpoll, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) int num_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) reply_q = container_of(irqpoll, struct adapter_reply_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (reply_q->irq_line_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) disable_irq_nosync(reply_q->os_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) reply_q->irq_line_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) num_entries = _base_process_reply_queue(reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (num_entries < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) irq_poll_complete(irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) reply_q->irq_poll_scheduled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) reply_q->irq_line_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) enable_irq(reply_q->os_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * Go for one more round of processing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * reply descriptor post queue incase if HBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * Firmware has posted some reply descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * while reenabling the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) _base_process_reply_queue(reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * _base_init_irqpolls - initliaze IRQ polls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * returns nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct adapter_reply_queue *reply_q, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (list_empty(&ioc->reply_queue_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) irq_poll_init(&reply_q->irqpoll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ioc->hba_queue_depth/4, _base_irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) reply_q->irq_poll_scheduled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) reply_q->irq_line_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) reply_q->os_irq = pci_irq_vector(ioc->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) reply_q->msix_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * _base_is_controller_msix_enabled - is controller support muli-reply queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * Return: Whether or not MSI/X is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * @poll: poll over reply descriptor pools incase interrupt for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * timed-out SCSI command got delayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * Context: non ISR conext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * Called when a Task Management request has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* If MSIX capability is turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * then multi-queues are not enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (!_base_is_controller_msix_enabled(ioc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ioc->shost_recovery || ioc->remove_host ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ioc->pci_error_recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* TMs are on msix_index == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (reply_q->msix_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (reply_q->irq_poll_scheduled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* Calling irq_poll_disable will wait for any pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * callbacks to have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) irq_poll_disable(&reply_q->irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) irq_poll_enable(&reply_q->irqpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* check how the scheduled poll has ended,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * clean up only if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (reply_q->irq_poll_scheduled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) reply_q->irq_poll_scheduled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) reply_q->irq_line_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) enable_irq(reply_q->os_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) _base_process_reply_queue(reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * mpt3sas_base_release_callback_handler - clear interrupt callback handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * @cb_idx: callback index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) mpt3sas_base_release_callback_handler(u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) mpt_callbacks[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * @cb_func: callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * Return: Index of @cb_func.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (mpt_callbacks[cb_idx] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) mpt_callbacks[cb_idx] = cb_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) mpt3sas_base_initialize_callback_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) mpt3sas_base_release_callback_handler(cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * _base_build_zero_len_sge - build zero length sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * @paddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * Create a zero length scatter gather entry to insure the IOCs hardware has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * something to use if the target device goes brain dead and tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * to send data even when none is asked for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) MPI2_SGE_FLAGS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ioc->base_add_sg_single(paddr, flags_length, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * @paddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * @flags_length: SGE flags and data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) Mpi2SGESimple32_t *sgel = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) sgel->FlagsLength = cpu_to_le32(flags_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) sgel->Address = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * @paddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * @flags_length: SGE flags and data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) Mpi2SGESimple64_t *sgel = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) sgel->FlagsLength = cpu_to_le32(flags_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) sgel->Address = cpu_to_le64(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * _base_get_chain_buffer_tracker - obtain chain tracker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * @scmd: SCSI commands of the IO request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * Return: chain tracker from chain_lookup table using key as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * smid and smid's chain_offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static struct chain_tracker *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct scsi_cmnd *scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct chain_tracker *chain_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct scsiio_tracker *st = scsi_cmd_priv(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u16 smid = st->smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) u8 chain_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (chain_offset == ioc->chains_needed_per_io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return chain_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * _base_build_sg - build generic sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * @psge: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * @data_out_dma: physical address for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * @data_out_sz: data xfer size for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * @data_in_dma: physical address for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * @data_in_sz: data xfer size for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) size_t data_in_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) u32 sgl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (!data_out_sz && !data_in_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) _base_build_zero_len_sge(ioc, psge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (data_out_sz && data_in_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* WRITE sgel first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ioc->base_add_sg_single(psge, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) data_out_sz, data_out_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* incr sgel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) psge += ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* READ sgel last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) MPI2_SGE_FLAGS_END_OF_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ioc->base_add_sg_single(psge, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) data_in_sz, data_in_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) } else if (data_out_sz) /* WRITE */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ioc->base_add_sg_single(psge, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) data_out_sz, data_out_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) } else if (data_in_sz) /* READ */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) MPI2_SGE_FLAGS_END_OF_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ioc->base_add_sg_single(psge, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) data_in_sz, data_in_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* IEEE format sgls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * _base_build_nvme_prp - This function is called for NVMe end devices to build
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * entry of the NVMe message (PRP1). If the data buffer is small enough to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * used to describe a larger data buffer. If the data buffer is too large to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * describe using the two PRP entriess inside the NVMe message, then PRP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * describes the first data memory segment, and PRP2 contains a pointer to a PRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * list located elsewhere in memory to describe the remaining data memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * segments. The PRP list will be contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * consists of a list of PRP entries to describe a number of noncontigous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * physical memory segments as a single memory buffer, just as a SGL does. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * however, that this function is only used by the IOCTL call, so the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * given will be guaranteed to be contiguous. There is no need to translate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * non-contiguous SGL into a PRP in this case. All PRPs will describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * contiguous space that is one page size each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) * Each NVMe message contains two PRP entries. The first (PRP1) either contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * a PRP list pointer or a PRP element, depending upon the command. PRP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * contains the second PRP element if the memory being described fits within 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * A PRP list pointer contains the address of a PRP list, structured as a linear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * array of PRP entries. Each PRP entry in this list describes a segment of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * physical memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * Each 64-bit PRP entry comprises an address and an offset field. The address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * always points at the beginning of a 4KB physical memory page, and the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) * describes where within that 4KB page the memory segment begins. Only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * first element in a PRP list may contain a non-zero offest, implying that all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) * memory segments following the first begin at the start of a 4KB page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) * Each PRP element normally describes 4KB of physical memory, with exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) * for the first and last elements in the list. If the memory being described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) * by the list begins at a non-zero offset within the first 4KB page, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) * first PRP element will contain a non-zero offset indicating where the region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) * begins within the 4KB page. The last memory segment may end before the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) * of the 4KB segment, depending upon the overall size of the memory being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) * described by the PRP list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * Since PRP entries lack any indication of size, the overall data buffer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * is used to determine where the end of the data memory buffer is located, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * how many PRP entries are required to describe it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * @smid: system request message index for getting asscociated SGL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * @nvme_encap_request: the NVMe request msg frame pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) * @data_out_dma: physical address for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) * @data_out_sz: data xfer size for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) * @data_in_dma: physical address for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * @data_in_sz: data xfer size for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) size_t data_in_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) int prp_size = NVME_PRP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) __le64 *prp_entry, *prp1_entry, *prp2_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) __le64 *prp_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dma_addr_t prp_entry_dma, prp_page_dma, dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) u32 offset, entry_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) u32 page_mask_result, page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct mpt3sas_nvme_cmd *nvme_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) (void *)nvme_encap_request->NVMe_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * Not all commands require a data transfer. If no data, just return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * without constructing any PRP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (!data_in_sz && !data_out_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) prp1_entry = &nvme_cmd->prp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) prp2_entry = &nvme_cmd->prp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) prp_entry = prp1_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) * For the PRP entries, use the specially allocated buffer of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * contiguous memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * Check if we are within 1 entry of a page boundary we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * want our first entry to be a PRP List entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) page_mask = ioc->page_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (!page_mask_result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /* Bump up to next page boundary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) prp_page = (__le64 *)((u8 *)prp_page + prp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) prp_page_dma = prp_page_dma + prp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * Set PRP physical pointer, which initially points to the current PRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * DMA memory page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) prp_entry_dma = prp_page_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* Get physical address and length of the data buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (data_in_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dma_addr = data_in_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) length = data_in_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dma_addr = data_out_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) length = data_out_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* Loop while the length is not zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) while (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * Check if we need to put a list pointer here if we are at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * page boundary - prp_size (8 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) page_mask_result = (prp_entry_dma + prp_size) & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (!page_mask_result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * This is the last entry in a PRP List, so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * put a PRP list pointer here. What this does is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * - bump the current memory pointer to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * address, which will be the next full page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) * - set the PRP Entry to point to that page. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * is now the PRP List pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) * - bump the PRP Entry pointer the start of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) * next page. Since all of this PRP memory is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) * contiguous, no need to get a new page - it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * just the next address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) prp_entry_dma++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) *prp_entry = cpu_to_le64(prp_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) prp_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* Need to handle if entry will be part of a page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) offset = dma_addr & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) entry_len = ioc->page_size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (prp_entry == prp1_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * Must fill in the first PRP pointer (PRP1) before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * moving on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) *prp1_entry = cpu_to_le64(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) * Now point to the second PRP entry within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) * command (PRP2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) prp_entry = prp2_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) } else if (prp_entry == prp2_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * Should the PRP2 entry be a PRP List pointer or just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * a regular PRP pointer? If there is more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * more page of data, must use a PRP List pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (length > ioc->page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * PRP2 will contain a PRP List pointer because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) * more PRP's are needed with this command. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) * list will start at the beginning of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * contiguous buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) *prp2_entry = cpu_to_le64(prp_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * The next PRP Entry will be the start of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * first PRP List.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) prp_entry = prp_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * After this, the PRP Entries are complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * This command uses 2 PRP's and no PRP list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) *prp2_entry = cpu_to_le64(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) * Put entry in list and bump the addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) * After PRP1 and PRP2 are filled in, this will fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) * all remaining PRP entries in a PRP List, one per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) * each time through the loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) *prp_entry = cpu_to_le64(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) prp_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) prp_entry_dma++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * Bump the phys address of the command's data buffer by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) * entry_len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) dma_addr += entry_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) /* Decrement length accounting for last partial page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (entry_len > length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) length -= entry_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * base_make_prp_nvme -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * @scmd: SCSI command from the mid-layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) * @mpi_request: mpi request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * @smid: msg Index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * @sge_count: scatter gather element count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) * Return: true: PRPs are built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) * false: IEEE SGLs needs to be built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) struct scsi_cmnd *scmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) Mpi25SCSIIORequest_t *mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) u16 smid, int sge_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) int sge_len, num_prp_in_chain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) __le64 *curr_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) dma_addr_t msg_dma, sge_addr, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) u32 page_mask, page_mask_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct scatterlist *sg_scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) u32 first_prp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) int data_len = scsi_bufflen(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) u32 nvme_pg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * Nvme has a very convoluted prp format. One prp is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * for each page or partial page. Driver need to split up OS sg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) * entries if it is longer than one page or cross a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * boundary. Driver also have to insert a PRP list pointer entry as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * the last entry in each physical page of the PRP list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) * NOTE: The first PRP "entry" is actually placed in the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * SGL entry in the main message as IEEE 64 format. The 2nd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * entry in the main message is the chain element, and the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * of the PRP entries are built in the contiguous pcie buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) page_mask = nvme_pg_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * Native SGL is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * Put a chain element in main message frame that points to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * chain buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * NOTE: The ChainOffset field must be 0 when using a chain pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * a native SGL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* Set main message chain element pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) * For NVMe the chain element needs to be the 2nd SG entry in the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) * message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) main_chain_element = (Mpi25IeeeSgeChain64_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * For the PRP entries, use the specially allocated buffer of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * contiguous memory. Normal chain buffers can't be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * because each chain buffer would need to be the size of an OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * page (4k).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) main_chain_element->Address = cpu_to_le64(msg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) main_chain_element->NextChainOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) /* Build first prp, sge need not to be page aligned*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) sg_scmd = scsi_sglist(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) sge_addr = sg_dma_address(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) sge_len = sg_dma_len(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) offset = sge_addr & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) first_prp_len = nvme_pg_size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ptr_first_sgl->Address = cpu_to_le64(sge_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) data_len -= first_prp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) if (sge_len > first_prp_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) sge_addr += first_prp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) sge_len -= first_prp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) } else if (data_len && (sge_len == first_prp_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) sge_addr = sg_dma_address(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) sge_len = sg_dma_len(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) offset = sge_addr & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* Put PRP pointer due to page boundary*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (unlikely(!page_mask_result)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) scmd_printk(KERN_NOTICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) scmd, "page boundary curr_buff: 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) curr_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) msg_dma += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) *curr_buff = cpu_to_le64(msg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) curr_buff++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) num_prp_in_chain++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) *curr_buff = cpu_to_le64(sge_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) curr_buff++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) msg_dma += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) num_prp_in_chain++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) sge_addr += nvme_pg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) sge_len -= nvme_pg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) data_len -= nvme_pg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (data_len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) if (sge_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) sge_addr = sg_dma_address(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) sge_len = sg_dma_len(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) main_chain_element->Length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) cpu_to_le32(num_prp_in_chain * sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) u32 data_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) bool build_prp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) data_length = scsi_bufflen(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (pcie_device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) build_prp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return build_prp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) * we built IEEE SGL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) build_prp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) return build_prp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * determine if the driver needs to build a native SGL. If so, that native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * SGL is built in the special contiguous buffers allocated especially for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) * PCIe SGL creation. If the driver will not build a native SGL, return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) * TRUE and a normal IEEE SGL will be built. Currently this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) * supports NVMe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * @mpi_request: mf request pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) * @scmd: scsi command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) * @pcie_device: points to the PCIe device's info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) * Return: 0 if native SGL was built, 1 if no SGL was built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) struct _pcie_device *pcie_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) int sges_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* Get the SG list pointer and info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) sges_left = scsi_dma_map(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) if (sges_left < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) sdev_printk(KERN_ERR, scmd->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) "scsi_dma_map failed: request for %d bytes!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) scsi_bufflen(scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /* Check if we need to build a native SG list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) if (base_is_prp_possible(ioc, pcie_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) scmd, sges_left) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /* We built a native SG list, just return. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * Build native NVMe PRP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) base_make_prp_nvme(ioc, scmd, mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) smid, sges_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) scsi_dma_unmap(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * _base_add_sg_single_ieee - add sg element for IEEE format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * @paddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * @flags: SGE flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * @chain_offset: number of 128 byte elements from start of segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * @length: data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) Mpi25IeeeSgeChain64_t *sgel = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) sgel->Flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) sgel->NextChainOffset = chain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) sgel->Length = cpu_to_le32(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) sgel->Address = cpu_to_le64(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * @paddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * Create a zero length scatter gather entry to insure the IOCs hardware has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * something to use if the target device goes brain dead and tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * to send data even when none is asked for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * _base_build_sg_scmd - main sg creation routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * pcie_device is unused here!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) * @scmd: scsi command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) * @unused: unused pcie_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) * Context: none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) * The main routine that builds scatter gather table from a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * scsi request sent via the .queuecommand main handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) * Return: 0 success, anything else error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) Mpi2SCSIIORequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) dma_addr_t chain_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) struct scatterlist *sg_scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) void *sg_local, *chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) u32 chain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) u32 chain_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) u32 chain_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) int sges_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) u32 sges_in_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) u32 sgl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) u32 sgl_flags_last_element;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) u32 sgl_flags_end_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) struct chain_tracker *chain_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* init scatter gather flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (scmd->sc_data_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) sg_scmd = scsi_sglist(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) sges_left = scsi_dma_map(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (sges_left < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) sdev_printk(KERN_ERR, scmd->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) "scsi_dma_map failed: request for %d bytes!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) scsi_bufflen(scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) sg_local = &mpi_request->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) sges_in_segment = ioc->max_sges_in_main_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (sges_left <= sges_in_segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) goto fill_in_last_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) (sges_in_segment * ioc->sge_size))/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* fill in main message segment when there is a chain following */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) while (sges_in_segment) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (sges_in_segment == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ioc->base_add_sg_single(sg_local,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) sgl_flags_last_element | sg_dma_len(sg_scmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) ioc->base_add_sg_single(sg_local, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) sg_local += ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) sges_in_segment--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) /* initializing the chain flags and pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (!chain_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) chain = chain_req->chain_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) chain_dma = chain_req->chain_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) sges_in_segment = (sges_left <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ioc->max_sges_in_chain_message) ? sges_left :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ioc->max_sges_in_chain_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) chain_offset = (sges_left == sges_in_segment) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) 0 : (sges_in_segment * ioc->sge_size)/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) chain_length = sges_in_segment * ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (chain_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) chain_offset = chain_offset <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) MPI2_SGE_CHAIN_OFFSET_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) chain_length += ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) chain_length, chain_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) sg_local = chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (!chain_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) goto fill_in_last_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* fill in chain segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) while (sges_in_segment) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (sges_in_segment == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ioc->base_add_sg_single(sg_local,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) sgl_flags_last_element |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) sg_dma_len(sg_scmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ioc->base_add_sg_single(sg_local, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) sg_dma_len(sg_scmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) sg_local += ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) sges_in_segment--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (!chain_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) chain = chain_req->chain_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) chain_dma = chain_req->chain_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) fill_in_last_segment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) /* fill the last segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) while (sges_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (sges_left == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ioc->base_add_sg_single(sg_local, sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) sg_local += ioc->sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) * @scmd: scsi command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) * constructed on need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) * Context: none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) * The main routine that builds scatter gather table from a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * scsi request sent via the .queuecommand main handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) * Return: 0 success, anything else error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) Mpi25SCSIIORequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) dma_addr_t chain_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) struct scatterlist *sg_scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) void *sg_local, *chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) u32 chain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) u32 chain_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) int sges_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) u32 sges_in_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) u8 simple_sgl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) u8 simple_sgl_flags_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) u8 chain_sgl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) struct chain_tracker *chain_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* init scatter gather flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) simple_sgl_flags_last = simple_sgl_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /* Check if we need to build a native SG list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) smid, scmd, pcie_device) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /* We built a native SG list, just return. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) sg_scmd = scsi_sglist(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) sges_left = scsi_dma_map(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (sges_left < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) sdev_printk(KERN_ERR, scmd->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) "scsi_dma_map failed: request for %d bytes!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) scsi_bufflen(scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) sg_local = &mpi_request->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) sges_in_segment = (ioc->request_sz -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) if (sges_left <= sges_in_segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) goto fill_in_last_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* fill in main message segment when there is a chain following */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) while (sges_in_segment > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) sg_local += ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) sges_in_segment--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) /* initializing the pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) if (!chain_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) chain = chain_req->chain_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) chain_dma = chain_req->chain_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) sges_in_segment = (sges_left <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ioc->max_sges_in_chain_message) ? sges_left :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) ioc->max_sges_in_chain_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) chain_offset = (sges_left == sges_in_segment) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) 0 : sges_in_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) chain_length = sges_in_segment * ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (chain_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) chain_length += ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) chain_offset, chain_length, chain_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) sg_local = chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (!chain_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) goto fill_in_last_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) /* fill in chain segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) while (sges_in_segment) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) sg_local += ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) sges_in_segment--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (!chain_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) chain = chain_req->chain_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) chain_dma = chain_req->chain_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) fill_in_last_segment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) /* fill the last segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) while (sges_left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (sges_left == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) _base_add_sg_single_ieee(sg_local,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) sg_scmd = sg_next(sg_scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) sg_local += ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) sges_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) * _base_build_sg_ieee - build generic sg for IEEE format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) * @psge: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) * @data_out_dma: physical address for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) * @data_out_sz: data xfer size for WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) * @data_in_dma: physical address for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) * @data_in_sz: data xfer size for READS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) size_t data_in_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) u8 sgl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) if (!data_out_sz && !data_in_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) _base_build_zero_len_sge_ieee(ioc, psge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (data_out_sz && data_in_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* WRITE sgel first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) data_out_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) /* incr sgel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) psge += ioc->sge_size_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) /* READ sgel last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) data_in_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) } else if (data_out_sz) /* WRITE */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) data_out_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) } else if (data_in_sz) /* READ */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) data_in_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) * _base_config_dma_addressing - set dma addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * @pdev: PCI device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) struct sysinfo s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) int dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if (ioc->is_mcpu_endpoint ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) dma_get_required_mask(&pdev->dev) <= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dma_mask = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) dma_mask = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) dma_mask = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) if (dma_mask > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) ioc->base_add_sg_single = &_base_add_sg_single_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) ioc->sge_size = sizeof(Mpi2SGESimple64_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) ioc->base_add_sg_single = &_base_add_sg_single_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ioc->sge_size = sizeof(Mpi2SGESimple32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) si_meminfo(&s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dma_mask, convert_to_kb(s.totalram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) * _base_check_enable_msix - checks MSIX capabable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) * Check to see if card is capable of MSIX, and set number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) * of available msix vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) u16 message_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /* Check whether controller SAS2008 B0 controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /* get msix vector count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) /* NUMA_IO not supported for older controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) ioc->msix_vector_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) pci_read_config_word(ioc->pdev, base + 2, &message_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) ioc->msix_vector_count = (message_control & 0x3FF) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) ioc->msix_vector_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) * _base_free_irq - free irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) * Freeing respective reply_queue from the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) struct adapter_reply_queue *reply_q, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) if (list_empty(&ioc->reply_queue_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) list_del(&reply_q->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) if (ioc->smp_affinity_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) reply_q->msix_index), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) kfree(reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) * _base_request_irq - request irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) * @index: msix index into vector table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) * Inserting respective reply_queue into the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) struct pci_dev *pdev = ioc->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) if (!reply_q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ioc_err(ioc, "unable to allocate memory %zu!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) sizeof(struct adapter_reply_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) reply_q->ioc = ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) reply_q->msix_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) atomic_set(&reply_q->busy, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) if (ioc->msix_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) ioc->driver_name, ioc->id, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) ioc->driver_name, ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) IRQF_SHARED, reply_q->name, reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) pr_err("%s: unable to allocate interrupt %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) reply_q->name, pci_irq_vector(pdev, index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) kfree(reply_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) INIT_LIST_HEAD(&reply_q->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) list_add_tail(&reply_q->list, &ioc->reply_queue_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) * _base_assign_reply_queues - assigning msix index for each cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) * It would nice if we could call irq_set_affinity, however it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) * an exported symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) unsigned int cpu, nr_cpus, nr_msix, index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) int local_numa_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) if (!_base_is_controller_msix_enabled(ioc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) if (ioc->msix_load_balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) nr_cpus = num_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) ioc->facts.MaxMSIxVectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (!nr_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) if (ioc->smp_affinity_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) * set irq affinity to local numa node for those irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) * corresponding to high iops queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (ioc->high_iops_queues) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) local_numa_node = dev_to_node(&ioc->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) for (index = 0; index < ioc->high_iops_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) index), cpumask_of_node(local_numa_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) const cpumask_t *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) if (reply_q->msix_index < ioc->high_iops_queues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) mask = pci_irq_get_affinity(ioc->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) reply_q->msix_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) if (!mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) ioc_warn(ioc, "no affinity for msi %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) reply_q->msix_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) goto fall_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) for_each_cpu_and(cpu, mask, cpu_online_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) if (cpu >= ioc->cpu_msix_table_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) ioc->cpu_msix_table[cpu] = reply_q->msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) fall_back:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) cpu = cpumask_first(cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) nr_msix -= ioc->high_iops_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) unsigned int i, group = nr_cpus / nr_msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (reply_q->msix_index < ioc->high_iops_queues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (cpu >= nr_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if (index < nr_cpus % nr_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) group++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) for (i = 0 ; i < group ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) ioc->cpu_msix_table[cpu] = reply_q->msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) cpu = cpumask_next(cpu, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) * _base_check_and_enable_high_iops_queues - enable high iops mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) * @hba_msix_vector_count: msix vectors supported by HBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) * Enable high iops queues only if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) * - HBA is a SEA/AERO controller and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) * - MSI-Xs vector supported by the HBA is 128 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) * - total CPU count in the system >=16 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * - loaded driver with default max_msix_vectors module parameter and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * - system booted in non kdump mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * returns nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) int hba_msix_vector_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) u16 lnksta, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (perf_mode == MPT_PERF_MODE_IOPS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) perf_mode == MPT_PERF_MODE_LATENCY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) ioc->high_iops_queues = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) if (perf_mode == MPT_PERF_MODE_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) speed = lnksta & PCI_EXP_LNKSTA_CLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (speed < 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) ioc->high_iops_queues = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (!reset_devices && ioc->is_aero_ioc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) max_msix_vectors == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) ioc->high_iops_queues = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) * _base_disable_msix - disables msix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) if (!ioc->msix_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) pci_free_irq_vectors(ioc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) ioc->msix_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * _base_alloc_irq_vectors - allocate msix vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) int i, irq_flags = PCI_IRQ_MSIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) struct irq_affinity *descp = &desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (ioc->smp_affinity_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) irq_flags |= PCI_IRQ_AFFINITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) descp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ioc_info(ioc, " %d %d\n", ioc->high_iops_queues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ioc->reply_queue_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) i = pci_alloc_irq_vectors_affinity(ioc->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) ioc->high_iops_queues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) ioc->reply_queue_count, irq_flags, descp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) * _base_enable_msix - enables msix, failback to io_apic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) int i, local_max_msix_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) u8 try_msix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) ioc->msix_load_balance = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) if (msix_disable == -1 || msix_disable == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) try_msix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) if (!try_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) goto try_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) if (_base_check_enable_msix(ioc) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) goto try_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) ioc->cpu_count, max_msix_vectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) if (ioc->is_aero_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) _base_check_and_enable_high_iops_queues(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) ioc->msix_vector_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) ioc->reply_queue_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) min_t(int, ioc->cpu_count + ioc->high_iops_queues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) ioc->msix_vector_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) local_max_msix_vectors = (reset_devices) ? 1 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) local_max_msix_vectors = max_msix_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) if (local_max_msix_vectors > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) ioc->reply_queue_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) else if (local_max_msix_vectors == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) goto try_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) * Enable msix_load_balance only if combined reply queue mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) * disabled on SAS3 & above generation HBA devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) if (!ioc->combined_reply_queue &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) ioc->hba_mpi_version_belonged != MPI2_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) "combined ReplyQueue is off, Enabling msix load balance\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) ioc->msix_load_balance = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) * smp affinity setting is not need when msix load balance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) * is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) if (ioc->msix_load_balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) ioc->smp_affinity_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) r = _base_alloc_irq_vectors(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) goto try_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) ioc->msix_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) ioc->reply_queue_count = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) for (i = 0; i < ioc->reply_queue_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) r = _base_request_irq(ioc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) _base_free_irq(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) _base_disable_msix(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) goto try_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) ioc_info(ioc, "High IOPs queues : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) ioc->high_iops_queues ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* failback to io_apic interrupt routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) try_ioapic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) ioc->high_iops_queues = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) ioc_info(ioc, "High IOPs queues : disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) ioc->reply_queue_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) dfailprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) r = _base_request_irq(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) * mpt3sas_base_unmap_resources - free controller resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) struct pci_dev *pdev = ioc->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) _base_free_irq(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) _base_disable_msix(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) kfree(ioc->replyPostRegisterIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) ioc->replyPostRegisterIndex = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (ioc->chip_phys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) iounmap(ioc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ioc->chip_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) if (pci_is_enabled(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) pci_release_selected_regions(ioc->pdev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) pci_disable_pcie_error_reporting(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) * _base_check_for_fault_and_issue_reset - check if IOC is in fault state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) * and if it is in fault state then issue diag reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) * Returns: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) _base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) int rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) dinitprintk(ioc, pr_info("%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if (ioc->pci_error_recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) mpt3sas_print_fault_code(ioc, ioc_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) rc = _base_diag_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) mpt3sas_print_coredump_info(ioc, ioc_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) rc = _base_diag_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) struct pci_dev *pdev = ioc->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) u32 memap_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) u32 pio_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) int i, r = 0, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) u64 pio_chip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) phys_addr_t chip_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) if (pci_enable_device_mem(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) ioc_warn(ioc, "pci_enable_device_mem: failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) ioc->bars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (pci_request_selected_regions(pdev, ioc->bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) ioc->driver_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) ioc_warn(ioc, "pci_request_selected_regions: failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) ioc->bars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* AER (Advanced Error Reporting) hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) pci_enable_pcie_error_reporting(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) if (_base_config_dma_addressing(ioc, pdev) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) (!memap_sz || !pio_sz); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) if (pio_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) pio_chip = (u64)pci_resource_start(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) pio_sz = pci_resource_len(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) if (memap_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) ioc->chip_phys = pci_resource_start(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) chip_phys = ioc->chip_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) memap_sz = pci_resource_len(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) ioc->chip = ioremap(ioc->chip_phys, memap_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) if (ioc->chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) ioc_err(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) "unable to map adapter memory! or resource not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) mpt3sas_base_mask_interrupts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) r = _base_get_ioc_facts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) rc = _base_check_for_fault_and_issue_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (rc || (_base_get_ioc_facts(ioc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if (!ioc->rdpq_array_enable_assigned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) ioc->rdpq_array_enable = ioc->rdpq_array_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) ioc->rdpq_array_enable_assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) r = _base_enable_msix(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) if (!ioc->is_driver_loading)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) _base_init_irqpolls(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) /* Use the Combined reply queue feature only for SAS3 C0 & higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) * revision HBAs and also only when reply queue count is greater than 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (ioc->combined_reply_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* Determine the Supplemental Reply Post Host Index Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) * Addresse. Supplemental Reply Post Host Index Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) * each register is at offset bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) ioc->replyPostRegisterIndex = kcalloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) ioc->combined_reply_index_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) sizeof(resource_size_t *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) if (!ioc->replyPostRegisterIndex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) ioc_err(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) "allocation for replyPostRegisterIndex failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) for (i = 0; i < ioc->combined_reply_index_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) ioc->replyPostRegisterIndex[i] = (resource_size_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) ((u8 __force *)&ioc->chip->Doorbell +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) if (ioc->is_warpdrive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) &ioc->chip->ReplyPostHostIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) for (i = 1; i < ioc->cpu_msix_table_sz; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) ioc->reply_post_host_index[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) (resource_size_t __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) * 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) pr_info("%s: %s enabled: IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) reply_q->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) pci_irq_vector(ioc->pdev, reply_q->msix_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) &chip_phys, ioc->chip, memap_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) (unsigned long long)pio_chip, pio_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) /* Save PCI configuration state for recovery from PCI AER/EEH errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) out_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) mpt3sas_base_unmap_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) * mpt3sas_base_get_msg_frame - obtain request mf pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) * @smid: system request message index(smid zero is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) * Return: virt pointer to message frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) return (void *)(ioc->request + (smid * ioc->request_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) * Return: virt pointer to sense buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * Return: phys pointer to the low 32bit address of the sense buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) __le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) SCSI_SENSE_BUFFERSIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) * Return: virt pointer to a PCIe SGL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) * Return: phys pointer to the address of the PCIe buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) * @phys_addr: lower 32 physical addr of the reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) * Converts 32bit lower physical addr into a virt address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) if (!phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) * _base_get_msix_index - get the msix index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) * @scmd: scsi_cmnd object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) * returns msix index of general reply queues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) * i.e. reply queue on which IO request's reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) * should be posted by the HBA firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) struct scsi_cmnd *scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) /* Enables reply_queue load balancing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (ioc->msix_load_balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) return ioc->reply_queue_count ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) base_mod64(atomic64_add_return(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) return ioc->cpu_msix_table[raw_smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * _base_sdev_nr_inflight_request -get number of inflight requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) * of a request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) * @q: request_queue object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) * returns number of inflight request of a request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) _base_sdev_nr_inflight_request(struct request_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) struct blk_mq_hw_ctx *hctx = q->queue_hw_ctx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) return atomic_read(&hctx->nr_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) * _base_get_high_iops_msix_index - get the msix index of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) * high iops queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) * @scmd: scsi_cmnd object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) * Returns: msix index of high iops reply queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) * i.e. high iops reply queue on which IO request's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) * reply should be posted by the HBA firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) struct scsi_cmnd *scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) * Round robin the IO interrupts among the high iops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) * reply queues in terms of batch count 16 when outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) * IOs on the target device is >=8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) if (_base_sdev_nr_inflight_request(scmd->device->request_queue) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) return base_mod64((
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) atomic64_add_return(1, &ioc->high_iops_outstanding) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) MPT3SAS_HIGH_IOPS_BATCH_COUNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) return _base_get_msix_index(ioc, scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) * mpt3sas_base_get_smid - obtain a free smid from internal queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) * @cb_idx: callback index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) * Return: smid (zero is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) struct request_tracker *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) if (list_empty(&ioc->internal_free_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) ioc_err(ioc, "%s: smid not available\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) request = list_entry(ioc->internal_free_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) struct request_tracker, tracker_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) request->cb_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) smid = request->smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) list_del(&request->tracker_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) return smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) * @cb_idx: callback index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) * @scmd: pointer to scsi command object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) * Return: smid (zero is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) struct scsi_cmnd *scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) struct scsiio_tracker *request = scsi_cmd_priv(scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) unsigned int tag = scmd->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) smid = tag + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) request->cb_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) request->smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) request->scmd = scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) INIT_LIST_HEAD(&request->chain_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) return smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * @cb_idx: callback index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) * Return: smid (zero is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) struct request_tracker *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) if (list_empty(&ioc->hpr_free_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) request = list_entry(ioc->hpr_free_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) struct request_tracker, tracker_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) request->cb_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) smid = request->smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) list_del(&request->tracker_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) return smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) * See _wait_for_commands_to_complete() call with regards to this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) if (ioc->shost_recovery && ioc->pending_io_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) ioc->pending_io_count = scsi_host_busy(ioc->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) if (ioc->pending_io_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) wake_up(&ioc->reset_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) struct scsiio_tracker *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) if (WARN_ON(st->smid == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) st->cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) st->direct_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) st->scmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) st->smid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) * mpt3sas_base_free_smid - put smid back on free_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) if (smid < ioc->hi_priority_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) struct scsiio_tracker *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) void *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) st = _get_st_from_smid(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) if (!st) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) _base_recovery_check(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) /* Clear MPI request frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) memset(request, 0, ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) mpt3sas_base_clear_st(ioc, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) _base_recovery_check(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) if (smid < ioc->internal_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) /* hi-priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) i = smid - ioc->hi_priority_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) ioc->hpr_lookup[i].cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) } else if (smid <= ioc->hba_queue_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) /* internal queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) i = smid - ioc->internal_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) ioc->internal_lookup[i].cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) list_add(&ioc->internal_lookup[i].tracker_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) &ioc->internal_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) * _base_mpi_ep_writeq - 32 bit write to MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) * @b: data payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) * @addr: address in MMIO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) * @writeq_lock: spin lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) * This special handling for MPI EP to take care of 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) * environment where its not quarenteed to send the entire word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) * in one transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) spinlock_t *writeq_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) spin_lock_irqsave(writeq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) __raw_writel((u32)(b), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) __raw_writel((u32)(b >> 32), (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) spin_unlock_irqrestore(writeq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) * _base_writeq - 64 bit write to MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) * @b: data payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) * @addr: address in MMIO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) * @writeq_lock: spin lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) * care of 32 bit environment where its not quarenteed to send the entire word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) * in one transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) #if defined(writeq) && defined(CONFIG_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) __raw_writeq(b, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) _base_mpi_ep_writeq(b, addr, writeq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) * _base_set_and_get_msix_index - get the msix index and assign to msix_io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) * variable of scsi tracker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) * returns msix index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) struct scsiio_tracker *st = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) if (smid < ioc->hi_priority_smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) st = _get_st_from_smid(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) if (st == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) return _base_get_msix_index(ioc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) return st->msix_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) * @handle: device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) u16 smid, u16 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) u64 *request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) void *mpi_req_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) _clone_sg_entries(ioc, (void *) mfp, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) mpi_req_iomem = (void __force *)ioc->chip +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) descriptor.SCSIIO.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) descriptor.SCSIIO.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) * _base_put_smid_scsi_io - send SCSI_IO request to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) * @handle: device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) u64 *request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) descriptor.SCSIIO.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) descriptor.SCSIIO.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) * _base_put_smid_fast_path - send fast path request to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) * @handle: device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) u16 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) u64 *request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) descriptor.SCSIIO.RequestFlags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) descriptor.SCSIIO.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) descriptor.SCSIIO.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) * _base_put_smid_hi_priority - send Task Management request to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) u16 msix_task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) void *mpi_req_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) u64 *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) if (ioc->is_mcpu_endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) /* TBD 256 is offset within sys register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) mpi_req_iomem = (void __force *)ioc->chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) + MPI_FRAME_START_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) + (smid * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) descriptor.HighPriority.RequestFlags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) descriptor.HighPriority.MSIxIndex = msix_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) descriptor.HighPriority.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) descriptor.HighPriority.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) descriptor.HighPriority.Reserved1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) _base_mpi_ep_writeq(*request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) * firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) u64 *request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) descriptor.Default.RequestFlags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) descriptor.Default.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) descriptor.Default.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) descriptor.Default.DescriptorTypeDependent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) * _base_put_smid_default - Default, primarily used for config pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) Mpi2RequestDescriptorUnion_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) void *mpi_req_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) u64 *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) if (ioc->is_mcpu_endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) _clone_sg_entries(ioc, (void *) mfp, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) /* TBD 256 is offset within sys register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) mpi_req_iomem = (void __force *)ioc->chip +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) request = (u64 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) descriptor.Default.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) descriptor.Default.LMID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) descriptor.Default.DescriptorTypeDependent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) _base_mpi_ep_writeq(*request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) &ioc->scsi_lookup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) * Atomic Request Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) * @handle: device handle, unused in this function, for function type match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) * Return nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) u16 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) Mpi26AtomicRequestDescriptor_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) u32 *request = (u32 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) descriptor.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) * _base_put_smid_fast_path_atomic - send fast path request to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) * using Atomic Request Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) * @handle: device handle, unused in this function, for function type match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) * Return nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) u16 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) Mpi26AtomicRequestDescriptor_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) u32 *request = (u32 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) descriptor.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) * _base_put_smid_hi_priority_atomic - send Task Management request to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) * firmware using Atomic Request Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) * Return nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) u16 msix_task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) Mpi26AtomicRequestDescriptor_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) u32 *request = (u32 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) descriptor.MSIxIndex = msix_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) descriptor.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) * _base_put_smid_default - Default, primarily used for config pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) * use Atomic Request Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) * Return nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) Mpi26AtomicRequestDescriptor_t descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) u32 *request = (u32 *)&descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) descriptor.SMID = cpu_to_le16(smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) * _base_display_OEMs_branding - Display branding string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) switch (ioc->pdev->subsystem_vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) case PCI_VENDOR_ID_INTEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) switch (ioc->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) case MPI2_MFGPAGE_DEVID_SAS2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) case MPT2SAS_INTEL_RMS2LL080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) MPT2SAS_INTEL_RMS2LL080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) case MPT2SAS_INTEL_RMS2LL040_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) MPT2SAS_INTEL_RMS2LL040_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) case MPT2SAS_INTEL_SSD910_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) MPT2SAS_INTEL_SSD910_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) case MPI2_MFGPAGE_DEVID_SAS2308_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) case MPT2SAS_INTEL_RS25GB008_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) MPT2SAS_INTEL_RS25GB008_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) case MPT2SAS_INTEL_RMS25JB080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) MPT2SAS_INTEL_RMS25JB080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) case MPT2SAS_INTEL_RMS25JB040_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) MPT2SAS_INTEL_RMS25JB040_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) case MPT2SAS_INTEL_RMS25KB080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) MPT2SAS_INTEL_RMS25KB080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) case MPT2SAS_INTEL_RMS25KB040_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) MPT2SAS_INTEL_RMS25KB040_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) case MPT2SAS_INTEL_RMS25LB040_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) MPT2SAS_INTEL_RMS25LB040_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) case MPT2SAS_INTEL_RMS25LB080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) MPT2SAS_INTEL_RMS25LB080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) case MPI25_MFGPAGE_DEVID_SAS3008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) case MPT3SAS_INTEL_RMS3JC080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) MPT3SAS_INTEL_RMS3JC080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) case MPT3SAS_INTEL_RS3GC008_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) MPT3SAS_INTEL_RS3GC008_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) case MPT3SAS_INTEL_RS3FC044_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) MPT3SAS_INTEL_RS3FC044_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) case MPT3SAS_INTEL_RS3UC080_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) MPT3SAS_INTEL_RS3UC080_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) case PCI_VENDOR_ID_DELL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) switch (ioc->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) case MPI2_MFGPAGE_DEVID_SAS2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) case MPT2SAS_DELL_PERC_H200_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) MPT2SAS_DELL_PERC_H200_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) case MPT2SAS_DELL_6GBPS_SAS_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) MPT2SAS_DELL_6GBPS_SAS_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) case MPI25_MFGPAGE_DEVID_SAS3008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) case MPT3SAS_DELL_12G_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) MPT3SAS_DELL_12G_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) case PCI_VENDOR_ID_CISCO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) switch (ioc->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) case MPI25_MFGPAGE_DEVID_SAS3008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) case MPI25_MFGPAGE_DEVID_SAS3108_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) case MPT2SAS_HP_3PAR_SSVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) switch (ioc->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) case MPI2_MFGPAGE_DEVID_SAS2004:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) case MPI2_MFGPAGE_DEVID_SAS2308_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) switch (ioc->pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) case MPT2SAS_HP_2_4_INTERNAL_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) MPT2SAS_HP_2_4_INTERNAL_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) ioc_info(ioc, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) ioc->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) * version from FW Image Header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) Mpi2FWImageHeader_t *fw_img_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) Mpi26ComponentImageHeader_t *cmp_img_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) Mpi25FWUploadRequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) Mpi2FWUploadReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) u32 package_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) void *fwpkg_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) dma_addr_t fwpkg_data_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) u16 smid, ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) size_t data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) ioc_err(ioc, "%s: internal command already in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) data_length = sizeof(Mpi2FWImageHeader_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) &fwpkg_data_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) if (!fwpkg_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) ioc_err(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) __FILE__, __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) r = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) ioc->base_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) ioc->base_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) mpi_request->ImageSize = cpu_to_le32(data_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) data_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) init_completion(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) /* Wait for 15 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) wait_for_completion_timeout(&ioc->base_cmds.done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) FW_IMG_HDR_READ_TIMEOUT*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) ioc_info(ioc, "%s: complete\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) ioc_err(ioc, "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) _debug_dump_mf(mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) sizeof(Mpi25FWUploadRequest_t)/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) r = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) memcpy(&mpi_reply, ioc->base_cmds.reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) sizeof(Mpi2FWUploadReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) if (le32_to_cpu(fw_img_hdr->Signature) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) cmp_img_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) (Mpi26ComponentImageHeader_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) (fwpkg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) package_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) le32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) cmp_img_hdr->ApplicationSpecific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) package_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) le32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) fw_img_hdr->PackageVersion.Word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) if (package_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) "FW Package Ver(%02d.%02d.%02d.%02d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) ((package_version) & 0xFF000000) >> 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) ((package_version) & 0x00FF0000) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) ((package_version) & 0x0000FF00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) (package_version) & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) _debug_dump_mf(&mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) sizeof(Mpi2FWUploadReply_t)/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) if (fwpkg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) fwpkg_data_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) * _base_display_ioc_capabilities - Disply IOC's capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) char desc[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) u32 iounit_pg1_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) u32 bios_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) strncpy(desc, ioc->manu_pg0.ChipName, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) ioc->facts.FWVersion.Word & 0x000000FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) ioc->pdev->revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) (bios_version & 0xFF000000) >> 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) (bios_version & 0x00FF0000) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) (bios_version & 0x0000FF00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) bios_version & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) _base_display_OEMs_branding(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) pr_info("%sNVMe", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) ioc_info(ioc, "Protocol=(");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) pr_cont("Initiator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) pr_cont("%sTarget", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) pr_cont("), Capabilities=(");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) if (!ioc->hide_ir_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) pr_cont("Raid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) pr_cont("%sTLR", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) pr_cont("%sMulticast", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) pr_cont("%sBIDI Target", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) pr_cont("%sEEDP", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) pr_cont("%sSnapshot Buffer", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) pr_cont("%sDiag Trace Buffer", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) pr_cont("%sDiag Extended Buffer", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) if (ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) pr_cont("%sTask Set Full", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) pr_cont("%sNCQ", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) pr_cont(")\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) * mpt3sas_base_update_missing_delay - change the missing delay timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) * @device_missing_delay: amount of time till device is reported missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) * @io_missing_delay: interval IO is returned when there is a missing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) * Passed on the command line, this function will modify the device missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) * delay, as well as the io missing delay. This should be called at driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) * load time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) u16 device_missing_delay, u8 io_missing_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) u16 dmd, dmd_new, dmd_orignal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) u8 io_missing_delay_original;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) u16 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) Mpi2ConfigReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) u8 num_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) u16 ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) if (!num_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) sizeof(Mpi2SasIOUnit1PhyData_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) if (!sas_iounit_pg1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) ioc_err(ioc, "failure at %s:%d/%s()!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) __FILE__, __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) sas_iounit_pg1, sz))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) ioc_err(ioc, "failure at %s:%d/%s()!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) __FILE__, __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) ioc_err(ioc, "failure at %s:%d/%s()!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) __FILE__, __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) /* device missing delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) dmd_orignal = dmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) if (device_missing_delay > 0x7F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) device_missing_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) dmd = dmd / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) dmd = device_missing_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) /* io missing delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) sz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) dmd_new = (dmd &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) dmd_new =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) dmd_orignal, dmd_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) io_missing_delay_original,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) io_missing_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) ioc->device_missing_delay = dmd_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) ioc->io_missing_delay = io_missing_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) kfree(sas_iounit_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) * according to performance mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) * @ioc : per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) * Return nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) Mpi2IOCPage1_t ioc_pg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) Mpi2ConfigReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) switch (perf_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) case MPT_PERF_MODE_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) case MPT_PERF_MODE_BALANCED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) if (ioc->high_iops_queues) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) "Enable interrupt coalescing only for first\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) "%d reply queues\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) * If 31st bit is zero then interrupt coalescing is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) * enabled for all reply descriptor post queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) * If 31st bit is set to one then user can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) * enable/disable interrupt coalescing on per reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) * descriptor post queue group(8) basis. So to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) * interrupt coalescing only on first reply descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * post queue group 31st bit and zero th bit is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) ioc_info(ioc, "performance mode: balanced\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) case MPT_PERF_MODE_LATENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) * Enable interrupt coalescing on all reply queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) * with timeout value 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) ioc_pg1.ProductSpecific = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) ioc_info(ioc, "performance mode: latency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) case MPT_PERF_MODE_IOPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) * Enable interrupt coalescing on all reply queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) "performance mode: iops with coalescing timeout: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) le32_to_cpu(ioc_pg1.CoalescingTimeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) ioc_pg1.ProductSpecific = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) * _base_static_config_pages - static start of day config pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) Mpi2ConfigReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) u32 iounit_pg1_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) ioc->nvme_abort_timeout = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) if (ioc->ir_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) &ioc->manu_pg10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) * Ensure correct T10 PI operation if vendor left EEDPTagMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) * flag unset in NVDATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) ioc->manu_pg11.EEDPTagMode &= ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) ioc->manu_pg11.EEDPTagMode |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) &ioc->manu_pg11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) ioc->tm_custom_handling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) ioc->tm_custom_handling = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) else if (ioc->manu_pg11.NVMeAbortTO >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) NVME_TASK_ABORT_MAX_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) _base_display_ioc_capabilities(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) * Enable task_set_full handling in iounit_pg1 when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) * facts capabilities indicate that its supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) if ((ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) iounit_pg1_flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) iounit_pg1_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) if (ioc->iounit_pg8.NumSensors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) if (ioc->is_aero_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) _base_update_ioc_page1_inlinewith_perf_mode(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) * mpt3sas_free_enclosure_list - release memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) * Free memory allocated during encloure add.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) /* Free enclosure list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) list_for_each_entry_safe(enclosure_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) enclosure_dev_next, &ioc->enclosure_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) list_del(&enclosure_dev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) kfree(enclosure_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) * _base_release_memory_pools - release memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) * Free memory allocated from _base_allocate_memory_pools.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) int j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) int dma_alloc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) struct chain_tracker *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) if (ioc->request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) ioc->request, ioc->request_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) dexitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) ioc_info(ioc, "request_pool(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) ioc->request));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) ioc->request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) if (ioc->sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) dma_pool_destroy(ioc->sense_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) dexitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) ioc_info(ioc, "sense_pool(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) ioc->sense));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) ioc->sense = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) if (ioc->reply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) dma_pool_destroy(ioc->reply_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) dexitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) ioc_info(ioc, "reply_pool(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) ioc->reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) ioc->reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) if (ioc->reply_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) ioc->reply_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) dma_pool_destroy(ioc->reply_free_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) dexitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) ioc_info(ioc, "reply_free_pool(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) ioc->reply_free));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) ioc->reply_free = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) if (ioc->reply_post) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) dma_alloc_count = DIV_ROUND_UP(count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) RDPQ_MAX_INDEX_IN_ONE_CHUNK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) && dma_alloc_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) if (ioc->reply_post[i].reply_post_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) dma_pool_free(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) ioc->reply_post_free_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) ioc->reply_post[i].reply_post_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) ioc->reply_post[i].reply_post_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) dexitprintk(ioc, ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) "reply_post_free_pool(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) ioc->reply_post[i].reply_post_free));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) ioc->reply_post[i].reply_post_free =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) --dma_alloc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) dma_pool_destroy(ioc->reply_post_free_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) if (ioc->reply_post_free_array &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) ioc->rdpq_array_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) dma_pool_free(ioc->reply_post_free_array_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) ioc->reply_post_free_array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) ioc->reply_post_free_array_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) ioc->reply_post_free_array = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) kfree(ioc->reply_post);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) if (ioc->pcie_sgl_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) for (i = 0; i < ioc->scsiio_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) dma_pool_free(ioc->pcie_sgl_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) ioc->pcie_sg_lookup[i].pcie_sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) ioc->pcie_sg_lookup[i].pcie_sgl_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) dma_pool_destroy(ioc->pcie_sgl_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) if (ioc->config_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) dexitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) ioc_info(ioc, "config_page(0x%p): free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) ioc->config_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) ioc->config_page, ioc->config_page_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) kfree(ioc->hpr_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) ioc->hpr_lookup = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) kfree(ioc->internal_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) ioc->internal_lookup = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) if (ioc->chain_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) for (i = 0; i < ioc->scsiio_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) for (j = ioc->chains_per_prp_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) j < ioc->chains_needed_per_io; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) ct = &ioc->chain_lookup[i].chains_per_smid[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) if (ct && ct->chain_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) dma_pool_free(ioc->chain_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) ct->chain_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) ct->chain_buffer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) kfree(ioc->chain_lookup[i].chains_per_smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) dma_pool_destroy(ioc->chain_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) kfree(ioc->chain_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) ioc->chain_lookup = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) * having same upper 32bits in their base memory address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) * @reply_pool_start_address: Base address of a reply queue set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) * @pool_sz: Size of single Reply Descriptor Post Queues pool size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) * Return: 1 if reply queues in a set have a same upper 32bits in their base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) * memory address, else 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) long reply_pool_end_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) reply_pool_end_address = reply_pool_start_address + pool_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) if (upper_32_bits(reply_pool_start_address) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) upper_32_bits(reply_pool_end_address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) * for reply queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) * @sz: DMA Pool size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) u32 dma_alloc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) int reply_post_free_sz = ioc->reply_post_queue_depth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) sizeof(Mpi2DefaultReplyDescriptor_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) if (!ioc->reply_post)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) * be within 4GB boundary i.e reply queues in a set must have same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) * upper 32-bits in their memory address. so here driver is allocating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) * the DMA'able memory for reply queues according.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) * Driver uses limitation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) * VENTURA_SERIES to manage INVADER_SERIES as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) dma_alloc_count = DIV_ROUND_UP(count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) RDPQ_MAX_INDEX_IN_ONE_CHUNK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) ioc->reply_post_free_dma_pool =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) dma_pool_create("reply_post_free pool",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) &ioc->pdev->dev, sz, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) if (!ioc->reply_post_free_dma_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) ioc->reply_post[i].reply_post_free =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) dma_pool_zalloc(ioc->reply_post_free_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) &ioc->reply_post[i].reply_post_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) if (!ioc->reply_post[i].reply_post_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) * Each set of RDPQ pool must satisfy 4gb boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) * restriction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) * 1) Check if allocated resources for RDPQ pool are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) * the same 4GB range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) * 2) If #1 is true, continue with 64 bit DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) * 3) If #1 is false, return 1. which means free all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) * resources and set DMA mask to 32 and allocate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) if (!mpt3sas_check_same_4gb_region(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) (long)ioc->reply_post[i].reply_post_free, sz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) ioc_err(ioc, "bad Replypost free pool(0x%p)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) "reply_post_free_dma = (0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) ioc->reply_post[i].reply_post_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) (unsigned long long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) ioc->reply_post[i].reply_post_free_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) dma_alloc_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) ioc->reply_post[i].reply_post_free =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) (Mpi2ReplyDescriptorsUnion_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) ((long)ioc->reply_post[i-1].reply_post_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) + reply_post_free_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) ioc->reply_post[i].reply_post_free_dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) (dma_addr_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) (ioc->reply_post[i-1].reply_post_free_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) reply_post_free_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) * _base_allocate_memory_pools - allocate start of day memory pools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) * Return: 0 success, anything else error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) struct mpt3sas_facts *facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) u16 max_sge_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) u16 chains_needed_per_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) u32 retry_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) u32 rdpq_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) u16 max_request_credit, nvme_blocks_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) unsigned short sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) u16 sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) struct chain_tracker *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) retry_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) facts = &ioc->facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) /* command line tunables for max sgl entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) if (max_sgl_entries != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) sg_tablesize = max_sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) sg_tablesize = MPT2SAS_SG_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) sg_tablesize = MPT3SAS_SG_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) if (reset_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) sg_tablesize = min_t(unsigned short, sg_tablesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) MPT_KDUMP_MIN_PHYS_SEGMENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) sg_tablesize = min_t(unsigned short, sg_tablesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) SG_MAX_SEGMENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) ioc->shost->sg_tablesize = sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) (facts->RequestCredit / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) INTERNAL_SCSIIO_CMDS_COUNT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) facts->RequestCredit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ioc->internal_depth = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) ioc->hi_priority_depth = ioc->internal_depth - (5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) /* command line tunables for max controller queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) if (max_queue_depth != -1 && max_queue_depth != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) max_request_credit = min_t(u16, max_queue_depth +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) ioc->internal_depth, facts->RequestCredit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) max_request_credit = MAX_HBA_QUEUE_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) } else if (reset_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) max_request_credit = min_t(u16, facts->RequestCredit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) max_request_credit = min_t(u16, facts->RequestCredit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) MAX_HBA_QUEUE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) /* Firmware maintains additional facts->HighPriorityCredit number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) * credits for HiPriprity Request messages, so hba queue depth will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) * sum of max_request_credit and high priority queue depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) /* request frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) ioc->request_sz = facts->IOCRequestFrameSize * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) /* reply frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) ioc->reply_sz = facts->ReplyFrameSize * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) /* chain segment size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) if (facts->IOCMaxChainSegmentSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) ioc->chain_segment_sz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) facts->IOCMaxChainSegmentSize *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) MAX_CHAIN_ELEMT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) MAX_CHAIN_ELEMT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) ioc->chain_segment_sz = ioc->request_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) /* calculate the max scatter element size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) retry_allocation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) total_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) /* calculate number of sg elements left over in the 1st frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) sizeof(Mpi2SGEIOUnion_t)) + sge_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) ioc->max_sges_in_main_message = max_sge_elements/sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) /* now do the same for a chain buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) max_sge_elements = ioc->chain_segment_sz - sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) chains_needed_per_io = ((ioc->shost->sg_tablesize -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) if (chains_needed_per_io > facts->MaxChainDepth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) chains_needed_per_io = facts->MaxChainDepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) ioc->shost->sg_tablesize = min_t(u16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) * chains_needed_per_io), ioc->shost->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) ioc->chains_needed_per_io = chains_needed_per_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) /* reply free queue sizing - taking into account for 64 FW events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) /* mCPU manage single counters for simplicity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) /* calculate reply descriptor post queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) ioc->reply_post_queue_depth = ioc->hba_queue_depth +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) ioc->reply_free_queue_depth + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) /* align the reply post queue on the next 16 count boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) if (ioc->reply_post_queue_depth % 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) ioc->reply_post_queue_depth += 16 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) (ioc->reply_post_queue_depth % 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) if (ioc->reply_post_queue_depth >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) facts->MaxReplyDescriptorPostQueueDepth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) ioc->reply_post_queue_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) facts->MaxReplyDescriptorPostQueueDepth -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) (facts->MaxReplyDescriptorPostQueueDepth % 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) ioc->hba_queue_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) ((ioc->reply_post_queue_depth - 64) / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) "sge_per_io(%d), chains_per_io(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) ioc->max_sges_in_main_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) ioc->max_sges_in_chain_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) ioc->shost->sg_tablesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) ioc->chains_needed_per_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) /* reply post queue, 16 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) reply_post_free_sz = ioc->reply_post_queue_depth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) sizeof(Mpi2DefaultReplyDescriptor_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) if (ret == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) * Free allocated bad RDPQ memory pools.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) * Change dma coherent mask to 32 bit and reallocate RDPQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) _base_release_memory_pools(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) ioc->use_32bit_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) ioc_err(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) "32 DMA mask failed %s\n", pci_name(ioc->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) } else if (ret == -ENOMEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) ioc->scsiio_depth = ioc->hba_queue_depth -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) ioc->hi_priority_depth - ioc->internal_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) /* set the scsi host can_queue depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) * with some internal commands that could be outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) ioc->shost->can_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) /* contiguous pool for request and chains, 16 byte align, one extra "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) * "frame for smid=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) /* hi-priority queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) sz += (ioc->hi_priority_depth * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) /* internal queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) sz += (ioc->internal_depth * ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) ioc->request_dma_sz = sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) &ioc->request_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) if (!ioc->request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) ioc->hba_queue_depth, ioc->chains_needed_per_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) ioc->request_sz, sz / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) retry_sz = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) ioc->hba_queue_depth -= retry_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) _base_release_memory_pools(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) goto retry_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) if (retry_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) ioc->hba_queue_depth, ioc->chains_needed_per_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) ioc->request_sz, sz / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) /* hi-priority queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) /* internal queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) "request pool(0x%p) - dma(0x%llx): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) "depth(%d), frame_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) ioc->request, (unsigned long long) ioc->request_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) ioc->hba_queue_depth, ioc->request_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) (ioc->hba_queue_depth * ioc->request_sz) / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) total_sz += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) ioc->request, ioc->scsiio_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) if (!ioc->chain_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) for (i = 0; i < ioc->scsiio_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) if (!ioc->chain_lookup[i].chains_per_smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) ioc_err(ioc, "chain_lookup: kzalloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) /* initialize hi-priority queue smid's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) sizeof(struct request_tracker), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) if (!ioc->hpr_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) ioc->hi_priority_smid = ioc->scsiio_depth + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) ioc->hi_priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) ioc->hi_priority_depth, ioc->hi_priority_smid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) /* initialize internal queue smid's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) ioc->internal_lookup = kcalloc(ioc->internal_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) sizeof(struct request_tracker), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) if (!ioc->internal_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) ioc_err(ioc, "internal_lookup: kcalloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) ioc->internal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) ioc->internal_depth, ioc->internal_smid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) * The number of NVMe page sized blocks needed is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) * that is placed in the main message frame. 8 is the size of each PRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) * entry or PRP list pointer entry. 8 is subtracted from page_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) * because of the PRP list pointer entry at the end of a page, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) * is not counted as a PRP entry. The 1 added page is a round up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) * To avoid allocation failures due to the amount of memory that could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) * be required for NVMe PRP's, only each set of NVMe blocks will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) * contiguous, so a new set is allocated for each possible I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) ioc->chains_per_prp_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) nvme_blocks_needed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) nvme_blocks_needed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) if (!ioc->pcie_sg_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) sz = nvme_blocks_needed * ioc->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) ioc->pcie_sgl_dma_pool =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) if (!ioc->pcie_sgl_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) ioc_info(ioc, "PCIe SGL pool: dma_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) ioc->chains_needed_per_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) for (i = 0; i < ioc->scsiio_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) ioc->pcie_sgl_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) ioc_info(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) ct = &ioc->chain_lookup[i].chains_per_smid[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) ct->chain_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) ioc->pcie_sg_lookup[i].pcie_sgl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) (j * ioc->chain_segment_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) ct->chain_buffer_dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) ioc->pcie_sg_lookup[i].pcie_sgl_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) (j * ioc->chain_segment_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) ioc_info(ioc, "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) ioc->scsiio_depth, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) (sz * ioc->scsiio_depth) / 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) ioc_info(ioc, "Number of chains can fit in a PRP page(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) ioc->chains_per_prp_buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) total_sz += sz * ioc->scsiio_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) ioc->chain_segment_sz, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) if (!ioc->chain_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) ioc_err(ioc, "chain_dma_pool: dma_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) for (i = 0; i < ioc->scsiio_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) for (j = ioc->chains_per_prp_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) j < ioc->chains_needed_per_io; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) ct = &ioc->chain_lookup[i].chains_per_smid[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) ct->chain_buffer = dma_pool_alloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) ioc->chain_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) &ct->chain_buffer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) if (!ct->chain_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) ioc_err(ioc, "chain_lookup: pci_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) total_sz += ioc->chain_segment_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) ioc->chain_depth, ioc->chain_segment_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) /* sense buffers, 4 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) if (!ioc->sense_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) ioc_err(ioc, "sense pool: dma_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) &ioc->sense_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) if (!ioc->sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) ioc_err(ioc, "sense pool: dma_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) /* sense buffer requires to be in same 4 gb region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) * Below function will check the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) * In case of failure, new pci pool will be created with updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) * alignment. Older allocation and pool will be destroyed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) * Alignment will be used such a way that next allocation if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) * success, will always meet same 4gb region requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) * Actual requirement is not alignment, but we need start and end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) * DMA address must have same upper 32 bit address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) //Release Sense pool & Reallocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) dma_pool_destroy(ioc->sense_dma_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) ioc->sense = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) ioc->sense_dma_pool =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) dma_pool_create("sense pool", &ioc->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) roundup_pow_of_two(sz), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) if (!ioc->sense_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) ioc_err(ioc, "sense pool: pci_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) &ioc->sense_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) if (!ioc->sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) ioc_err(ioc, "sense pool: pci_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) "sense pool(0x%p)- dma(0x%llx): depth(%d),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) "element_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) SCSI_SENSE_BUFFERSIZE, sz / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) total_sz += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) /* reply pool, 4 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) sz = ioc->reply_free_queue_depth * ioc->reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) if (!ioc->reply_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) ioc_err(ioc, "reply pool: dma_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) &ioc->reply_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) if (!ioc->reply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) ioc_err(ioc, "reply pool: dma_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) ioc_info(ioc, "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) ioc->reply, ioc->reply_free_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) ioc->reply_sz, sz / 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) ioc_info(ioc, "reply_dma(0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) (unsigned long long)ioc->reply_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) total_sz += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) /* reply free queue, 16 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) sz = ioc->reply_free_queue_depth * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) &ioc->pdev->dev, sz, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) if (!ioc->reply_free_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) ioc_err(ioc, "reply_free pool: dma_pool_create failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) ioc->reply_free = dma_pool_zalloc(ioc->reply_free_dma_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) &ioc->reply_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) if (!ioc->reply_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) ioc_err(ioc, "reply_free pool: dma_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) ioc_info(ioc, "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) ioc->reply_free, ioc->reply_free_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) 4, sz / 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) ioc_info(ioc, "reply_free_dma (0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) (unsigned long long)ioc->reply_free_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) total_sz += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) if (ioc->rdpq_array_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) reply_post_free_array_sz = ioc->reply_queue_count *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) sizeof(Mpi2IOCInitRDPQArrayEntry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) ioc->reply_post_free_array_dma_pool =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) dma_pool_create("reply_post_free_array pool",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) if (!ioc->reply_post_free_array_dma_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) ioc_info(ioc, "reply_post_free_array pool: dma_pool_create failed\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) ioc->reply_post_free_array =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) GFP_KERNEL, &ioc->reply_post_free_array_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) if (!ioc->reply_post_free_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) ioc_info(ioc, "reply_post_free_array pool: dma_pool_alloc failed\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) ioc->config_page_sz = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) if (!ioc->config_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) ioc_err(ioc, "config page: dma_pool_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) ioc->config_page, (unsigned long long)ioc->config_page_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) ioc->config_page_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) total_sz += ioc->config_page_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) total_sz / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) ioc->shost->can_queue, facts->RequestCredit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) ioc->shost->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) * @cooked: Request raw or cooked IOC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) * Return: all IOC Doorbell register bits if cooked==0, else just the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) * Doorbell bits in MPI_IOC_STATE_MASK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) u32 s, sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) s = ioc->base_readl(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) sc = s & MPI2_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) return cooked ? sc : s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) * _base_wait_on_iocstate - waiting on a particular ioc state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) * @ioc: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) * @timeout: timeout in second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) u32 count, cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) u32 current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) cntdn = 1000 * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) current_state = mpt3sas_base_get_iocstate(ioc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) if (current_state == ioc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) if (count && current_state == MPI2_IOC_STATE_FAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) if (count && current_state == MPI2_IOC_STATE_COREDUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) } while (--cntdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) return current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) * _base_dump_reg_set - This function will print hexdump of register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) * Returns nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) unsigned int i, sz = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) u32 __iomem *reg = (u32 __iomem *)ioc->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) ioc_info(ioc, "System Register set:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) for (i = 0; i < (sz / sizeof(u32)); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) pr_info("%08x: %08x\n", (i * 4), readl(®[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) * a write to the doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) * @timeout: timeout in seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) u32 cntdn, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) cntdn = 1000 * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) __func__, count, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) } while (--cntdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) __func__, count, int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) u32 cntdn, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) cntdn = 2000 * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) __func__, count, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) } while (--cntdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) __func__, count, int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) * @timeout: timeout in second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) * doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) u32 cntdn, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) cntdn = 1000 * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) __func__, count, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) doorbell = ioc->base_readl(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) if ((doorbell & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) mpt3sas_print_fault_code(ioc, doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) if ((doorbell & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) mpt3sas_print_coredump_info(ioc, doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) } else if (int_status == 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) } while (--cntdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) __func__, count, int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) * @timeout: timeout in second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) u32 cntdn, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) u32 doorbell_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) cntdn = 1000 * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) __func__, count, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) } while (--cntdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) __func__, count, doorbell_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) * _base_send_ioc_reset - send doorbell reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) * @timeout: timeout in second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) ioc_err(ioc, "%s: unknown reset_type\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) if (!(ioc->facts.IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) ioc_info(ioc, "sending message unit reset !!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) &ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) if ((_base_wait_for_doorbell_ack(ioc, 15))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) if (ioc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) __func__, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) * Wait for IOC state CoreDump to clear only during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) * HBA initialization & release time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) if ((ioc_state & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) ioc->fault_reset_work_q == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) &ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) mpt3sas_print_coredump_info(ioc, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) mpt3sas_base_wait_for_coredump_completion(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) &ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) ioc_info(ioc, "message unit reset: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) r == 0 ? "SUCCESS" : "FAILED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) * @timeout: timeout in seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) * Return: Waits up to timeout seconds for the IOC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) * become operational. Returns 0 if IOC is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) * and operational; otherwise returns -EFAULT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) int wait_state_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) __func__, ++wait_state_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) if (wait_state_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) ioc_info(ioc, "ioc is operational\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) * _base_handshake_req_reply_wait - send request thru doorbell interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) * @request_bytes: request length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) * @request: pointer having request payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) * @reply_bytes: reply length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) * @reply: pointer to reply payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) * @timeout: timeout in second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) u32 *request, int reply_bytes, u16 *reply, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) u8 failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) __le32 *mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) /* make sure doorbell is not in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) /* clear pending doorbell interrupts from previous state changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) MPI2_HIS_IOC2SYS_DB_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) /* send message to ioc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) &ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) if ((_base_spin_on_doorbell_int(ioc, 5))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) if ((_base_wait_for_doorbell_ack(ioc, 5))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) /* send message 32-bits at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) if ((_base_wait_for_doorbell_ack(ioc, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) failed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) if (failed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) /* now wait for the reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) if ((_base_wait_for_doorbell_int(ioc, timeout))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) /* read the first two 16-bits, it gives the total length of the reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) & MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) if ((_base_wait_for_doorbell_int(ioc, 5))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) & MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) for (i = 2; i < default_reply->MsgLength * 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) if ((_base_wait_for_doorbell_int(ioc, 5))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) if (i >= reply_bytes/2) /* overflow case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) ioc->base_readl(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) reply[i] = le16_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) ioc->base_readl(&ioc->chip->Doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) & MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) _base_wait_for_doorbell_int(ioc, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) ioc_info(ioc, "doorbell is in use (line=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) __LINE__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) writel(0, &ioc->chip->HostInterruptStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) if (ioc->logging_level & MPT_DEBUG_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) mfp = (__le32 *)reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) pr_info("\toffset:data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) for (i = 0; i < reply_bytes/4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) le32_to_cpu(mfp[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) * @mpi_reply: the reply payload from FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) * @mpi_request: the request payload sent to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) * The SAS IO Unit Control Request message allows the host to perform low-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) * operations, such as resets on the PHYs of the IO Unit, also allows the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) * to obtain the IOC assigned device handles for a device if it has other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) * identifying information about the device, in addition allows the host to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) * remove IOC resources associated with the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) Mpi2SasIoUnitControlReply_t *mpi_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) Mpi2SasIoUnitControlRequest_t *mpi_request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) u8 issue_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) void *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) mutex_lock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) ioc_err(ioc, "%s: base_cmd in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) ioc->base_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) ioc->base_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) ioc->ioc_link_reset_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) init_completion(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) wait_for_completion_timeout(&ioc->base_cmds.done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) msecs_to_jiffies(10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) ioc->ioc_link_reset_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) ioc->ioc_link_reset_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) issue_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) goto issue_host_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) memcpy(mpi_reply, ioc->base_cmds.reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) sizeof(Mpi2SasIoUnitControlReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) issue_host_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) if (issue_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) mutex_unlock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) * @mpi_reply: the reply payload from FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) * @mpi_request: the request payload sent to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) * The SCSI Enclosure Processor request message causes the IOC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) * communicate with SES devices to control LED status signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) u8 issue_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) void *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) mutex_lock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) ioc_err(ioc, "%s: base_cmd in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) ioc->base_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) ioc->base_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) memset(request, 0, ioc->request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) init_completion(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) wait_for_completion_timeout(&ioc->base_cmds.done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) msecs_to_jiffies(10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) mpt3sas_check_cmd_timeout(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) ioc->base_cmds.status, mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) sizeof(Mpi2SepRequest_t)/4, issue_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) goto issue_host_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) memcpy(mpi_reply, ioc->base_cmds.reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) sizeof(Mpi2SepReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) issue_host_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) if (issue_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) mutex_unlock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) * _base_get_port_facts - obtain port facts reply and save in ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) * @port: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) Mpi2PortFactsRequest_t mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) Mpi2PortFactsReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) struct mpt3sas_port_facts *pfacts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) int mpi_reply_sz, mpi_request_sz, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) memset(&mpi_request, 0, mpi_request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) mpi_request.PortNumber = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) pfacts = &ioc->pfacts[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) pfacts->PortNumber = mpi_reply.PortNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) pfacts->VP_ID = mpi_reply.VP_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) pfacts->VF_ID = mpi_reply.VF_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) pfacts->MaxPostedCmdBuffers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) * @timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) if (ioc->pci_error_recovery) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) dfailprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) ioc_info(ioc, "%s: host in pci error recovery\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) __func__, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) if (ioc_state & MPI2_DOORBELL_USED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) mpt3sas_print_fault_code(ioc, ioc_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) __func__, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) if (ioc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) dfailprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) __func__, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) issue_diag_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) rc = _base_diag_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) Mpi2IOCFactsRequest_t mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) Mpi2IOCFactsReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) struct mpt3sas_facts *facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) int mpi_reply_sz, mpi_request_sz, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) r = _base_wait_for_iocstate(ioc, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) dfailprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) ioc_info(ioc, "%s: failed getting to correct state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) memset(&mpi_request, 0, mpi_request_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) facts = &ioc->facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) memset(facts, 0, sizeof(struct mpt3sas_facts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) facts->VP_ID = mpi_reply.VP_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) facts->VF_ID = mpi_reply.VF_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) facts->MaxChainDepth = mpi_reply.MaxChainDepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) facts->WhoInit = mpi_reply.WhoInit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) facts->NumberOfPorts = mpi_reply.NumberOfPorts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) if (ioc->msix_enable && (facts->MaxMSIxVectors <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) ioc->combined_reply_queue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) facts->MaxReplyDescriptorPostQueueDepth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) ioc->ir_firmware = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) if ((facts->IOCCapabilities &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) ioc->rdpq_array_capable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) && ioc->is_aero_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) ioc->atomic_desc_capable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) facts->IOCRequestFrameSize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) le16_to_cpu(mpi_reply.IOCRequestFrameSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) facts->IOCMaxChainSegmentSize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) ioc->shost->max_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) facts->HighPriorityCredit =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) le16_to_cpu(mpi_reply.HighPriorityCredit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) * Get the Page Size from IOC Facts. If it's 0, default to 4k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) ioc->page_size = 1 << facts->CurrentHostPageSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) if (ioc->page_size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) ioc_info(ioc, "CurrentHostPageSize(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) facts->CurrentHostPageSize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) facts->RequestCredit, facts->MaxChainDepth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) dinitprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) facts->IOCRequestFrameSize * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) facts->ReplyFrameSize * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) * _base_send_ioc_init - send ioc_init to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) Mpi2IOCInitRequest_t mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) Mpi2IOCInitReply_t mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) int i, r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) ktime_t current_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) u16 ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) u32 reply_post_free_array_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) mpi_request.VF_ID = 0; /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) mpi_request.VP_ID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) if (_base_is_controller_msix_enabled(ioc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) mpi_request.HostMSIxVectors = ioc->reply_queue_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) mpi_request.ReplyDescriptorPostQueueDepth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) cpu_to_le16(ioc->reply_post_queue_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) mpi_request.ReplyFreeQueueDepth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) cpu_to_le16(ioc->reply_free_queue_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) mpi_request.SenseBufferAddressHigh =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) cpu_to_le32((u64)ioc->sense_dma >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) mpi_request.SystemReplyAddressHigh =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) cpu_to_le32((u64)ioc->reply_dma >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) mpi_request.SystemRequestFrameBaseAddress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) cpu_to_le64((u64)ioc->request_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) mpi_request.ReplyFreeQueueAddress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) cpu_to_le64((u64)ioc->reply_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) if (ioc->rdpq_array_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) reply_post_free_array_sz = ioc->reply_queue_count *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) sizeof(Mpi2IOCInitRDPQArrayEntry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) for (i = 0; i < ioc->reply_queue_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) ioc->reply_post_free_array[i].RDPQBaseAddress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) cpu_to_le64(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) (u64)ioc->reply_post[i].reply_post_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) mpi_request.ReplyDescriptorPostQueueAddress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) cpu_to_le64((u64)ioc->reply_post_free_array_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) mpi_request.ReplyDescriptorPostQueueAddress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) * Set the flag to enable CoreDump state feature in IOC firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) mpi_request.ConfigurationFlags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) /* This time stamp specifies number of milliseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) * since epoch ~ midnight January 1, 1970.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) current_time = ktime_get_real();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) if (ioc->logging_level & MPT_DEBUG_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) __le32 *mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) mfp = (__le32 *)&mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) ioc_info(ioc, "\toffset:data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) le32_to_cpu(mfp[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) r = _base_handshake_req_reply_wait(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) mpi_reply.IOCLogInfo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) ioc_err(ioc, "%s: failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) r = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) * mpt3sas_port_enable_done - command completion routine for port enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) * @smid: system request message index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) * @msix_index: MSIX table index supplied by the OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) * @reply: reply message frame(lower 32bit addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) * Return: 1 meaning mf should be freed from _base_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) * 0 means the mf is freed from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) u32 reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) MPI2DefaultReply_t *mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) u16 ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) if (!mpi_reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) ioc->port_enable_failed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) if (ioc->is_driver_loading) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) mpt3sas_port_enable_complete(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) ioc->start_scan_failed = ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) ioc->start_scan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) complete(&ioc->port_enable_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) * _base_send_port_enable - send port_enable(discovery stuff) to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) Mpi2PortEnableRequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) Mpi2PortEnableReply_t *mpi_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) u16 ioc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) ioc_info(ioc, "sending port enable !!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) ioc_err(ioc, "%s: internal command already in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) ioc->port_enable_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) init_completion(&ioc->port_enable_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) ioc_err(ioc, "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) _debug_dump_mf(mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) sizeof(Mpi2PortEnableRequest_t)/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) r = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) mpi_reply = ioc->port_enable_cmds.reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) __func__, ioc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) Mpi2PortEnableRequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) ioc_info(ioc, "sending port enable !!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) ioc_err(ioc, "%s: internal command already in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) ioc->port_enable_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) * _base_determine_wait_on_discovery - desposition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) * Decide whether to wait on discovery to complete. Used to either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) * locate boot device, or report volumes ahead of physical devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) * Return: 1 for wait, 0 for don't wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) /* We wait for discovery to complete if IR firmware is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) * The sas topology events arrive before PD events, so we need time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) * turn on the bit in ioc->pd_handles to indicate PD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) * Also, it maybe required to report Volumes ahead of physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) if (ioc->ir_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) /* if no Bios, then we don't need to wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) if (!ioc->bios_pg3.BiosVersion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) /* Bios is present, then we drop down here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) * If there any entries in the Bios Page 2, then we wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) * for discovery to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) /* Current Boot Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) if ((ioc->bios_pg2.CurrentBootDeviceForm &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) MPI2_BIOSPAGE2_FORM_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) /* Request Boot Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) (ioc->bios_pg2.ReqBootDeviceForm &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) MPI2_BIOSPAGE2_FORM_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) /* Alternate Request Boot Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) (ioc->bios_pg2.ReqAltBootDeviceForm &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) MPI2_BIOSPAGE2_FORM_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) * _base_unmask_events - turn on notification for this event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) * @event: firmware event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) * The mask is stored in ioc->event_masks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) u32 desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) if (event >= 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) desired_event = (1 << (event % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) if (event < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) ioc->event_masks[0] &= ~desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) else if (event < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) ioc->event_masks[1] &= ~desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) else if (event < 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) ioc->event_masks[2] &= ~desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) else if (event < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) ioc->event_masks[3] &= ~desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) * _base_event_notification - send event notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) Mpi2EventNotificationRequest_t *mpi_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) ioc_err(ioc, "%s: internal command already in use\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) if (!smid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) ioc->base_cmds.status = MPT3_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) ioc->base_cmds.smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) mpi_request->VF_ID = 0; /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) mpi_request->VP_ID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) mpi_request->EventMasks[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) cpu_to_le32(ioc->event_masks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) init_completion(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) ioc->put_smid_default(ioc, smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) ioc_err(ioc, "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) _debug_dump_mf(mpi_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) sizeof(Mpi2EventNotificationRequest_t)/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) if (ioc->base_cmds.status & MPT3_CMD_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) r = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) * mpt3sas_base_validate_event_type - validating event types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) * @event_type: firmware event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) * This will turn on firmware event notification when application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) * ask for that event. We don't mask events that are already enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) u32 event_mask, desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) u8 send_update_to_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) for (i = 0, send_update_to_fw = 0; i <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) event_mask = ~event_type[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) desired_event = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) if (!(event_mask & desired_event) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) (ioc->event_masks[i] & desired_event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) ioc->event_masks[i] &= ~desired_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) send_update_to_fw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) desired_event = (desired_event << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) if (!send_update_to_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) mutex_lock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) _base_event_notification(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) mutex_unlock(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) * _base_diag_reset - the "big hammer" start of day reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) u32 host_diagnostic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) u32 hcb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) ioc_info(ioc, "sending diag reset !!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) pci_cfg_access_lock(ioc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) /* Write magic sequence to WriteSequence register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) * Loop until in diagnostic mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) /* wait 100 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) if (count++ > 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) "Stop writing magic sequence after 20 retries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) _base_dump_reg_set(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) drsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) count, host_diagnostic));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) &ioc->chip->HostDiagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) /*This delay allows the chip PCIe hardware time to finish reset tasks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) /* Approximately 300 second max wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) for (count = 0; count < (300000000 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) if (host_diagnostic == 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) "Invalid host diagnostic register value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) _base_dump_reg_set(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) drsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) writel(host_diagnostic, &ioc->chip->HostDiagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) &ioc->chip->HCBSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) &ioc->chip->HostDiagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) drsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) ioc_info(ioc, "disable writes to the diagnostic register\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) if (ioc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) __func__, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) _base_dump_reg_set(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) pci_cfg_access_unlock(ioc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) ioc_info(ioc, "diag reset: SUCCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) pci_cfg_access_unlock(ioc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) ioc_err(ioc, "diag reset: FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) * _base_make_ioc_ready - put controller in READY state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) * @type: FORCE_BIG_HAMMER or SOFT_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) if (ioc->pci_error_recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) dhsprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) __func__, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) /* if in RESET state, it should move to READY state shortly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) while ((ioc_state & MPI2_IOC_STATE_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) MPI2_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) if (count++ == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) __func__, ioc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) if (ioc_state & MPI2_DOORBELL_USED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) ioc_info(ioc, "unexpected doorbell active!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) mpt3sas_print_fault_code(ioc, ioc_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) * if host reset is invoked while watch dog thread is waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) * for IOC state to be changed to Fault state then driver has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) * to wait here for CoreDump state to clear otherwise reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) * will be issued to the FW and FW move the IOC state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) * reset state without copying the FW logs to coredump region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) mpt3sas_print_coredump_info(ioc, ioc_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) MPI2_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) mpt3sas_base_wait_for_coredump_completion(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) if (type == FORCE_BIG_HAMMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) goto issue_diag_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) if (!(_base_send_ioc_reset(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) issue_diag_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) rc = _base_diag_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) * _base_make_ioc_operational - put controller in OPERATIONAL state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) int r, i, index, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) u32 reply_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) struct _tr_list *delayed_tr, *delayed_tr_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) struct _sc_list *delayed_sc, *delayed_sc_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) u8 hide_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) struct adapter_reply_queue *reply_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) /* clean the delayed target reset list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) list_for_each_entry_safe(delayed_tr, delayed_tr_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) &ioc->delayed_tr_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) list_del(&delayed_tr->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) kfree(delayed_tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) list_for_each_entry_safe(delayed_tr, delayed_tr_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) &ioc->delayed_tr_volume_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) list_del(&delayed_tr->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) kfree(delayed_tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) list_for_each_entry_safe(delayed_sc, delayed_sc_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) &ioc->delayed_sc_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) list_del(&delayed_sc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) kfree(delayed_sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) &ioc->delayed_event_ack_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) list_del(&delayed_event_ack->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) kfree(delayed_event_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) /* hi-priority queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) INIT_LIST_HEAD(&ioc->hpr_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) smid = ioc->hi_priority_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) ioc->hpr_lookup[i].cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) ioc->hpr_lookup[i].smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) list_add_tail(&ioc->hpr_lookup[i].tracker_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) &ioc->hpr_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) /* internal queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) INIT_LIST_HEAD(&ioc->internal_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) smid = ioc->internal_smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) for (i = 0; i < ioc->internal_depth; i++, smid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) ioc->internal_lookup[i].cb_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) ioc->internal_lookup[i].smid = smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) list_add_tail(&ioc->internal_lookup[i].tracker_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) &ioc->internal_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) /* initialize Reply Free Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) for (i = 0, reply_address = (u32)ioc->reply_dma ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) i < ioc->reply_free_queue_depth ; i++, reply_address +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) ioc->reply_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) ioc->reply_free[i] = cpu_to_le32(reply_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) _base_clone_reply_to_sys_mem(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) reply_address, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) /* initialize reply queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) if (ioc->is_driver_loading)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) _base_assign_reply_queues(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) /* initialize Reply Post Free Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) reply_post_free_contig = ioc->reply_post[0].reply_post_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) * If RDPQ is enabled, switch to the next allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) * Otherwise advance within the contiguous region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) if (ioc->rdpq_array_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) reply_q->reply_post_free =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) ioc->reply_post[index++].reply_post_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) reply_q->reply_post_free = reply_post_free_contig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) reply_post_free_contig += ioc->reply_post_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) reply_q->reply_post_host_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) for (i = 0; i < ioc->reply_post_queue_depth; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) reply_q->reply_post_free[i].Words =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) cpu_to_le64(ULLONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) if (!_base_is_controller_msix_enabled(ioc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) goto skip_init_reply_post_free_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) skip_init_reply_post_free_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) r = _base_send_ioc_init(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) * No need to check IOC state for fault state & issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) * diag reset during host reset. This check is need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) * only during driver load time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) if (!ioc->is_driver_loading)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) rc = _base_check_for_fault_and_issue_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) if (rc || (_base_send_ioc_init(ioc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) /* initialize reply free host index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) /* initialize reply post host index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) if (ioc->combined_reply_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) writel((reply_q->msix_index & 7)<<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) MPI2_RPHI_MSIX_INDEX_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) writel(reply_q->msix_index <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) MPI2_RPHI_MSIX_INDEX_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) &ioc->chip->ReplyPostHostIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) if (!_base_is_controller_msix_enabled(ioc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) goto skip_init_reply_post_host_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) skip_init_reply_post_host_index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) mpt3sas_base_unmask_interrupts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) r = _base_display_fwpkg_version(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) _base_static_config_pages(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) r = _base_event_notification(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) if (ioc->is_driver_loading) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) == 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) hide_flag = (u8) (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) MFG_PAGE10_HIDE_SSDS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) ioc->mfg_pg10_hide_flag = hide_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) ioc->wait_for_discovery_to_complete =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) _base_determine_wait_on_discovery(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) return r; /* scan_start and scan_finished support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) r = _base_send_port_enable(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) * mpt3sas_base_free_resources - free resources controller resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) /* synchronizing freeing resource with pci_access_mutex lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) mutex_lock(&ioc->pci_access_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) if (ioc->chip_phys && ioc->chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) mpt3sas_base_mask_interrupts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) ioc->shost_recovery = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) _base_make_ioc_ready(ioc, SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) ioc->shost_recovery = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) mpt3sas_base_unmap_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) mutex_unlock(&ioc->pci_access_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) * mpt3sas_base_attach - attach controller instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) int r, i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) int cpu_id, last_cpu_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) /* setup cpu_msix_table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) ioc->cpu_count = num_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) for_each_online_cpu(cpu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) last_cpu_id = cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) ioc->cpu_msix_table_sz = last_cpu_id + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) ioc->reply_queue_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) if (!ioc->cpu_msix_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) if (ioc->is_warpdrive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) sizeof(resource_size_t *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) if (!ioc->reply_post_host_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) ioc->smp_affinity_enable = smp_affinity_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) ioc->rdpq_array_enable_assigned = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) ioc->use_32bit_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) if (ioc->is_aero_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) ioc->base_readl = &_base_readl_aero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) ioc->base_readl = &_base_readl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) r = mpt3sas_base_map_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) pci_set_drvdata(ioc->pdev, ioc->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) r = _base_get_ioc_facts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) rc = _base_check_for_fault_and_issue_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) if (rc || (_base_get_ioc_facts(ioc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) switch (ioc->hba_mpi_version_belonged) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) case MPI2_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) ioc->build_sg_scmd = &_base_build_sg_scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) ioc->build_sg = &_base_build_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) ioc->build_zero_len_sge = &_base_build_zero_len_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) ioc->get_msix_index_for_smlio = &_base_get_msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) case MPI25_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) case MPI26_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) * In SAS3.0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) * Target Status - all require the IEEE formated scatter gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) * elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) ioc->build_sg = &_base_build_sg_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) ioc->build_nvme_prp = &_base_build_nvme_prp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) if (ioc->high_iops_queues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) ioc->get_msix_index_for_smlio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) &_base_get_high_iops_msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) ioc->get_msix_index_for_smlio = &_base_get_msix_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) if (ioc->atomic_desc_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) ioc->put_smid_default = &_base_put_smid_default_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) ioc->put_smid_fast_path =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) &_base_put_smid_fast_path_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) ioc->put_smid_hi_priority =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) &_base_put_smid_hi_priority_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) ioc->put_smid_default = &_base_put_smid_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) ioc->put_smid_fast_path = &_base_put_smid_fast_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) if (ioc->is_mcpu_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) ioc->put_smid_scsi_io =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) &_base_put_smid_mpi_ep_scsi_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) * These function pointers for other requests that don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) * the require IEEE scatter gather elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) * For example Configuration Pages and SAS IOUNIT Control don't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) ioc->build_sg_mpi = &_base_build_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) r = _base_make_ioc_ready(ioc, SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) if (!ioc->pfacts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) r = _base_get_port_facts(ioc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) rc = _base_check_for_fault_and_issue_reset(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) if (rc || (_base_get_port_facts(ioc, i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) r = _base_allocate_memory_pools(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) if (irqpoll_weight > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) ioc->thresh_hold = irqpoll_weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) ioc->thresh_hold = ioc->hba_queue_depth/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) _base_init_irqpolls(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) init_waitqueue_head(&ioc->reset_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) /* allocate memory pd handle bitmask list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) if (ioc->facts.MaxDevHandle % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) ioc->pd_handles_sz++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) if (!ioc->pd_handles) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) if (!ioc->blocking_handles) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) /* allocate memory for pending OS device add list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) if (ioc->facts.MaxDevHandle % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) ioc->pend_os_device_add_sz++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) if (!ioc->pend_os_device_add) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) ioc->device_remove_in_progress =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) if (!ioc->device_remove_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) ioc->fwfault_debug = mpt3sas_fwfault_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) /* base internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) mutex_init(&ioc->base_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) ioc->base_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) /* port_enable command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) /* transport internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) mutex_init(&ioc->transport_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) /* scsih internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) mutex_init(&ioc->scsih_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) /* task management internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) mutex_init(&ioc->tm_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) /* config page internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) ioc->config_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) mutex_init(&ioc->config_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) /* ctl module internal command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) mutex_init(&ioc->ctl_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) ioc->event_masks[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) /* here we enable the events we care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) if (ioc->is_gen35_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) _base_unmask_events(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) _base_unmask_events(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) r = _base_make_ioc_operational(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) * Copy current copy of IOCFacts in prev_fw_facts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) * and it will be used during online firmware upgrade.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) memcpy(&ioc->prev_fw_facts, &ioc->facts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) sizeof(struct mpt3sas_facts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) ioc->non_operational_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) ioc->ioc_coredump_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) ioc->got_task_abort_from_ioctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) out_free_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) ioc->remove_host = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) mpt3sas_base_free_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) _base_release_memory_pools(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) pci_set_drvdata(ioc->pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) kfree(ioc->cpu_msix_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) if (ioc->is_warpdrive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) kfree(ioc->reply_post_host_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) kfree(ioc->pd_handles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) kfree(ioc->blocking_handles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) kfree(ioc->device_remove_in_progress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) kfree(ioc->pend_os_device_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) kfree(ioc->tm_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) kfree(ioc->transport_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) kfree(ioc->scsih_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) kfree(ioc->config_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) kfree(ioc->base_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) kfree(ioc->port_enable_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) kfree(ioc->ctl_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) kfree(ioc->ctl_cmds.sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) kfree(ioc->pfacts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) ioc->ctl_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) ioc->base_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) ioc->tm_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) ioc->scsih_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) ioc->transport_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) ioc->config_cmds.reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495) ioc->pfacts = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) * mpt3sas_base_detach - remove controller instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) mpt3sas_base_stop_watchdog(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) mpt3sas_base_free_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) _base_release_memory_pools(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) mpt3sas_free_enclosure_list(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) pci_set_drvdata(ioc->pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) kfree(ioc->cpu_msix_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) if (ioc->is_warpdrive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) kfree(ioc->reply_post_host_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) kfree(ioc->pd_handles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) kfree(ioc->blocking_handles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) kfree(ioc->device_remove_in_progress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) kfree(ioc->pend_os_device_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) kfree(ioc->pfacts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) kfree(ioc->ctl_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) kfree(ioc->ctl_cmds.sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) kfree(ioc->base_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) kfree(ioc->port_enable_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) kfree(ioc->tm_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) kfree(ioc->transport_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) kfree(ioc->scsih_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) kfree(ioc->config_cmds.reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) * _base_pre_reset_handler - pre reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) mpt3sas_scsih_pre_reset_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) mpt3sas_ctl_pre_reset_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) dtmprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) ioc->transport_cmds.status |= MPT3_CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) complete(&ioc->transport_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) ioc->base_cmds.status |= MPT3_CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) complete(&ioc->base_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) ioc->port_enable_failed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) if (ioc->is_driver_loading) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) ioc->start_scan_failed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) MPI2_IOCSTATUS_INTERNAL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) ioc->start_scan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) ioc->port_enable_cmds.status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) MPT3_CMD_NOT_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) complete(&ioc->port_enable_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) ioc->config_cmds.status |= MPT3_CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) ioc->config_cmds.smid = USHRT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) complete(&ioc->config_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) * _base_clear_outstanding_commands - clear all outstanding commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591) mpt3sas_ctl_clear_outstanding_ioctls(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) _base_clear_outstanding_mpt_commands(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) * _base_reset_done_handler - reset done handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) * @ioc: per adapter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) mpt3sas_scsih_reset_done_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) mpt3sas_ctl_reset_done_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) * mpt3sas_wait_for_commands_to_complete - reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) * This function is waiting 10s for all pending commands to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) * prior to putting controller in reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) ioc->pending_io_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) /* pending command count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) ioc->pending_io_count = scsi_host_busy(ioc->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) if (!ioc->pending_io_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) /* wait for pending commands to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) * attributes during online firmware upgrade and update the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) * IOC variables accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) u16 pd_handles_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) void *pd_handles = NULL, *blocking_handles = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) void *pend_os_device_add = NULL, *device_remove_in_progress = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) if (ioc->facts.MaxDevHandle % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) pd_handles_sz++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) if (!pd_handles) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) "Unable to allocate the memory for pd_handles of sz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) pd_handles_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) memset(pd_handles + ioc->pd_handles_sz, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) (pd_handles_sz - ioc->pd_handles_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) ioc->pd_handles = pd_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) blocking_handles = krealloc(ioc->blocking_handles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) pd_handles_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) if (!blocking_handles) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) "Unable to allocate the memory for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) "blocking_handles of sz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) pd_handles_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) memset(blocking_handles + ioc->pd_handles_sz, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) (pd_handles_sz - ioc->pd_handles_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) ioc->blocking_handles = blocking_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) ioc->pd_handles_sz = pd_handles_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) pend_os_device_add = krealloc(ioc->pend_os_device_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) pd_handles_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) if (!pend_os_device_add) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) pd_handles_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) (pd_handles_sz - ioc->pend_os_device_add_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) ioc->pend_os_device_add = pend_os_device_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) ioc->pend_os_device_add_sz = pd_handles_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) device_remove_in_progress = krealloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) if (!device_remove_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) "Unable to allocate the memory for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) "device_remove_in_progress of sz: %d\n "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) , pd_handles_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) memset(device_remove_in_progress +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) ioc->device_remove_in_progress_sz, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) (pd_handles_sz - ioc->device_remove_in_progress_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) ioc->device_remove_in_progress = device_remove_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) ioc->device_remove_in_progress_sz = pd_handles_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) * mpt3sas_base_hard_reset_handler - reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) * @type: FORCE_BIG_HAMMER or SOFT_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) * Return: 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) enum reset_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) u8 is_fault = 0, is_trigger = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) if (ioc->pci_error_recovery) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) goto out_unlocked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) if (mpt3sas_fwfault_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) mpt3sas_halt_firmware(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) /* wait for an active reset in progress to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) mutex_lock(&ioc->reset_in_progress_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) ioc->shost_recovery = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) MPT3_DIAG_BUFFER_IS_REGISTERED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) MPT3_DIAG_BUFFER_IS_RELEASED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) is_trigger = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) (ioc_state & MPI2_IOC_STATE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) MPI2_IOC_STATE_COREDUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) is_fault = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) _base_pre_reset_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) mpt3sas_wait_for_commands_to_complete(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) mpt3sas_base_mask_interrupts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) r = _base_make_ioc_ready(ioc, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) _base_clear_outstanding_commands(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766) /* If this hard reset is called while port enable is active, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) * there is no reason to call make_ioc_operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) if (ioc->is_driver_loading && ioc->port_enable_failed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) ioc->remove_host = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) r = _base_get_ioc_facts(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) r = _base_check_ioc_facts_changes(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) ioc_info(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) "Some of the parameters got changed in this new firmware"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) " image and it requires system reboot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) panic("%s: Issue occurred with flashing controller firmware."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) "Please reboot the system and ensure that the correct"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) " firmware version is running\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) r = _base_make_ioc_operational(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) _base_reset_done_handler(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) ioc->shost_recovery = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) ioc->ioc_reset_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) mutex_unlock(&ioc->reset_in_progress_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) out_unlocked:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) if ((r == 0) && is_trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) if (is_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) mpt3sas_trigger_master(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) MASTER_TRIGGER_ADAPTER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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