^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MESH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MESH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Registers in the MESH controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct mesh_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned char count_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) char pad0[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned char count_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) char pad1[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned char fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) char pad2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned char sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) char pad3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned char bus_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) char pad4[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned char bus_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) char pad5[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned char fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) char pad6[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned char exception;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char pad7[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned char error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) char pad8[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned char intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) char pad9[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned char interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char pad10[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned char source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) char pad11[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char dest_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) char pad12[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned char sync_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) char pad13[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned char mesh_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) char pad14[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char sel_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) char pad15[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Bits in the sequence register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SEQ_TARGET 0x40 /* put the controller into target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SEQ_ATN 0x20 /* assert ATN signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SEQ_CMD 0x0f /* command bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SEQ_ARBITRATE 1 /* get the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SEQ_SELECT 2 /* select a target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SEQ_COMMAND 3 /* send a command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SEQ_STATUS 4 /* receive status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SEQ_DATAOUT 5 /* send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SEQ_DATAIN 6 /* receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SEQ_MSGOUT 7 /* send a message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SEQ_MSGIN 8 /* receive a message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SEQ_BUSFREE 9 /* look for bus free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SEQ_ENBPARITY 0x0a /* enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SEQ_DISPARITY 0x0b /* disable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SEQ_ENBRESEL 0x0c /* enable reselection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SEQ_DISRESEL 0x0d /* disable reselection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SEQ_RESETMESH 0x0e /* reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Bits in the bus_status0 and bus_status1 registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) these correspond directly to the SCSI bus control signals. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BS0_REQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BS0_ACK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BS0_ATN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BS0_MSG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BS0_CD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BS0_IO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BS1_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BS1_BSY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BS1_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Bus phases defined by the bits in bus_status0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BP_DATAOUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BP_DATAIN BS0_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BP_COMMAND BS0_CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BP_STATUS (BS0_CD+BS0_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BP_MSGOUT (BS0_MSG+BS0_CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Bits in the exception register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EXC_ARBLOST 0x04 /* we lost arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EXC_SELTO 0x01 /* selection timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Bits in the error register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ERR_SEQERR 0x10 /* we did something the chip didn't like */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ERR_PARITY 0x01 /* parity error was detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Bits in the interrupt and intr_mask registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define INT_ERROR 0x04 /* error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INT_EXCEPTION 0x02 /* exception interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_CMDDONE 0x01 /* command done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Fields in the sync_params register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SYNC_OFF(x) ((x) >> 4) /* offset field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SYNC_PER(x) ((x) & 0xf) /* period field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SYNC_PARAMS(o, p) (((o) << 4) | (p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ASYNC_PARAMS 2 /* sync_params value for async xfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Assuming a clock frequency of 50MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * The transfer period with SYNC_PER(sync_params) == x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * is (x + 2) * 40ns, except that x == 0 gives 100ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * The units of the sel_timeout register are 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif /* _MESH_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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