^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux MegaRAID driver for SAS based RAID controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2003-2013 LSI Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2013-2016 Avago Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2016-2018 Broadcom Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * FILE: megaraid_sas.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Authors: Broadcom Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Kashyap Desai <kashyap.desai@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Sumit Saxena <sumit.saxena@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Send feedback to: megaraidlinux.pdl@broadcom.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef LSI_MEGARAID_SAS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LSI_MEGARAID_SAS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * MegaRAID SAS Driver meta data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MEGASAS_VERSION "07.714.04.00-rc1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MEGASAS_RELDATE "Apr 14, 2020"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MEGASAS_MSIX_NAME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Device IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_DEVICE_ID_LSI_FUSION 0x005b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_LSI_INVADER 0x005d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_DEVICE_ID_LSI_FURY 0x005f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Intel HBA SSDIDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Intruder HBA SSDIDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MEGARAID_INTRUDER_SSDID1 0x9371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MEGARAID_INTRUDER_SSDID2 0x9390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MEGARAID_INTRUDER_SSDID3 0x9370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Intel HBA branding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MEGARAID_INTEL_RS3DC080_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Intel(R) RAID Controller RS3DC080"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MEGARAID_INTEL_RS3DC040_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "Intel(R) RAID Controller RS3DC040"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MEGARAID_INTEL_RS3SC008_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "Intel(R) RAID Controller RS3SC008"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MEGARAID_INTEL_RS3MC044_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "Intel(R) RAID Controller RS3MC044"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MEGARAID_INTEL_RS3WC080_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "Intel(R) RAID Controller RS3WC080"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MEGARAID_INTEL_RS3WC040_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "Intel(R) RAID Controller RS3WC040"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MEGARAID_INTEL_RMS3BC160_BRANDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "Intel(R) Integrated RAID Module RMS3BC160"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * MegaRAID SAS MFI firmware definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * protocol between the software and firmware. Commands are issued using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * "message frames"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * FW posts its state in upper 4 bits of outbound_msg_0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MFI_STATE_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MFI_STATE_UNDEFINED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MFI_STATE_BB_INIT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MFI_STATE_FW_INIT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MFI_STATE_FW_INIT_2 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MFI_STATE_DEVICE_SCAN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MFI_STATE_FLUSH_CACHE 0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MFI_STATE_READY 0xB0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MFI_STATE_OPERATIONAL 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MFI_STATE_FAULT 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MFI_STATE_FORCE_OCR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MFI_STATE_DMADONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MFI_RESET_REQUIRED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MFI_RESET_ADAPTER 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MEGAMFI_FRAME_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MFI_STATE_FAULT_CODE 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * During FW init, clear pending cmds & reset state using inbound_msg_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * ABORT : Abort all pending cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * READY : Move from OPERATIONAL to READY state; discard queue info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * HOTPLUG : Resume from Hotplug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * MFI_STOP_ADP : Send signal to FW to stop processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DIAG_WRITE_ENABLE (0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DIAG_RESET_ADAPTER (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MFI_ADP_RESET 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MFI_INIT_ABORT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MFI_INIT_READY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MFI_INIT_MFIMODE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MFI_INIT_HOTPLUG 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MFI_STOP_ADP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MFI_RESET_FLAGS MFI_INIT_READY| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MFI_INIT_MFIMODE| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MFI_INIT_ABORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * MFI frame flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MFI_FRAME_SGL32 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MFI_FRAME_SGL64 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MFI_FRAME_SENSE32 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MFI_FRAME_SENSE64 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MFI_FRAME_DIR_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MFI_FRAME_DIR_WRITE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MFI_FRAME_DIR_READ 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MFI_FRAME_DIR_BOTH 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MFI_FRAME_IEEE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Driver internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DRV_DCMD_POLLED_MODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DRV_DCMD_SKIP_REFIRE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Definition for cmd_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MFI_CMD_STATUS_POLL_MODE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * MFI command opcodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum MFI_CMD_OP {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MFI_CMD_INIT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MFI_CMD_LD_READ = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MFI_CMD_LD_WRITE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MFI_CMD_LD_SCSI_IO = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MFI_CMD_PD_SCSI_IO = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MFI_CMD_DCMD = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MFI_CMD_ABORT = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MFI_CMD_SMP = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MFI_CMD_STP = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MFI_CMD_NVME = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MFI_CMD_TOOLBOX = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MFI_CMD_OP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MFI_CMD_INVALID = 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MR_DCMD_CTRL_GET_INFO 0x01010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MR_DCMD_LD_GET_LIST 0x03010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MR_DCMD_LD_LIST_QUERY 0x03010100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MR_FLUSH_CTRL_CACHE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MR_FLUSH_DISK_CACHE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MR_ENABLE_DRIVE_SPINDOWN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MR_DCMD_CTRL_EVENT_GET 0x01040300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MR_DCMD_CLUSTER 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MR_DCMD_PD_LIST_QUERY 0x02010100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MR_DCMD_PD_GET_INFO 0x02020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Global functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * MFI command completion codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enum MFI_STAT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MFI_STAT_OK = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MFI_STAT_INVALID_CMD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MFI_STAT_INVALID_DCMD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MFI_STAT_INVALID_PARAMETER = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MFI_STAT_APP_IN_USE = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MFI_STAT_APP_NOT_INITIALIZED = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MFI_STAT_FLASH_BUSY = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MFI_STAT_FLASH_ERROR = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MFI_STAT_FLASH_IMAGE_BAD = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MFI_STAT_FLASH_NOT_OPEN = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MFI_STAT_FLASH_NOT_STARTED = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MFI_STAT_FLUSH_FAILED = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MFI_STAT_MFC_HW_ERROR = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MFI_STAT_NO_HW_PRESENT = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MFI_STAT_NOT_FOUND = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MFI_STAT_NOT_IN_ENCL = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MFI_STAT_PD_TYPE_WRONG = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MFI_STAT_PR_DISABLED = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MFI_STAT_ROW_INDEX_INVALID = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MFI_STAT_SCSI_IO_FAILED = 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MFI_STAT_SHUTDOWN_FAILED = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MFI_STAT_TIME_NOT_SET = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MFI_STAT_WRONG_STATE = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MFI_STAT_LD_OFFLINE = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MFI_STAT_INVALID_STATUS = 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum mfi_evt_class {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MFI_EVT_CLASS_DEBUG = -2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MFI_EVT_CLASS_PROGRESS = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MFI_EVT_CLASS_INFO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MFI_EVT_CLASS_WARNING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MFI_EVT_CLASS_CRITICAL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MFI_EVT_CLASS_FATAL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MFI_EVT_CLASS_DEAD = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Crash dump related defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MAX_CRASH_DUMP_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CRASH_DMA_BUF_SIZE (1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum MR_FW_CRASH_DUMP_STATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) UNAVAILABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) AVAILABLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) COPYING = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) COPIED = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) COPY_ERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enum _MR_CRASH_BUF_STATUS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MR_CRASH_BUF_TURN_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MR_CRASH_BUF_TURN_ON = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Number of mailbox bytes in DCMD message frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MFI_MBOX_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enum MR_EVT_CLASS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MR_EVT_CLASS_DEBUG = -2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MR_EVT_CLASS_PROGRESS = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MR_EVT_CLASS_INFO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MR_EVT_CLASS_WARNING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MR_EVT_CLASS_CRITICAL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MR_EVT_CLASS_FATAL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MR_EVT_CLASS_DEAD = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum MR_EVT_LOCALE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MR_EVT_LOCALE_LD = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MR_EVT_LOCALE_PD = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MR_EVT_LOCALE_ENCL = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MR_EVT_LOCALE_BBU = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MR_EVT_LOCALE_SAS = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MR_EVT_LOCALE_CTRL = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MR_EVT_LOCALE_CONFIG = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MR_EVT_LOCALE_CLUSTER = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MR_EVT_LOCALE_ALL = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) enum MR_EVT_ARGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MR_EVT_ARGS_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MR_EVT_ARGS_CDB_SENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MR_EVT_ARGS_LD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MR_EVT_ARGS_LD_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MR_EVT_ARGS_LD_LBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MR_EVT_ARGS_LD_OWNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MR_EVT_ARGS_LD_LBA_PD_LBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MR_EVT_ARGS_LD_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MR_EVT_ARGS_LD_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MR_EVT_ARGS_LD_STRIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MR_EVT_ARGS_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MR_EVT_ARGS_PD_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MR_EVT_ARGS_PD_LBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MR_EVT_ARGS_PD_LBA_LD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MR_EVT_ARGS_PD_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MR_EVT_ARGS_PD_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MR_EVT_ARGS_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MR_EVT_ARGS_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MR_EVT_ARGS_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MR_EVT_ARGS_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MR_EVT_ARGS_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MR_EVT_ARGS_LD_PROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MR_EVT_ARGS_PD_SPARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MR_EVT_ARGS_PD_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MR_EVT_ARGS_DIAG_PASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MR_EVT_ARGS_DIAG_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MR_EVT_ARGS_PD_LBA_LBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MR_EVT_ARGS_PORT_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MR_EVT_ARGS_PD_MISSING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MR_EVT_ARGS_PD_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MR_EVT_ARGS_BITMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MR_EVT_ARGS_CONNECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MR_EVT_ARGS_PD_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MR_EVT_ARGS_PD_FRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MR_EVT_ARGS_PD_PATHINFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MR_EVT_ARGS_PD_POWER_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MR_EVT_ARGS_GENERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SGE_BUFFER_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MEGASAS_CLUSTER_ID_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * define constants for device list query options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enum MR_PD_QUERY_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MR_PD_QUERY_TYPE_ALL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MR_PD_QUERY_TYPE_STATE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MR_PD_QUERY_TYPE_POWER_STATE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MR_PD_QUERY_TYPE_SPEED = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) enum MR_LD_QUERY_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MR_LD_QUERY_TYPE_ALL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MR_EVT_CFG_CLEARED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MR_EVT_LD_STATE_CHANGE 0x0051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MR_EVT_PD_INSERTED 0x005b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MR_EVT_PD_REMOVED 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MR_EVT_LD_CREATED 0x008a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MR_EVT_LD_DELETED 0x008b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MR_EVT_LD_OFFLINE 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MR_EVT_CTRL_PROP_CHANGED 0x012f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) enum MR_PD_STATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MR_PD_STATE_HOT_SPARE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MR_PD_STATE_OFFLINE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MR_PD_STATE_FAILED = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MR_PD_STATE_REBUILD = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MR_PD_STATE_ONLINE = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MR_PD_STATE_COPYBACK = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MR_PD_STATE_SYSTEM = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) union MR_PD_REF {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u16 deviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u16 seqNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } mrPdRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * define the DDF Type bit structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) union MR_PD_DDF_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 forcedPDGUID:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u16 inVD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u16 isGlobalSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u16 isSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u16 isForeign:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u16 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u16 intf:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u16 intf:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u16 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 isForeign:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 isSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 isGlobalSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u16 inVD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u16 forcedPDGUID:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } pdType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } ddf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } nonDisk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * defines the progress structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) union MR_PROGRESS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 elapsedSecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u16 elapsedSecsForLastPercent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } mrProgress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * defines the physical drive progress structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct MR_PD_PROGRESS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 rbld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 patrol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 clear:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 copyBack:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 erase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 locate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 reserved:26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 reserved:26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 locate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 erase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 copyBack:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 clear:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 patrol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 rbld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) union MR_PROGRESS rbld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) union MR_PROGRESS patrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) union MR_PROGRESS clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) union MR_PROGRESS erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 rbld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 patrol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 clear:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 copyBack:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 erase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 reserved:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 reserved:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 erase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 copyBack:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 clear:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 patrol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 rbld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) union MR_PROGRESS reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct MR_PD_INFO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) union MR_PD_REF ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 inquiryData[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 vpdPage83[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 notSupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 scsiDevType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 connectedPortBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 connectedPortNumbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 deviceSpeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 mediaErrCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 otherErrCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 predFailCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 lastPredFailEventSeqNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u16 fwState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 disabledForRemoval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 linkSpeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) union MR_PD_DDF_TYPE state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 isPathBroken:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 reserved3:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 widePortCapable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 widePortCapable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 reserved3:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u8 isPathBroken:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u8 connectorIndex[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u64 sasAddr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 reserved2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } pathInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u64 rawSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u64 nonCoercedSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u64 coercedSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u16 enclDeviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 enclIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 slotNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u8 enclConnectorIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct MR_PD_PROGRESS progInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 badBlockTableFull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 unusableInCurrentConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 vpdPage83Ext[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 powerState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 enclPosition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 allowedOps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u16 copyBackPartnerId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u16 enclPartnerDeviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u16 fdeCapable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u16 fdeEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u16 secured:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u16 locked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u16 foreign:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u16 needsEKM:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 reserved:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u16 reserved:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u16 needsEKM:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u16 foreign:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u16 locked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u16 secured:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u16 fdeEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u16 fdeCapable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } security;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 mediaType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 notCertified;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 bridgeVendor[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 bridgeProductIdentification[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 bridgeProductRevisionLevel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 satBridgeExists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 interfaceType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 emulatedBlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u16 userDataBlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 piType:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 piFormatted:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 piEligible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 NCQ:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 WCE:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 commissionedSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 emergencySpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 ineligibleForSSCD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 ineligibleForLd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 useSSEraseType:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 wceUnchanged:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 supportScsiUnmap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 reserved:18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 reserved:18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 supportScsiUnmap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 wceUnchanged:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 useSSEraseType:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 ineligibleForLd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 ineligibleForSSCD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 emergencySpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 commissionedSpare:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 WCE:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 NCQ:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 piEligible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 piFormatted:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 piType:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u64 shieldDiagCompletionTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 shieldCounter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 linkSpeedOther;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 reserved4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 bbmErrCountSupported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 bbmErrCount:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 bbmErrCount:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 bbmErrCountSupported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } bbmErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u8 reserved1[512-428];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Definition of structure used to expose attributes of VD or JBOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * is fired by driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct MR_TARGET_PROPERTIES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 max_io_size_kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 device_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 reset_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u8 reserved[499];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * defines the physical drive address structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct MR_PD_ADDRESS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __le16 deviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u16 enclDeviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u8 enclIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 slotNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } mrPdAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u8 enclPosition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 enclConnectorIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } mrEnclAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u8 scsiDevType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u8 connectedPortBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 connectedPortNumbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u64 sasAddr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * defines the physical drive list structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct MR_PD_LIST {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct MR_PD_ADDRESS addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct megasas_pd_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u16 tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 driveType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u8 driveState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * defines the logical drive reference structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) union MR_LD_REF {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u8 targetId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __le16 seqNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __le32 ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * defines the logical drive list structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct MR_LD_LIST {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __le32 ldCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) union MR_LD_REF ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __le64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } ldList[MAX_LOGICAL_DRIVES_EXT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct MR_LD_TARGETID_LIST {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u8 targetId[MAX_LOGICAL_DRIVES_EXT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct MR_HOST_DEVICE_LIST_ENTRY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u8 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u8 is_sys_pd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u8 is_sys_pd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u8 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 scsi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __le16 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __le64 sas_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct MR_HOST_DEVICE_LIST {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __le32 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct MR_HOST_DEVICE_LIST_ENTRY host_device_list[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * SAS controller properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct megasas_ctrl_prop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u16 seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u16 pred_fail_poll_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u16 intr_throttle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u16 intr_throttle_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 rebuild_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 patrol_read_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 bgi_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 cc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u8 recon_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u8 cache_flush_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u8 spinup_drv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 spinup_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 cluster_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 coercion_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 alarm_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 disable_auto_rebuild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 disable_battery_warn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 ecc_bucket_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u16 ecc_bucket_leak_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 restore_hotspare_on_insertion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 expose_encl_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 maintainPdFailHistory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u8 disallowHostRequestReordering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 abortCCOnError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 loadBalanceMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 disableAutoDetectBackplane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u8 snapVDSpace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * Add properties that can be controlled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * a bit in the following structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 reserved:18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 enableJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 disableSpinDownHS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 allowBootWithPinnedCache:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 disableOnlineCtrlReset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 enableSecretKeyControl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 autoEnhancedImport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 enableSpinDownUnconfigured:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 SSDPatrolReadEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 SSDSMARTerEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u32 disableNCQ:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 useFdeOnly:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 prCorrectUnconfiguredAreas:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 SMARTerEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 copyBackDisabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 copyBackDisabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 SMARTerEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 prCorrectUnconfiguredAreas:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 useFdeOnly:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 disableNCQ:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 SSDSMARTerEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 SSDPatrolReadEnabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 enableSpinDownUnconfigured:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 autoEnhancedImport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 enableSecretKeyControl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 disableOnlineCtrlReset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 allowBootWithPinnedCache:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 disableSpinDownHS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 enableJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u32 reserved:18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) } OnOffProperties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u8 autoSnapVDSpace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u8 viewSpace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u16 reserved3:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u16 enable_fw_dev_list:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u16 reserved2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u16 enable_snap_dump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u16 reserved1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u16 reserved1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u16 enable_snap_dump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u16 reserved2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u16 enable_fw_dev_list:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u16 reserved3:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } on_off_properties2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) __le16 spinDownTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u8 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * SAS controller information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct megasas_ctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * PCI device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) __le16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) __le16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) __le16 sub_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) __le16 sub_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u8 reserved[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } __attribute__ ((packed)) pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Host interface information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 PCIX:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 PCIE:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u8 iSCSI:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u8 SAS_3G:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u8 SRIOV:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u8 reserved_0:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u8 reserved_1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u8 port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u64 port_addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } __attribute__ ((packed)) host_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * Device (backend) interface information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u8 SPI:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u8 SAS_3G:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u8 SATA_1_5G:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u8 SATA_3G:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u8 reserved_0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u8 reserved_1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u8 port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u64 port_addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) } __attribute__ ((packed)) device_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * List of components residing in flash. All str are null terminated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __le32 image_check_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __le32 image_component_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) char version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) char build_date[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) char built_time[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } __attribute__ ((packed)) image_component[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * List of flash components that have been flashed on the card, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * are not in use, pending reset of the adapter. This list will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * empty if a flash operation has not occurred. All stings are null
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * terminated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) __le32 pending_image_component_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) char version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) char build_date[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) char build_time[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } __attribute__ ((packed)) pending_image_component[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u8 max_arms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u8 max_spans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u8 max_arrays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) u8 max_lds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) char product_name[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) char serial_no[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * Other physical/controller/operation information. Indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * presence of the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 bbu:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 alarm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 nvram:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) u32 uart:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 reserved:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) } __attribute__ ((packed)) hw_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __le32 current_fw_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * Maximum data transfer sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) __le16 max_concurrent_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __le16 max_sge_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) __le32 max_request_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * Logical and physical device counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __le16 ld_present_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __le16 ld_degraded_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) __le16 ld_offline_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __le16 pd_present_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) __le16 pd_disk_present_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __le16 pd_disk_pred_failure_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __le16 pd_disk_failed_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * Memory size information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) __le16 nvram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) __le16 memory_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) __le16 flash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * Error counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) __le16 mem_correctable_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) __le16 mem_uncorrectable_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * Cluster information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u8 cluster_permitted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u8 cluster_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * Additional max data transfer sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) __le16 max_strips_per_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * Controller capabilities structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u32 raid_level_0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u32 raid_level_1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u32 raid_level_5:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 raid_level_1E:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) u32 raid_level_6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) u32 reserved:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) } __attribute__ ((packed)) raid_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u32 rbld_rate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) u32 cc_rate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u32 bgi_rate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 recon_rate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 patrol_rate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 alarm_control:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u32 cluster_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 bbu:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u32 spanning_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 dedicated_hotspares:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u32 revertible_hotspares:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u32 foreign_config_import:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u32 self_diagnostic:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) u32 mixed_redundancy_arr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) u32 global_hot_spares:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u32 reserved:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) } __attribute__ ((packed)) adapter_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u32 read_policy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) u32 write_policy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u32 io_policy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u32 access_policy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u32 disk_cache_policy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u32 reserved:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } __attribute__ ((packed)) ld_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u8 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u8 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) } __attribute__ ((packed)) stripe_sz_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u32 force_online:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u32 force_offline:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 force_rebuild:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u32 reserved:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) } __attribute__ ((packed)) pd_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 ctrl_supports_sas:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 ctrl_supports_sata:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 allow_mix_in_encl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u32 allow_mix_in_ld:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u32 allow_sata_in_cluster:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) u32 reserved:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) } __attribute__ ((packed)) pd_mix_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Define ECC single-bit-error bucket information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u8 ecc_bucket_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u8 reserved_2[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * Include the controller properties (changeable items)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct megasas_ctrl_prop properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * Define FW pkg version (set in envt v'bles on OEM basis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) char package_version[0x60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * If adapterOperations.supportMoreThan8Phys is set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * and deviceInterface.portCount is greater than 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * SAS Addrs for first 8 ports shall be populated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * deviceInterface.portAddr, and the rest shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * populated in deviceInterfacePortAddr2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) __le64 deviceInterfacePortAddr2[8]; /*6a0h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 reserved3[128]; /*6e0h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct { /*760h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u16 minPdRaidLevel_0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) u16 maxPdRaidLevel_0:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u16 minPdRaidLevel_1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u16 maxPdRaidLevel_1:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u16 minPdRaidLevel_5:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u16 maxPdRaidLevel_5:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u16 minPdRaidLevel_1E:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u16 maxPdRaidLevel_1E:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u16 minPdRaidLevel_6:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) u16 maxPdRaidLevel_6:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u16 minPdRaidLevel_10:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u16 maxPdRaidLevel_10:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u16 minPdRaidLevel_50:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) u16 maxPdRaidLevel_50:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u16 minPdRaidLevel_60:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) u16 maxPdRaidLevel_60:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u16 minPdRaidLevel_1E_RLQ0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u16 maxPdRaidLevel_1E_RLQ0:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u16 minPdRaidLevel_1E0_RLQ0:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) u16 maxPdRaidLevel_1E0_RLQ0:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u16 reserved[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } pdsForRaidLevels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) __le16 maxPds; /*780h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) __le16 maxDedHSPs; /*782h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) __le16 maxGlobalHSP; /*784h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) __le16 ddfSize; /*786h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u8 maxLdsPerArray; /*788h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u8 partitionsInDDF; /*789h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u8 lockKeyBinding; /*78ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u8 maxPITsPerLd; /*78bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u8 maxViewsPerLd; /*78ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u8 maxTargetId; /*78dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) __le16 maxBvlVdSize; /*78eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) __le16 maxConfigurableSSCSize; /*790h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) __le16 currentSSCsize; /*792h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) char expanderFwVersion[12]; /*794h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) __le16 PFKTrialTimeRemaining; /*7A0h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) __le16 cacheMemorySize; /*7A2h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct { /*7A4h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) u32 reserved:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) u32 activePassive:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 supportConfigAutoBalance:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u32 mpio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 supportDataLDonSSCArray:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u32 supportPointInTimeProgress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 supportUnevenSpans:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 dedicatedHotSparesLimited:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) u32 headlessMode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u32 supportEmulatedDrives:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) u32 supportResetNow:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u32 realTimeScheduler:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u32 supportSSDPatrolRead:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u32 supportPerfTuning:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) u32 disableOnlinePFKChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u32 supportJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u32 supportBootTimePFKChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u32 supportSetLinkSpeed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 supportEmergencySpares:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u32 supportSuspendResumeBGops:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u32 blockSSDWriteCacheChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u32 supportShieldState:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 supportLdBBMInfo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 supportLdPIType3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u32 supportLdPIType2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u32 supportLdPIType1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) u32 supportPIcontroller:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 supportPIcontroller:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u32 supportLdPIType1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u32 supportLdPIType2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u32 supportLdPIType3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u32 supportLdBBMInfo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u32 supportShieldState:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) u32 blockSSDWriteCacheChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u32 supportSuspendResumeBGops:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u32 supportEmergencySpares:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 supportSetLinkSpeed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u32 supportBootTimePFKChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) u32 supportJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u32 disableOnlinePFKChange:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 supportPerfTuning:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) u32 supportSSDPatrolRead:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) u32 realTimeScheduler:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u32 supportResetNow:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u32 supportEmulatedDrives:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u32 headlessMode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 dedicatedHotSparesLimited:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) u32 supportUnevenSpans:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u32 supportPointInTimeProgress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) u32 supportDataLDonSSCArray:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u32 mpio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u32 supportConfigAutoBalance:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u32 activePassive:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u32 reserved:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) } adapterOperations2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u8 driverVersion[32]; /*7A8h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u8 maxDAPdCountSpinup60; /*7C8h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u8 temperatureROC; /*7C9h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u8 temperatureCtrl; /*7CAh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u8 reserved4; /*7CBh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) __le16 maxConfigurablePds; /*7CCh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u8 reserved5[2]; /*0x7CDh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * HA cluster information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u32 reserved:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) u32 passive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 premiumFeatureMismatch:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 ctrlPropIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u32 fwVersionMismatch:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 hwIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 peerIsIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 peerIsPresent:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u32 peerIsPresent:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u32 peerIsIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u32 hwIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) u32 fwVersionMismatch:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u32 ctrlPropIncompatible:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) u32 premiumFeatureMismatch:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) u32 passive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) u32 reserved:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) } cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) u8 maxVFsSupported; /*0x7E4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) u8 numVFsEnabled; /*0x7E5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u8 reserved; /*0x7E7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) } iov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) u32 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) u32 useSeqNumJbodFP:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) u32 supportExtendedSSCSize:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u32 supportDiskCacheSettingForSysPDs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) u32 supportCPLDUpdate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 supportTTYLogCompression:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 discardCacheDuringLDDelete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) u32 supportSecurityonJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) u32 supportCacheBypassModes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) u32 supportDisableSESMonitoring:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) u32 supportForceFlash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) u32 supportNVDRAM:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) u32 supportDrvActivityLEDSetting:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u32 supportAllowedOpsforDrvRemoval:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) u32 supportHOQRebuild:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u32 supportForceTo512e:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 supportNVCacheErase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 supportDebugQueue:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) u32 supportSwZone:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u32 supportCrashDump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u32 supportMaxExtLDs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 supportT10RebuildAssist:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) u32 supportDisableImmediateIO:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) u32 supportThermalPollInterval:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u32 supportPersonalityChange:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) u32 supportPersonalityChange:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) u32 supportThermalPollInterval:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 supportDisableImmediateIO:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 supportT10RebuildAssist:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 supportMaxExtLDs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u32 supportCrashDump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) u32 supportSwZone:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u32 supportDebugQueue:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) u32 supportNVCacheErase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) u32 supportForceTo512e:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u32 supportHOQRebuild:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) u32 supportAllowedOpsforDrvRemoval:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) u32 supportDrvActivityLEDSetting:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 supportNVDRAM:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) u32 supportForceFlash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) u32 supportDisableSESMonitoring:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 supportCacheBypassModes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) u32 supportSecurityonJBOD:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) u32 discardCacheDuringLDDelete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u32 supportTTYLogCompression:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) u32 supportCPLDUpdate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u32 supportDiskCacheSettingForSysPDs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) u32 supportExtendedSSCSize:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) u32 useSeqNumJbodFP:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) u32 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) } adapterOperations3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) u8 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Indicates whether the CPLD image is part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * the package and stored in flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u8 cpld_in_flash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) u8 cpld_in_flash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) u8 reserved:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* Null terminated string. Has the version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * information if cpld_in_flash = FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) u8 userCodeDefinition[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) } cpld; /* Valid only if upgradableCPLD is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u16 reserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u16 support_nvme_passthru:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u16 support_pl_debug_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u16 support_flash_comp_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u16 support_host_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u16 support_dual_fw_update:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u16 support_ssc_rev3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u16 fw_swaps_bbu_vpd_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u16 support_pd_map_target_id:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u16 support_ses_ctrl_in_multipathcfg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) u16 image_upload_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u16 support_encrypted_mfc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u16 supported_enc_algo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) u16 support_ibutton_less:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) u16 ctrl_info_ext_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u16 ctrl_info_ext_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) u16 support_ibutton_less:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u16 supported_enc_algo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) u16 support_encrypted_mfc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) u16 image_upload_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* FW supports LUN based association and target port based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) u16 support_ses_ctrl_in_multipathcfg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* association for the SES device connected in multipath mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u16 support_pd_map_target_id:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * provide the data in little endian order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) u16 fw_swaps_bbu_vpd_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) u16 support_ssc_rev3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* FW supports CacheCade 3.0, only one SSCD creation allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u16 support_dual_fw_update:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* FW supports dual firmware update feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) u16 support_host_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u16 support_flash_comp_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u16 support_pl_debug_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* FW supports retrieval of PL debug information through apps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u16 support_nvme_passthru:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* FW supports NVMe passthru commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u16 reserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) } adapter_operations4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) u8 reserved6[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u32 reserved:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u32 support_pci_lane_margining: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u32 support_psoc_update:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u32 support_force_personality_change:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u32 support_fde_type_mix:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u32 support_snap_dump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) u32 support_nvme_tm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) u32 support_oce_only:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u32 support_ext_mfg_vpd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u32 support_pcie:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u32 support_cvhealth_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u32 support_profile_change:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) u32 mr_config_ext2_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u32 mr_config_ext2_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u32 support_profile_change:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u32 support_cvhealth_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) u32 support_pcie:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u32 support_ext_mfg_vpd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 support_oce_only:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) u32 support_nvme_tm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u32 support_snap_dump:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) u32 support_fde_type_mix:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) u32 support_force_personality_change:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) u32 support_psoc_update:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) u32 support_pci_lane_margining: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) u32 reserved:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) } adapter_operations5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) u32 rsvdForAdptOp[63];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) u8 reserved7[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) u8 reserved8[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * ===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * MegaRAID SAS driver definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * ===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define MEGASAS_MAX_PD_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define MEGASAS_MAX_LD_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) MEGASAS_MAX_LD_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define MEGASAS_MAX_DEV_PER_CHANNEL 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define MEGASAS_DEFAULT_INIT_ID -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define MEGASAS_MAX_LUN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define MEGASAS_DEFAULT_CMD_PER_LUN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) MEGASAS_MAX_DEV_PER_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) MEGASAS_MAX_DEV_PER_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define MEGASAS_MAX_SECTORS (2*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define MEGASAS_MAX_SECTORS_IEEE (2*128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define MEGASAS_DBG_LVL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define MEGASAS_FW_BUSY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* Driver's internal Logging levels*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define OCR_DEBUG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define TM_DEBUG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define LD_PD_DEBUG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define SCAN_PD_CHANNEL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define SCAN_VD_CHANNEL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define MEGASAS_KDUMP_QUEUE_DEPTH 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) enum MR_SCSI_CMD_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) READ_WRITE_LDIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) NON_READ_WRITE_LDIO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) READ_WRITE_SYSPDIO = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) NON_READ_WRITE_SYSPDIO = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) enum DCMD_TIMEOUT_ACTION {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) INITIATE_OCR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) KILL_ADAPTER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) IGNORE_TIMEOUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) enum FW_BOOT_CONTEXT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) PROBE_CONTEXT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) OCR_CONTEXT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* Frame Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define IO_FRAME 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define PTHRU_FRAME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * When SCSI mid-layer calls driver's reset routine, driver waits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * that the driver cannot _actually_ abort or reset pending commands. While
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * it is waiting for the commands to complete, it prints a diagnostic message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * every MEGASAS_RESET_NOTICE_INTERVAL seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define MEGASAS_RESET_WAIT_TIME 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define MEGASAS_RESET_NOTICE_INTERVAL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define MEGASAS_IOCTL_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define MEGASAS_DEFAULT_TM_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * FW reports the maximum of number of commands that it can accept (maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * commands that can be outstanding) at any time. The driver must report a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * lower number to the mid layer because it can issue a few internal commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * is shown below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define MEGASAS_INT_CMDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define MEGASAS_SKINNY_INT_CMDS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define MEGASAS_FUSION_INTERNAL_CMDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define MEGASAS_FUSION_IOCTL_CMDS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define MEGASAS_MFI_IOCTL_CMDS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define MEGASAS_MAX_MSIX_QUEUES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * SGLs based on the size of dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define IS_DMA64 (sizeof(dma_addr_t) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define MFI_OB_INTR_STATUS_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define MFI_POLL_TIMEOUT_SECS 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define MFI_IO_TIMEOUT_SECS 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define MFI_1068_PCSR_OFFSET 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define MFI_1068_FW_READY 0xDDDD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define MR_MAX_MSIX_REG_ARRAY 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define MR_RDPQ_MODE_OFFSET 0X00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define MR_MIN_MAP_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* 64k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define MR_INTR_COALESCING_SUPPORT_OFFSET (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define MEGASAS_WATCHDOG_WAIT_COUNT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) enum MR_ADAPTER_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) MFI_SERIES = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) THUNDERBOLT_SERIES = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) INVADER_SERIES = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) VENTURA_SERIES = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) AERO_SERIES = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * register set for both 1068 and 1078 controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * structure extended for 1078 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct megasas_register_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u32 doorbell; /*0000h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 fusion_seq_offset; /*0004h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u32 fusion_host_diag; /*0008h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 reserved_01; /*000Ch*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 inbound_msg_0; /*0010h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u32 inbound_msg_1; /*0014h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) u32 outbound_msg_0; /*0018h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) u32 outbound_msg_1; /*001Ch*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) u32 inbound_doorbell; /*0020h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) u32 inbound_intr_status; /*0024h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u32 inbound_intr_mask; /*0028h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u32 outbound_doorbell; /*002Ch*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 outbound_intr_status; /*0030h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) u32 outbound_intr_mask; /*0034h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u32 reserved_1[2]; /*0038h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u32 inbound_queue_port; /*0040h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u32 outbound_queue_port; /*0044h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u32 reserved_2[9]; /*0048h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u32 reply_post_host_index; /*006Ch*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u32 reserved_2_2[12]; /*0070h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u32 outbound_doorbell_clear; /*00A0h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u32 reserved_3[3]; /*00A4h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) u32 outbound_scratch_pad_0; /*00B0h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) u32 outbound_scratch_pad_1; /*00B4h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) u32 outbound_scratch_pad_2; /*00B8h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) u32 outbound_scratch_pad_3; /*00BCh*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) u32 inbound_low_queue_port ; /*00C0h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u32 inbound_high_queue_port ; /*00C4h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) u32 inbound_single_queue_port; /*00C8h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u32 res_6[11]; /*CCh*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 host_diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) u32 seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u32 index_registers[807]; /*00CCh*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct megasas_sge32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) __le32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct megasas_sge64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) __le64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct megasas_sge_skinny {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) __le64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) __le32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) union megasas_sgl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct megasas_sge32 sge32[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct megasas_sge64 sge64[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct megasas_sge_skinny sge_skinny[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct megasas_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) u8 sense_len; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) u8 scsi_status; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) u8 target_id; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) u8 lun; /*05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) u8 cdb_len; /*06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) __le32 data_xferlen; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) union megasas_sgl_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) struct megasas_sge32 sge32[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct megasas_sge64 sge64[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) typedef union _MFI_CAPABILITIES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #if defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) u32 reserved:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) u32 support_fw_exposed_dev_list:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) u32 support_nvme_passthru:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) u32 support_64bit_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) u32 support_pd_map_target_id:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u32 support_qd_throttling:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u32 support_fp_rlbypass:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) u32 support_vfid_in_ioframe:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) u32 support_ext_io_size:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) u32 support_ext_queue_depth:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) u32 security_protocol_cmds_fw:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) u32 support_core_affinity:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) u32 support_ndrive_r1_lb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) u32 support_max_255lds:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) u32 support_fastpath_wb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) u32 support_additional_msix:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u32 support_fp_remote_lun:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) u32 support_fp_remote_lun:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u32 support_additional_msix:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 support_fastpath_wb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u32 support_max_255lds:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u32 support_ndrive_r1_lb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) u32 support_core_affinity:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u32 security_protocol_cmds_fw:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) u32 support_ext_queue_depth:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) u32 support_ext_io_size:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) u32 support_vfid_in_ioframe:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 support_fp_rlbypass:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) u32 support_qd_throttling:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) u32 support_pd_map_target_id:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) u32 support_64bit_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) u32 support_nvme_passthru:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) u32 support_fw_exposed_dev_list:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) u32 reserved:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } mfi_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } MFI_CAPABILITIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) struct megasas_init_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) u8 reserved_0; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) u8 reserved_1; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) MFI_CAPABILITIES driver_operations; /*04h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) __le16 replyqueue_mask; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) __le32 data_xfer_len; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) __le32 queue_info_new_phys_addr_lo; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) __le32 queue_info_new_phys_addr_hi; /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) __le32 queue_info_old_phys_addr_lo; /*20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) __le32 queue_info_old_phys_addr_hi; /*24h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) __le32 reserved_4[2]; /*28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) __le32 system_info_lo; /*30h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) __le32 system_info_hi; /*34h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) __le32 reserved_5[2]; /*38h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct megasas_init_queue_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) __le32 init_flags; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) __le32 reply_queue_entries; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) __le32 reply_queue_start_phys_addr_lo; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) __le32 reply_queue_start_phys_addr_hi; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) __le32 producer_index_phys_addr_lo; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) __le32 producer_index_phys_addr_hi; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) __le32 consumer_index_phys_addr_lo; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) __le32 consumer_index_phys_addr_hi; /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct megasas_io_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) u8 sense_len; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) u8 scsi_status; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) u8 target_id; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) u8 access_byte; /*05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) u8 reserved_0; /*06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) __le32 lba_count; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) __le32 sense_buf_phys_addr_lo; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) __le32 sense_buf_phys_addr_hi; /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) __le32 start_lba_lo; /*20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) __le32 start_lba_hi; /*24h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) union megasas_sgl sgl; /*28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct megasas_pthru_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) u8 sense_len; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) u8 scsi_status; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) u8 target_id; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) u8 lun; /*05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) u8 cdb_len; /*06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) __le32 data_xfer_len; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) __le32 sense_buf_phys_addr_lo; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) __le32 sense_buf_phys_addr_hi; /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) u8 cdb[16]; /*20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) union megasas_sgl sgl; /*30h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct megasas_dcmd_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) u8 reserved_0; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u8 reserved_1[4]; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) __le32 data_xfer_len; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __le32 opcode; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) union { /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) u8 b[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) __le16 s[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) __le32 w[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) } mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) union megasas_sgl sgl; /*28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct megasas_abort_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) u8 reserved_0; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u8 reserved_1; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) __le32 reserved_2; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) __le16 reserved_3; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) __le32 reserved_4; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) __le32 abort_context; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) __le32 pad_1; /*1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) __le32 abort_mfi_phys_addr_lo; /*20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) __le32 abort_mfi_phys_addr_hi; /*24h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) __le32 reserved_5[6]; /*28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct megasas_smp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) u8 reserved_1; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) u8 connection_status; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) u8 reserved_2[3]; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) __le32 data_xfer_len; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) __le64 sas_addr; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) } sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct megasas_stp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) u8 cmd; /*00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) u8 reserved_1; /*01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) u8 cmd_status; /*02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) u8 reserved_2; /*03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) u8 target_id; /*04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) u8 reserved_3[2]; /*05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) u8 sge_count; /*07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) __le32 context; /*08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) __le32 pad_0; /*0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) __le16 flags; /*10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __le16 timeout; /*12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) __le32 data_xfer_len; /*14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) __le16 fis[10]; /*18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) __le32 stp_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) } sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) union megasas_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct megasas_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) struct megasas_init_frame init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) struct megasas_io_frame io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) struct megasas_pthru_frame pthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) struct megasas_dcmd_frame dcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) struct megasas_abort_frame abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct megasas_smp_frame smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct megasas_stp_frame stp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) u8 raw_bytes[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * struct MR_PRIV_DEVICE - sdev private hostdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * @is_tm_capable: firmware managed tm_capable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * @tm_busy: TM request is in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) struct MR_PRIV_DEVICE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) bool is_tm_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) bool tm_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) atomic_t r1_ldio_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) u8 interface_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) u8 task_abort_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) u8 target_reset_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct megasas_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) union megasas_evt_class_locale {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #ifndef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) u16 locale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) s8 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) s8 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) u16 locale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) } __attribute__ ((packed)) members;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) struct megasas_evt_log_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) __le32 newest_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) __le32 oldest_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) __le32 clear_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) __le32 shutdown_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) __le32 boot_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct megasas_progress {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) __le16 progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) __le16 elapsed_seconds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct megasas_evtarg_ld {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) u16 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) u8 ld_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct megasas_evtarg_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) u8 encl_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) u8 slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct megasas_evt_detail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) __le32 seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) __le32 time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) __le32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) union megasas_evt_class_locale cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) u8 arg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) u8 reserved1[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) u8 cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) u8 sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) u8 cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) u8 sense[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) } __attribute__ ((packed)) cdbSense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) __le64 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) } __attribute__ ((packed)) ld_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) __le64 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) } __attribute__ ((packed)) ld_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) __le32 prevOwner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) __le32 newOwner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) } __attribute__ ((packed)) ld_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) u64 ld_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) u64 pd_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) } __attribute__ ((packed)) ld_lba_pd_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) struct megasas_progress prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) } __attribute__ ((packed)) ld_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) u32 prev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) u32 new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) } __attribute__ ((packed)) ld_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) u64 strip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) } __attribute__ ((packed)) ld_strip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) u32 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) } __attribute__ ((packed)) pd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) u64 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) } __attribute__ ((packed)) pd_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) u64 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct megasas_evtarg_ld ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) } __attribute__ ((packed)) pd_lba_ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct megasas_progress prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) } __attribute__ ((packed)) pd_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct megasas_evtarg_pd pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) u32 prevState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) u32 newState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) } __attribute__ ((packed)) pd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) u16 vendorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) __le16 deviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) u16 subVendorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) u16 subDeviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) } __attribute__ ((packed)) pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) char str[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) u32 rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) u32 elapsedSeconds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) } __attribute__ ((packed)) time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) u32 ecar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) u32 elog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) char str[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) } __attribute__ ((packed)) ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) u8 b[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) __le16 s[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) __le32 w[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) __le64 d[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) } args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) char description[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) struct megasas_aen_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) struct delayed_work hotplug_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) struct megasas_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) struct megasas_irq_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) char name[MEGASAS_MSIX_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct megasas_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) u32 MSIxIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) u32 os_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct irq_poll irqpoll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) bool irq_poll_scheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) bool irq_line_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) struct MR_DRV_SYSTEM_INFO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) u8 infoVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) u8 systemIdLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) u16 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) u8 systemId[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) u8 reserved[1980];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) enum MR_PD_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) UNKNOWN_DRIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) PARALLEL_SCSI = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) SAS_PD = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) SATA_PD = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) FC_PD = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) NVME_PD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* JBOD Queue depth definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define MEGASAS_SATA_QD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define MEGASAS_SAS_QD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define MEGASAS_DEFAULT_PD_QD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define MEGASAS_NVME_QD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define MR_DEFAULT_NVME_PAGE_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define MR_DEFAULT_NVME_PAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define MR_DEFAULT_NVME_MDTS_KB 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /*Aero performance parameters*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define MR_HIGH_IOPS_QUEUE_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define MR_DEVICE_HIGH_IOPS_DEPTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define MR_HIGH_IOPS_BATCH_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) enum MR_PERF_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) MR_BALANCED_PERF_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) MR_IOPS_PERF_MODE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) MR_LATENCY_PERF_MODE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define MEGASAS_PERF_MODE_2STR(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) "Unknown")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) enum MEGASAS_LD_TARGET_ID_STATUS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) LD_TARGET_ID_INITIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) LD_TARGET_ID_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) LD_TARGET_ID_DELETED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define MEGASAS_TARGET_ID(sdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) (((sdev->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct megasas_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) unsigned int *reply_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) __le32 *producer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) dma_addr_t producer_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) __le32 *consumer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) dma_addr_t consumer_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) struct MR_DRV_SYSTEM_INFO *system_info_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) dma_addr_t system_info_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct MR_LD_VF_AFFILIATION *vf_affiliation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) dma_addr_t vf_affiliation_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) dma_addr_t vf_affiliation_111_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) dma_addr_t hb_host_mem_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) struct MR_PD_INFO *pd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dma_addr_t pd_info_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) struct MR_TARGET_PROPERTIES *tgt_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) dma_addr_t tgt_prop_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) __le32 *reply_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) dma_addr_t reply_queue_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) u32 *crash_dump_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) dma_addr_t crash_dump_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct MR_PD_LIST *pd_list_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) dma_addr_t pd_list_buf_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) struct megasas_ctrl_info *ctrl_info_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) dma_addr_t ctrl_info_buf_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) struct MR_LD_LIST *ld_list_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) dma_addr_t ld_list_buf_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) dma_addr_t ld_targetid_list_buf_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) struct MR_HOST_DEVICE_LIST *host_device_list_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) dma_addr_t host_device_list_buf_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) dma_addr_t snapdump_prop_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) void *crash_buf[MAX_CRASH_DUMP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) unsigned int fw_crash_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) unsigned int fw_crash_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) unsigned int fw_crash_buffer_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) u32 drv_buf_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) u32 drv_buf_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) u32 crash_dump_fw_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) u32 crash_dump_drv_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) u32 crash_dump_app_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) u32 secure_jbod_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) bool use_seqnum_jbod_fp; /* Added for PD sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) bool smp_affinity_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) spinlock_t crashdump_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct megasas_register_set __iomem *reg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) u8 ld_ids[MEGASAS_MAX_LD_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) u8 ld_tgtid_status[MEGASAS_MAX_LD_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) u8 ld_ids_prev[MEGASAS_MAX_LD_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) u8 ld_ids_from_raidmap[MEGASAS_MAX_LD_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) s8 init_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) u16 max_num_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) u16 max_fw_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) u16 max_mpt_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) u16 max_mfi_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) u16 max_scsi_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) u16 ldio_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) u16 cur_can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) u32 max_sectors_per_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) bool msix_load_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) struct megasas_aen_event *ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) struct megasas_cmd **cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) struct list_head cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /* used to sync fire the cmd to fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) spinlock_t mfi_pool_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* used to sync fire the cmd to fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) spinlock_t hba_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) /* used to synch producer, consumer ptrs in dpc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) spinlock_t stream_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) spinlock_t completion_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct dma_pool *frame_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) struct dma_pool *sense_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) struct megasas_evt_detail *evt_detail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) dma_addr_t evt_detail_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) struct megasas_cmd *aen_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) struct semaphore ioctl_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) wait_queue_head_t int_cmd_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) wait_queue_head_t abort_cmd_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) u32 unique_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) u32 fw_support_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) u32 threshold_reply_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) atomic_t fw_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) atomic_t ldio_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) atomic_t fw_reset_no_pci_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) atomic64_t total_io_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) atomic64_t high_iops_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) struct megasas_instance_template *instancet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) struct tasklet_struct isr_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) struct work_struct work_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) struct delayed_work fw_fault_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct workqueue_struct *fw_fault_work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) char fault_handler_work_q_name[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) u8 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) u8 unload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) u8 flag_ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) u8 issuepend_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) u8 disableOnlineCtrlReset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) u8 UnevenSpanSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) u8 supportmax256vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) u8 pd_list_not_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) u16 fw_supported_vd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) u16 fw_supported_pd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) u16 drv_supported_vd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) u16 drv_supported_pd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) atomic_t adprecovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) unsigned long last_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 mfiStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) u32 last_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) struct list_head internal_reset_pending_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* Ptr to hba specific information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) void *ctrl_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) unsigned int msix_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) u64 map_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) u64 pd_seq_map_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) struct megasas_cmd *map_update_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) struct megasas_cmd *jbod_seq_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) unsigned long bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) long reset_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) struct mutex reset_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) struct timer_list sriov_heartbeat_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) char skip_heartbeat_timer_del;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) u8 requestorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) char PlasmaFW111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) char clusterId[MEGASAS_CLUSTER_ID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) u8 peerIsPresent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) u8 passive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) u16 throttlequeuedepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) u8 mask_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) u16 max_chain_frame_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) u8 is_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) u8 is_rdpq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) bool dev_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) bool fw_sync_cache_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) u32 mfi_frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) bool msix_combined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) u16 max_raid_mapsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* preffered count to send as LDIO irrspective of FP capable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) u8 r1_ldio_hint_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) u32 nvme_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) u8 adapter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) bool consistent_mask_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) bool support_nvme_passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) bool enable_sdev_max_qd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) u8 task_abort_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u8 max_reset_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) u8 snapdump_wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) struct dentry *raidmap_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) u8 enable_fw_dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) bool atomic_desc_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) bool support_seqnum_jbod_fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) bool support_pci_lane_margining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) u8 low_latency_index_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) int perf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) struct MR_LD_VF_MAP {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) union MR_LD_REF ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) u8 ldVfCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) u8 reserved[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) u8 policy[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) struct MR_LD_VF_AFFILIATION {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) u8 ldCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) u8 vfCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) u8 thisVf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) u8 reserved[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) struct MR_LD_VF_MAP map[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* Plasma 1.11 FW backward compatibility structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define IOV_111_OFFSET 0x7CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define MAX_VIRTUAL_FUNCTIONS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define MR_LD_ACCESS_HIDDEN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) struct IOV_111 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) u8 maxVFsSupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) u8 numVFsEnabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) u8 requestorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) u8 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct MR_LD_VF_MAP_111 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) u8 targetId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) u8 policy[MAX_VIRTUAL_FUNCTIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) struct MR_LD_VF_AFFILIATION_111 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) u8 vdCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) u8 vfCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) u8 thisVf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) u8 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) struct MR_CTRL_HB_HOST_MEM {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) u32 fwCounter; /* Firmware heart beat counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) u32 debugmode:1; /* 1=Firmware is in debug mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) Heart beat will not be updated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) u32 reserved:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) } debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) u32 reserved_fw[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) u32 driverCounter; /* Driver heart beat counter. 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) u32 reserved_driver[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) } HB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) u8 pad[0x400-0x40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) MEGASAS_HBA_OPERATIONAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) MEGASAS_ADPRESET_SM_INFAULT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) MEGASAS_HW_CRITICAL_ERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) MEGASAS_ADPRESET_SM_POLLING = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) struct megasas_instance_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) u32, struct megasas_register_set __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) void (*enable_intr)(struct megasas_instance *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) void (*disable_intr)(struct megasas_instance *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) int (*clear_intr)(struct megasas_instance *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) u32 (*read_fw_status_reg)(struct megasas_instance *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) int (*adp_reset)(struct megasas_instance *, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct megasas_register_set __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) int (*check_reset)(struct megasas_instance *, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct megasas_register_set __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) irqreturn_t (*service_isr)(int irq, void *devp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) void (*tasklet)(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) u32 (*init_adapter)(struct megasas_instance *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) u32 (*build_and_issue_cmd) (struct megasas_instance *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) void (*issue_dcmd)(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) struct megasas_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define MEGASAS_IS_LOGICAL(sdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) #define MEGASAS_DEV_INDEX(scp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) scp->device->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define MEGASAS_PD_INDEX(scp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) scp->device->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) struct megasas_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) union megasas_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) dma_addr_t frame_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) u8 *sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) dma_addr_t sense_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) u8 sync_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) u8 cmd_status_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) u8 abort_aen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) u8 retry_for_fw_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) struct scsi_cmnd *scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct megasas_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) u16 smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) u16 resvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) } context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) u32 frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define MAX_MGMT_ADAPTERS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #define MAX_IOCTL_SGE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) struct megasas_iocpacket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) u16 host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) u16 __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) u32 sgl_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) u32 sge_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) u32 sense_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) u32 sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) u8 raw[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct megasas_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) } frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct iovec sgl[MAX_IOCTL_SGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) struct megasas_aen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) u16 host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) u16 __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) u32 seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) u32 class_locale_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) struct compat_megasas_iocpacket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) u16 host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) u16 __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) u32 sgl_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) u32 sge_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) u32 sense_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) u32 sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) u8 raw[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) struct megasas_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) } frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct compat_iovec sgl[MAX_IOCTL_SGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct megasas_mgmt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) u16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) int max_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) enum MEGASAS_OCR_CAUSE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) FW_FAULT_OCR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) SCSIIO_TIMEOUT_OCR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) MFI_IO_TIMEOUT_OCR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) enum DCMD_RETURN_STATUS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) DCMD_SUCCESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) DCMD_TIMEOUT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) DCMD_FAILED = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) DCMD_BUSY = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) DCMD_INIT = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) MR_BuildRaidContext(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) struct IO_REQUEST_INFO *io_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) struct RAID_CONTEXT *pRAID_Context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) __le16 get_updated_dev_handle(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) struct LD_LOAD_BALANCE_INFO *lbInfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) struct IO_REQUEST_INFO *in_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) struct MR_DRV_RAID_MAP_ALL *drv_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) struct LD_LOAD_BALANCE_INFO *lbInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) int megasas_get_ctrl_info(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* PD sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) bool is_target_prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) int megasas_get_target_prop(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) struct scsi_device *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) void megasas_get_snapdump_properties(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) int megasas_set_crash_dump_params(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) u8 crash_buf_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) void megasas_free_host_crash_buffer(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) void megasas_return_cmd_fusion(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) struct megasas_cmd_fusion *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) int megasas_issue_blocked_cmd(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) struct megasas_cmd *cmd, int timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) void __megasas_return_cmd(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct megasas_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) int megasas_cmd_type(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) void megasas_setup_jbod_map(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) void megasas_update_sdev_properties(struct scsi_device *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) u32 mega_mod64(u64 dividend, u32 divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) int megasas_alloc_fusion_context(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) void megasas_free_fusion_context(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) int megasas_fusion_start_watchdog(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) void megasas_set_dma_settings(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) struct megasas_dcmd_frame *dcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) dma_addr_t dma_addr, u32 dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) bool do_adp_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) int ocr_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) u32 megasas_readl(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) const volatile void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) struct megasas_cmd *megasas_get_cmd(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) void megasas_return_cmd(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) struct megasas_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) int megasas_issue_polled(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) struct megasas_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) void megaraid_sas_kill_hba(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) void megasas_check_and_restore_queue_depth(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) void megasas_start_timer(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) int megasas_sriov_start_heartbeat(struct megasas_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) int initial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) int megasas_alloc_cmds(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) void megasas_free_cmds(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) void megasas_init_debugfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) void megasas_exit_debugfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) void megasas_setup_debugfs(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) void megasas_destroy_debugfs(struct megasas_instance *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) #endif /*LSI_MEGARAID_SAS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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