^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Linux MegaRAID device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2003-2004 LSI Logic Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * FILE : megaraid_mbox.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _MEGARAID_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _MEGARAID_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "mega_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "mbox_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "megaraid_ioctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MEGARAID_VERSION "2.20.5.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MEGARAID_EXT_VERSION "(Release Date: Thu Nov 16 15:32:35 EST 2006)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Define some PCI values here until they are put in the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_DEVICE_ID_PERC4_SC 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_SUBSYS_ID_PERC4_SC 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_DEVICE_ID_PERC4_DC 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_SUBSYS_ID_PERC4_DC 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_VERDE 0x0407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_PERC4E_DI_KOBUK 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_SUBSYS_ID_PERC4E_DI_KOBUK 0x016d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_PERC4E_DI_CORVETTE 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE 0x016e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION 0x016f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_DOBSON 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_MEGARAID_SCSI_320_0 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0 0xA520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_MEGARAID_SCSI_320_1 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_MEGARAID_SCSI_320_2 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_DEVICE_ID_MEGARAID_I4_133_RAID 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID 0x0522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_MEGARAID_SATA_150_4 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_SUBSYS_ID_MEGARAID_SATA_150_4 0x4523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_MEGARAID_SATA_150_6 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_SUBSYS_ID_MEGARAID_SATA_150_6 0x0523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_LINDSAY 0x0409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_INTEL_RAID_SRCS16 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_SUBSYS_ID_INTEL_RAID_SRCS16 0x0523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCI_SUBSYS_ID_PERC3_QC 0x0471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_SUBSYS_ID_PERC3_DC 0x0493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCI_SUBSYS_ID_PERC3_SC 0x0475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCI_SUBSYS_ID_CERC_ATA100_4CH 0x0511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MBOX_MAX_SCSI_CMDS 128 // number of cmds reserved for kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MBOX_MAX_USER_CMDS 32 // number of cmds for applications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MBOX_DEF_CMD_PER_LUN 64 // default commands per lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MBOX_DEFAULT_SG_SIZE 26 // default sg size supported by all fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MBOX_MAX_SG_SIZE 32 // maximum scatter-gather list size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MBOX_MAX_SECTORS 128 // maximum sectors per IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MBOX_TIMEOUT 30 // timeout value for internal cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MBOX_BUSY_WAIT 10 // max usec to wait for busy mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MBOX_RESET_WAIT 180 // wait these many seconds in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MBOX_RESET_EXT_WAIT 120 // extended wait reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MBOX_SYNC_WAIT_CNT 0xFFFF // wait loop index for synchronous mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MBOX_SYNC_DELAY_200 200 // 200 micro-seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * maximum transfer that can happen through the firmware commands issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * internnaly from the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MBOX_IBUF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * mbox_ccb_t - command control block specific to mailbox based controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @raw_mbox : raw mailbox pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @mbox : mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @mbox64 : extended mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @mbox_dma_h : mailbox dma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @sgl64 : 64-bit scatter-gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @sgl32 : 32-bit scatter-gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @sgl_dma_h : dma handle for the scatter-gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @pthru : passthru structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @pthru_dma_h : dma handle for the passthru structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @epthru : extended passthru structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @epthru_dma_h : dma handle for extended passthru structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @buf_dma_h : dma handle for buffers w/o sg list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * command control block specific to the mailbox based controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint8_t *raw_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mbox_t *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mbox64_t *mbox64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dma_addr_t mbox_dma_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mbox_sgl64 *sgl64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mbox_sgl32 *sgl32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dma_addr_t sgl_dma_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mraid_passthru_t *pthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_addr_t pthru_dma_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mraid_epassthru_t *epthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dma_addr_t epthru_dma_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_addr_t buf_dma_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } mbox_ccb_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * mraid_device_t - adapter soft state structure for mailbox controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @una_mbox64 : 64-bit mbox - unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @una_mbox64_dma : mbox dma addr - unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @mbox : 32-bit mbox - aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @mbox64 : 64-bit mbox - aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @mbox_dma : mbox dma addr - aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @mailbox_lock : exclusion lock for the mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @baseport : base port of hba memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @baseaddr : mapped addr of hba memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @mbox_pool : pool of mailboxes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @mbox_pool_handle : handle for the mailbox pool memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @epthru_pool : a pool for extended passthru commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @epthru_pool_handle : handle to the pool above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @sg_pool : pool of scatter-gather lists for this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @sg_pool_handle : handle to the pool above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @ccb_list : list of our command control blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @uccb_list : list of cmd control blocks for mgmt module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @umbox64 : array of mailbox for user commands (cmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @pdrv_state : array for state of each physical drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @last_disp : flag used to show device scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @hw_error : set if FW not responding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @fast_load : If set, skip physical device scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @channel_class : channel class, RAID or SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @sysfs_mtx : mutex to serialize access to sysfs res.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @sysfs_uioc : management packet to issue FW calls from sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @sysfs_mbox64 : mailbox packet to issue FW calls from sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @sysfs_buffer : data buffer for FW commands issued from sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @sysfs_buffer_dma : DMA buffer for FW commands issued from sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @sysfs_wait_q : wait queue for sysfs operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @random_del_supported : set if the random deletion is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @curr_ldmap : current LDID map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Initialization structure for mailbox controllers: memory based and IO based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * All the fields in this structure are LLD specific and may be discovered at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * init() or start() time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * NOTE: The fields of this structures are placed to minimize cache misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MAX_LD_EXTENDED64 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mbox64_t *una_mbox64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dma_addr_t una_mbox64_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mbox_t *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mbox64_t *mbox64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dma_addr_t mbox_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spinlock_t mailbox_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long baseport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __iomem * baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mraid_pci_blk mbox_pool[MBOX_MAX_SCSI_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct dma_pool *mbox_pool_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mraid_pci_blk epthru_pool[MBOX_MAX_SCSI_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_pool *epthru_pool_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mraid_pci_blk sg_pool[MBOX_MAX_SCSI_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct dma_pool *sg_pool_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mbox_ccb_t ccb_list[MBOX_MAX_SCSI_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mbox_ccb_t uccb_list[MBOX_MAX_USER_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mbox64_t umbox64[MBOX_MAX_USER_CMDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) uint32_t last_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int hw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int fast_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) uint8_t channel_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct mutex sysfs_mtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uioc_t *sysfs_uioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mbox64_t *sysfs_mbox64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) caddr_t sysfs_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dma_addr_t sysfs_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wait_queue_head_t sysfs_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int random_del_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint16_t curr_ldmap[MAX_LD_EXTENDED64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } mraid_device_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) // route to raid device from adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ADAP2RAIDDEV(adp) ((mraid_device_t *)((adp)->raid_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MAILBOX_LOCK(rdev) (&(rdev)->mailbox_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) // Find out if this channel is a RAID or SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IS_RAID_CH(rdev, ch) (((rdev)->channel_class >> (ch)) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RDINDOOR(rdev) readl((rdev)->baseaddr + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RDOUTDOOR(rdev) readl((rdev)->baseaddr + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define WRINDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define WROUTDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif // _MEGARAID_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) // vim: set ts=8 sw=8 tw=78:
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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