Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * found on Power Macintosh computers, controlling the external SCSI chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _MAC53C94_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _MAC53C94_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Registers in the 53C94 controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct mac53c94_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	unsigned char	count_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	char pad0[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	unsigned char	count_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	char pad1[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	unsigned char	fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	char pad2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned char	command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	char pad3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned char	status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	char pad4[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned char	interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	char pad5[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned char	seqstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	char pad6[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned char	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	char pad7[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned char	config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	char pad8[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned char	clk_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	char pad9[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned char	test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	char pad10[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned char	config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	char pad11[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned char	config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	char pad12[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned char	config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	char pad13[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned char	count_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	char pad14[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned char	fifo_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	char pad15[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * Alternate functions for some registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define dest_id		status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define sel_timeout	interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define sync_period	seqstep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define sync_offset	flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Bits in command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CMD_DMA_MODE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CMD_MODE_MASK	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CMD_MODE_INIT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CMD_MODE_TARG	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CMD_MODE_DISC	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CMD_NOP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CMD_FLUSH	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CMD_RESET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CMD_SCSI_RESET	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CMD_XFER_DATA	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CMD_I_COMPLETE	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CMD_ACCEPT_MSG	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CMD_XFER_PAD	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CMD_SET_ATN	0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CMD_CLR_ATN	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CMD_SEND_MSG	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CMD_SEND_STATUS	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CMD_SEND_DATA	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CMD_DISC_SEQ	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CMD_TERMINATE	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CMD_T_COMPLETE	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CMD_DISCONNECT	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CMD_RECV_MSG	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CMD_RECV_CDB	0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CMD_RECV_DATA	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CMD_RECV_CMD	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CMD_ABORT_DMA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CMD_RESELECT	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CMD_SELECT	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CMD_SELECT_ATN	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CMD_SELATN_STOP	0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CMD_ENABLE_SEL	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CMD_DISABLE_SEL	0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CMD_SEL_ATN3	0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CMD_RESEL_ATN3	0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * Bits in status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STAT_IRQ	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STAT_ERROR	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STAT_PARITY	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STAT_TC_ZERO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STAT_DONE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STAT_PHASE	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STAT_MSG	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STAT_CD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STAT_IO		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * Bits in interrupt register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INTR_RESET	0x80	/* SCSI bus was reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INTR_ILL_CMD	0x40	/* illegal command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INTR_DISCONNECT	0x20	/* we got disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INTR_BUS_SERV	0x10	/* bus service requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INTR_DONE	0x08	/* function completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INTR_RESELECTED	0x04	/* we were reselected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INTR_SEL_ATN	0x02	/* we were selected, ATN asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INTR_SELECT	0x01	/* we were selected, ATN negated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Encoding for the select timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TIMO_VAL(x)	((x) * 5000 / 7682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Bits in sequence step register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SS_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SS_ARB_SEL	0	/* Selection & arbitration complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SS_MSG_SENT	1	/* One message byte sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SS_NOT_CMD	2	/* Not in command phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SS_PHASE_CHG	3	/* Early phase change, cmd bytes lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SS_DONE		4	/* Command was sent OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * Encoding for sync transfer period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SYNCP_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SYNCP_MIN	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SYNCP_MAX	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * Bits in flags register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FLAGS_FIFO_LEV	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FLAGS_SEQ_STEP	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * Encoding for sync offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SYNCO_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SYNCO_ASS_CTRL	0x30	/* REQ/ACK assertion control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SYNCO_NEG_CTRL	0xc0	/* REQ/ACK negation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * Bits in config1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CF1_SLOW_CABLE	0x80	/* Slow cable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CF1_NO_RES_REP	0x40	/* Disable SCSI reset reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CF1_PAR_TEST	0x20	/* Parity test mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CF1_PAR_ENABLE	0x10	/* Enable parity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CF1_TEST	0x08	/* Chip tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CF1_MY_ID	0x07	/* Controller's address on bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * Encoding for clk_factor register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLKF_MASK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLKF_VAL(freq)	((((freq) + 4999999) / 5000000) & CLKF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * Bits in test mode register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEST_TARGET	1	/* target test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEST_INITIATOR	2	/* initiator test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEST_TRISTATE	4	/* tristate (hi-z) test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * Bits in config2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CF2_RFB		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CF2_FEATURE_EN	0x40	/* enable features / phase latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CF2_BYTECTRL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CF2_DREQ_HIZ	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CF2_SCSI2	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CF2_PAR_ABORT	0x04	/* bad parity target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CF2_REG_PARERR	0x02	/* register parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CF2_DMA_PARERR	0x01	/* DMA parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * Bits in the config3 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CF3_ID_MSG_CHK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CF3_3B_MSGS	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CF3_CDB10	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CF3_FASTSCSI	0x10	/* enable fast SCSI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CF3_FASTCLOCK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CF3_SAVERESID	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CF3_ALT_DMA	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CF3_THRESH_8	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * Bits in the config4 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CF4_EAN		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CF4_TEST	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CF4_BBTE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif /* _MAC53C94_H */