Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SCSI low-level driver for the 53c94 SCSI bus adaptor found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * on Power Macintosh computers, controlling the external SCSI chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * We assume the 53c94 is connected to a DBDMA (descriptor-based DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Paul Mackerras, August 1996.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/macio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "mac53c94.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) enum fsc_phase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	selecting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	dataing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	completing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	busfreeing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct fsc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct	mac53c94_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	int	intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct	dbdma_regs __iomem *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int	dmaintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int	clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct	Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct scsi_cmnd *request_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct scsi_cmnd *request_qtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct scsi_cmnd *current_req;		/* req we're currently working on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	enum fsc_phase phase;		/* what we're currently trying to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct dbdma_cmd *dma_cmds;	/* space for dbdma commands, aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	void	*dma_cmd_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct	pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct macio_dev *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void mac53c94_init(struct fsc_state *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void mac53c94_start(struct fsc_state *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void mac53c94_interrupt(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static irqreturn_t do_mac53c94_interrupt(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void cmd_done(struct fsc_state *, int result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static void set_dma_cmds(struct fsc_state *, struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int mac53c94_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct fsc_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (cmd->sc_data_direction == DMA_TO_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		printk(KERN_DEBUG "mac53c94_queue %p: command is", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		for (i = 0; i < cmd->cmd_len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			printk(KERN_CONT " %.2x", cmd->cmnd[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		printk(KERN_DEBUG "use_sg=%d request_bufflen=%d request_buffer=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		       scsi_sg_count(cmd), scsi_bufflen(cmd), scsi_sglist(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	cmd->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	state = (struct fsc_state *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (state->request_q == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		state->request_q = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		state->request_qtail->host_scribble = (void *) cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	state->request_qtail = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (state->phase == idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		mac53c94_start(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static DEF_SCSI_QCMD(mac53c94_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int mac53c94_host_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct fsc_state *state = (struct fsc_state *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct mac53c94_regs __iomem *regs = state->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct dbdma_regs __iomem *dma = state->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_lock_irqsave(cmd->device->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writeb(CMD_SCSI_RESET, &regs->command);	/* assert RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	udelay(100);			/* leave it on for a while (>= 25us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	writeb(CMD_RESET, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	mac53c94_init(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	writeb(CMD_NOP, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	spin_unlock_irqrestore(cmd->device->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void mac53c94_init(struct fsc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct mac53c94_regs __iomem *regs = state->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct dbdma_regs __iomem *dma = state->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	writeb(state->host->this_id | CF1_PAR_ENABLE, &regs->config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	writeb(TIMO_VAL(250), &regs->sel_timeout);	/* 250ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	writeb(CLKF_VAL(state->clk_freq), &regs->clk_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	writeb(CF2_FEATURE_EN, &regs->config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	writeb(0, &regs->config3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writeb(0, &regs->sync_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	writeb(0, &regs->sync_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	x = readb(&regs->interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * Start the next command for a 53C94.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * Should be called with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void mac53c94_start(struct fsc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct mac53c94_regs __iomem *regs = state->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (state->phase != idle || state->current_req != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		panic("inappropriate mac53c94_start (state=%p)", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (state->request_q == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	state->current_req = cmd = state->request_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	state->request_q = (struct scsi_cmnd *) cmd->host_scribble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Off we go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	writeb(0, &regs->count_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	writeb(0, &regs->count_mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	writeb(0, &regs->count_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	writeb(CMD_FLUSH, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	writeb(cmd->device->id, &regs->dest_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	writeb(0, &regs->sync_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writeb(0, &regs->sync_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* load the command into the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (i = 0; i < cmd->cmd_len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		writeb(cmd->cmnd[i], &regs->fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* do select without ATN XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	writeb(CMD_SELECT, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	state->phase = selecting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	set_dma_cmds(state, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static irqreturn_t do_mac53c94_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct Scsi_Host *dev = ((struct fsc_state *) dev_id)->current_req->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spin_lock_irqsave(dev->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	mac53c94_interrupt(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	spin_unlock_irqrestore(dev->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void mac53c94_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct fsc_state *state = (struct fsc_state *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct mac53c94_regs __iomem *regs = state->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct dbdma_regs __iomem *dma = state->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct scsi_cmnd *cmd = state->current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int nb, stat, seq, intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	static int mac53c94_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * Apparently, reading the interrupt register unlatches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * the status and sequence step registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	seq = readb(&regs->seqstep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	stat = readb(&regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	intr = readb(&regs->interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	       intr, stat, seq, state->phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (intr & INTR_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		/* SCSI bus was reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		printk(KERN_INFO "external SCSI bus reset detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		writeb(CMD_NOP, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		writel(RUN << 16, &dma->control);	/* stop dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		cmd_done(state, DID_RESET << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (intr & INTR_ILL_CMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		       intr, stat, seq, state->phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (stat & STAT_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		/* XXX these seem to be harmless? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		printk("53c94: bad error, intr=%x stat=%x seq=%x phase=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		       intr, stat, seq, state->phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		++mac53c94_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (cmd == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		printk(KERN_DEBUG "53c94: interrupt with no command active?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (stat & STAT_PARITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		printk(KERN_ERR "mac53c94: parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		cmd_done(state, DID_PARITY << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	switch (state->phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case selecting:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (intr & INTR_DISCONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			/* selection timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			cmd_done(state, DID_BAD_TARGET << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (intr != INTR_BUS_SERV + INTR_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			printk(KERN_DEBUG "got intr %x during selection\n", intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if ((seq & SS_MASK) != SS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			printk(KERN_DEBUG "seq step %x after command\n", seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		writeb(CMD_NOP, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/* set DMA controller going if any data to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		if ((stat & (STAT_MSG|STAT_CD)) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		    && (scsi_sg_count(cmd) > 0 || scsi_bufflen(cmd))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			nb = cmd->SCp.this_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			if (nb > 0xfff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				nb = 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			cmd->SCp.this_residual -= nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			writeb(nb, &regs->count_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			writeb(nb >> 8, &regs->count_mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			writel(virt_to_phys(state->dma_cmds), &dma->cmdptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			writel((RUN << 16) | RUN, &dma->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			state->phase = dataing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		} else if ((stat & STAT_PHASE) == STAT_CD + STAT_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			/* up to status phase already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			writeb(CMD_I_COMPLETE, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			state->phase = completing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			printk(KERN_DEBUG "in unexpected phase %x after cmd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			       stat & STAT_PHASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case dataing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (intr != INTR_BUS_SERV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			printk(KERN_DEBUG "got intr %x before status\n", intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (cmd->SCp.this_residual != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		    && (stat & (STAT_MSG|STAT_CD)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			/* Set up the count regs to transfer more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			nb = cmd->SCp.this_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			if (nb > 0xfff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				nb = 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			cmd->SCp.this_residual -= nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			writeb(nb, &regs->count_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			writeb(nb >> 8, &regs->count_mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		if ((stat & STAT_PHASE) != STAT_CD + STAT_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			printk(KERN_DEBUG "intr %x before data xfer complete\n", intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		writel(RUN << 16, &dma->control);	/* stop dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		/* should check dma status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		writeb(CMD_I_COMPLETE, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		state->phase = completing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	case completing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		if (intr != INTR_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			printk(KERN_DEBUG "got intr %x on completion\n", intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			cmd_done(state, DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		cmd->SCp.Status = readb(&regs->fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		cmd->SCp.Message = readb(&regs->fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		cmd->result = CMD_ACCEPT_MSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		writeb(CMD_ACCEPT_MSG, &regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		state->phase = busfreeing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	case busfreeing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (intr != INTR_DISCONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			printk(KERN_DEBUG "got intr %x when expected disconnect\n", intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		cmd_done(state, (DID_OK << 16) + (cmd->SCp.Message << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			 + cmd->SCp.Status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		printk(KERN_DEBUG "don't know about phase %d\n", state->phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void cmd_done(struct fsc_state *state, int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	cmd = state->current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (cmd != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		cmd->result = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		(*cmd->scsi_done)(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		state->current_req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	state->phase = idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	mac53c94_start(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * Set up DMA commands for transferring data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void set_dma_cmds(struct fsc_state *state, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	int i, dma_cmd, total, nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct scatterlist *scl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct dbdma_cmd *dcmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	u32 dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	nseg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	BUG_ON(nseg < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (!nseg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	dma_cmd = cmd->sc_data_direction == DMA_TO_DEVICE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			OUTPUT_MORE : INPUT_MORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	dcmds = state->dma_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	scsi_for_each_sg(cmd, scl, nseg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dma_addr = sg_dma_address(scl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dma_len = sg_dma_len(scl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (dma_len > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			panic("mac53c94: scatterlist element >= 64k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		total += dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		dcmds->req_count = cpu_to_le16(dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dcmds->command = cpu_to_le16(dma_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		dcmds->phy_addr = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		dcmds->xfer_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		++dcmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dcmds[-1].command = cpu_to_le16(dma_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	dcmds->command = cpu_to_le16(DBDMA_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	cmd->SCp.this_residual = total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static struct scsi_host_template mac53c94_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.proc_name	= "53c94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.name		= "53C94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.queuecommand	= mac53c94_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.eh_host_reset_handler = mac53c94_host_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.can_queue	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.this_id	= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.sg_tablesize	= SG_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.max_segment_size = 65535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int mac53c94_probe(struct macio_dev *mdev, const struct of_device_id *match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct device_node *node = macio_get_of_node(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct pci_dev *pdev = macio_get_pci_dev(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	struct fsc_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	void *dma_cmd_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	const unsigned char *clkprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	int proplen, rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		printk(KERN_ERR "mac53c94: expected 2 addrs and intrs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		       " (got %d/%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		       macio_resource_count(mdev), macio_irq_count(mdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (macio_request_resources(mdev, "mac53c94") != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)        		printk(KERN_ERR "mac53c94: unable to request memory resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)        	host = scsi_host_alloc(&mac53c94_template, sizeof(struct fsc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	if (host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		printk(KERN_ERR "mac53c94: couldn't register host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		goto out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	state = (struct fsc_state *) host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	macio_set_drvdata(mdev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	state->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	state->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	state->mdev = mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	state->regs = (struct mac53c94_regs __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		ioremap(macio_resource_start(mdev, 0), 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	state->intr = macio_irq(mdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	state->dma = (struct dbdma_regs __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		ioremap(macio_resource_start(mdev, 1), 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	state->dmaintr = macio_irq(mdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (state->regs == NULL || state->dma == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		printk(KERN_ERR "mac53c94: ioremap failed for %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	clkprop = of_get_property(node, "clock-frequency", &proplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)        	if (clkprop == NULL || proplen != sizeof(int)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)        		printk(KERN_ERR "%pOF: can't get clock frequency, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)        		       "assuming 25MHz\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)        		state->clk_freq = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)        	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)        		state->clk_freq = *(int *)clkprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)        	/* Space for dma command list: +1 for stop command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)        	 * +1 to allow for aligning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	 * XXX FIXME: Use DMA consistent routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)        	dma_cmd_space = kmalloc_array(host->sg_tablesize + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 					     sizeof(struct dbdma_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 					     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)        	if (dma_cmd_space == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)        		printk(KERN_ERR "mac53c94: couldn't allocate dma "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)        		       "command space for %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)        		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)        	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	state->dma_cmds = (struct dbdma_cmd *)DBDMA_ALIGN(dma_cmd_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	memset(state->dma_cmds, 0, (host->sg_tablesize + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	       * sizeof(struct dbdma_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	state->dma_cmd_space = dma_cmd_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	mac53c94_init(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	if (request_irq(state->intr, do_mac53c94_interrupt, 0, "53C94",state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		printk(KERN_ERR "mac53C94: can't get irq %d for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		       state->intr, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		goto out_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	rc = scsi_add_host(host, &mdev->ofdev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		goto out_release_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	scsi_scan_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)  out_release_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	free_irq(state->intr, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)  out_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	kfree(state->dma_cmd_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)  out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (state->dma != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		iounmap(state->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (state->regs != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		iounmap(state->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)  out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	macio_release_resources(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int mac53c94_remove(struct macio_dev *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	struct fsc_state *fp = (struct fsc_state *)macio_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	struct Scsi_Host *host = fp->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	scsi_remove_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	free_irq(fp->intr, fp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (fp->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		iounmap(fp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	if (fp->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		iounmap(fp->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	kfree(fp->dma_cmd_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	macio_release_resources(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct of_device_id mac53c94_match[] = 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	.name 		= "53c94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_DEVICE_TABLE (of, mac53c94_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct macio_driver mac53c94_driver = 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		.name 		= "mac53c94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		.of_match_table	= mac53c94_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	.probe		= mac53c94_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	.remove		= mac53c94_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int __init init_mac53c94(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	return macio_register_driver(&mac53c94_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void __exit exit_mac53c94(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	return macio_unregister_driver(&mac53c94_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) module_init(init_mac53c94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) module_exit(exit_mac53c94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_DESCRIPTION("PowerMac 53c94 SCSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_LICENSE("GPL");