^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is part of the Emulex Linux Device Driver for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Fibre Channel Host Bus Adapters. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2016 Emulex. All rights reserved. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * EMULEX and SLI are trademarks of Emulex. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * www.broadcom.com *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of version 2 of the GNU General *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Public License as published by the Free Software Foundation. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * TO BE LEGALLY INVALID. See the GNU General Public License for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * more details, a copy of which can be found in the file COPYING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * included with this package. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq_poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPFC_ACTIVE_MBOX_WAIT_CNT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPFC_RPI_LOW_WATER_MARK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPFC_UNREG_FCF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPFC_SKIP_UNREG_FCF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Amount of time in seconds for waiting FCF rediscovery to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPFC_NEMBED_MBOX_SGL_CNT 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPFC_HBA_HDWQ_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPFC_HBA_HDWQ_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPFC_HBA_HDWQ_DEF LPFC_HBA_HDWQ_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* irq_chann range, values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPFC_IRQ_CHANN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPFC_IRQ_CHANN_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPFC_IRQ_CHANN_DEF LPFC_IRQ_CHANN_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* FCP MQ queue count limiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPFC_FCP_MQ_THRESHOLD_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPFC_FCP_MQ_THRESHOLD_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPFC_FCP_MQ_THRESHOLD_DEF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Provide the default FCF Record attributes used by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * when nonFIP mode is configured and there is no other default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * FCF Record attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LPFC_FCOE_FCF_DEF_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LPFC_FCOE_NULL_VID 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LPFC_FCOE_IGNORE_VID 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* First 3 bytes of default FCF MAC is specified by FC_MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LPFC_FCOE_FCF_MAC3 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LPFC_FCOE_FCF_MAC4 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LPFC_FCOE_FCF_MAC5 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LPFC_FCOE_FCF_MAP0 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LPFC_FCOE_FCF_MAP1 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LPFC_FCOE_FCF_MAP2 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LPFC_FCOE_MAX_RCV_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LPFC_FCOE_FKA_ADV_PER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LPFC_FCOE_FIP_PRIORITY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define sli4_sid_from_fc_hdr(fc_hdr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ((fc_hdr)->fh_s_id[0] << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (fc_hdr)->fh_s_id[1] << 8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (fc_hdr)->fh_s_id[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define sli4_did_from_fc_hdr(fc_hdr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ((fc_hdr)->fh_d_id[0] << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (fc_hdr)->fh_d_id[1] << 8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (fc_hdr)->fh_d_id[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define sli4_fctl_from_fc_hdr(fc_hdr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ((fc_hdr)->fh_f_ctl[0] << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (fc_hdr)->fh_f_ctl[1] << 8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (fc_hdr)->fh_f_ctl[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define sli4_type_from_fc_hdr(fc_hdr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ((fc_hdr)->fh_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INT_FW_UPGRADE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RUN_FW_UPGRADE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum lpfc_sli4_queue_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LPFC_EQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LPFC_GCQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) LPFC_MCQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LPFC_WCQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LPFC_RCQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) LPFC_MQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LPFC_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LPFC_HRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) LPFC_DRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* The queue sub-type defines the functional purpose of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum lpfc_sli4_queue_subtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LPFC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LPFC_MBOX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) LPFC_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LPFC_ELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) LPFC_NVMET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) LPFC_NVME_LS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LPFC_USOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* RQ buffer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct lpfc_rqb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint16_t entry_count; /* Current number of RQ slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint16_t buffer_count; /* Current number of buffers posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Callback for HBQ buffer allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Callback for HBQ buffer free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void (*rqb_free_buffer)(struct lpfc_hba *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct rqb_dmabuf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum lpfc_poll_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) LPFC_QUEUE_WORK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LPFC_IRQ_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct lpfc_idle_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 prev_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u64 prev_wall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct lpfc_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct list_head wq_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * If interrupts are in effect on _all_ the eq's the footprint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * of polling code is zero (except mode). This memory is chec-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * ked for every io to see if the io needs to be polled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * while completion to check if the eq's needs to be rearmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Keep in same cacheline as the queue ptr to avoid cpu fetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * stalls. Using 1B memory will leave us with 7B hole. Fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * it with other frequently used members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint16_t last_cpu; /* most recent cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uint16_t hdwq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint8_t qe_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint8_t mode; /* interrupt or polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LPFC_EQ_INTERRUPT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LPFC_EQ_POLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct list_head wqfull_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum lpfc_sli4_queue_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum lpfc_sli4_queue_subtype subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct lpfc_hba *phba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct list_head child_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct list_head page_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct list_head sgl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct list_head cpu_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uint32_t entry_count; /* Number of entries to support on the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uint32_t entry_size; /* Size of each queue entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uint32_t entry_cnt_per_pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint32_t notify_interval; /* Queue Notification Interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * For chip->host queues (EQ, CQ, RQ):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * specifies the interval (number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * entries) where the doorbell is rung to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * notify the chip of entry consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * For host->chip queues (WQ):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * specifies the interval (number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * entries) where consumption CQE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * requested to indicate WQ entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * consumed by the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Not used on an MQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LPFC_EQ_NOTIFY_INTRVL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LPFC_CQ_NOTIFY_INTRVL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LPFC_WQ_NOTIFY_INTRVL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LPFC_RQ_NOTIFY_INTRVL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) uint32_t max_proc_limit; /* Queue Processing Limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * For chip->host queues (EQ, CQ):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * specifies the maximum number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * entries to be consumed in one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * processing iteration sequence. Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * will be rearmed after each iteration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Not used on an MQ, RQ or WQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LPFC_EQ_MAX_PROC_LIMIT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LPFC_CQ_MIN_PROC_LIMIT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) uint32_t queue_claimed; /* indicates queue is being processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint32_t queue_id; /* Queue ID assigned by the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint32_t host_index; /* The host's index for putting or getting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint32_t hba_index; /* The last known hba index for get or put */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint32_t q_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint16_t page_count; /* Number of pages allocated for this queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint16_t page_size; /* size of page allocated for this queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define LPFC_EXPANDED_PAGE_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define LPFC_DEFAULT_PAGE_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uint16_t chann; /* Hardware Queue association WQ/CQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* CPU affinity for EQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define LPFC_FIND_BY_EQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LPFC_FIND_BY_HDWQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint8_t db_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LPFC_DB_RING_FORMAT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define LPFC_DB_LIST_FORMAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint8_t q_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HBA_EQ_DELAY_CHK 0x2 /* EQ is a candidate for coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define LPFC_NVMET_CQ_NOTIFY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void __iomem *db_regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint16_t dpp_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint16_t dpp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void __iomem *dpp_regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* For q stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint32_t q_cnt_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uint32_t q_cnt_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) uint32_t q_cnt_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint64_t q_cnt_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* defines for EQ stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EQ_max_eqe q_cnt_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EQ_no_entry q_cnt_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EQ_cqe_cnt q_cnt_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EQ_processed q_cnt_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* defines for CQ stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CQ_mbox q_cnt_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CQ_max_cqe q_cnt_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CQ_release_wqe q_cnt_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CQ_xri_aborted q_cnt_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CQ_wq q_cnt_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* defines for WQ stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define WQ_overflow q_cnt_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define WQ_posted q_cnt_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* defines for RQ stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RQ_no_posted_buf q_cnt_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RQ_no_buf_found q_cnt_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RQ_buf_posted q_cnt_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RQ_rcv_buf q_cnt_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct work_struct irqwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct work_struct spwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct delayed_work sched_irqwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct delayed_work sched_spwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uint64_t isr_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct lpfc_queue *assoc_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct list_head _poll_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void **q_pgs; /* array to index entries per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LPFC_IRQ_POLL_WEIGHT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct irq_poll iop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum lpfc_poll_mode poll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct lpfc_sli4_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint32_t speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint8_t duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint8_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint8_t number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint8_t fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uint32_t logical_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint16_t topology;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct lpfc_fcf_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint8_t fabric_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint8_t switch_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint8_t mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint16_t fcf_indx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint32_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint16_t vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint32_t addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint32_t flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define BOOT_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define RECORD_VALID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct lpfc_fcf_pri_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint16_t fcf_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define LPFC_FCF_ON_PRI_LIST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define LPFC_FCF_FLOGI_FAILED 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint16_t flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uint32_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct lpfc_fcf_pri {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct lpfc_fcf_pri_rec fcf_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Maximum FCF table index, it is for driver internal book keeping, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * just needs to be no less than the supported HBA's FCF table size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define LPFC_SLI4_FCF_TBL_INDX_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct lpfc_fcf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) uint16_t fcfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) uint32_t fcf_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FCF_AVAILABLE 0x01 /* FCF available for discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FCF_REGISTERED 0x02 /* FCF registered with FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FCF_SCAN_DONE 0x04 /* FCF table scan done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define FCF_IN_USE 0x08 /* Atleast one discovery completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) uint16_t fcf_redisc_attempted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) uint32_t addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint32_t eligible_fcf_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct lpfc_fcf_rec current_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct lpfc_fcf_rec failover_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct list_head fcf_pri_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uint32_t current_fcf_scan_pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct timer_list redisc_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define LPFC_REGION23_SIGNATURE "RG23"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define LPFC_REGION23_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define LPFC_REGION23_LAST_REC 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRIVER_SPECIFIC_TYPE 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define LINUX_DRIVER_ID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PORT_STE_TYPE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct lpfc_fip_param_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FCOE_PARAM_TYPE 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uint8_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FCOE_PARAM_LENGTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint8_t parm_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define FIPP_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint8_t parm_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define FIPP_MODE_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define FIPP_MODE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define FIPP_VLAN_VALID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct lpfc_fcoe_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uint8_t fc_map[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uint8_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) uint16_t vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct lpfc_fcf_conn_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define FCOE_CONN_TBL_TYPE 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint8_t length; /* words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct lpfc_fcf_conn_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define FCFCNCT_VALID 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define FCFCNCT_BOOT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define FCFCNCT_FBNM_VALID 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FCFCNCT_SWNM_VALID 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define FCFCNCT_VLAN_VALID 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define FCFCNCT_AM_VALID 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint16_t vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint8_t fabric_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint8_t switch_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct lpfc_fcf_conn_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct lpfc_fcf_conn_rec conn_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Define the host's bootstrap mailbox. This structure contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * the member attributes needed to create, use, and destroy the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * bootstrap mailbox region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * The macro definitions for the bmbx data structure are defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * in lpfc_hw4.h with the register definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct lpfc_bmbx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct lpfc_dmabuf *dmabuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct dma_address dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void *avirt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_addr_t aphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uint32_t bmbx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LPFC_EQE_SIZE_4B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define LPFC_EQE_SIZE_16B 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define LPFC_CQE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define LPFC_WQE_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define LPFC_WQE128_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define LPFC_MQE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LPFC_RQE_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LPFC_EQE_DEF_COUNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LPFC_CQE_DEF_COUNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define LPFC_CQE_EXP_COUNT 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LPFC_WQE_DEF_COUNT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define LPFC_WQE_EXP_COUNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define LPFC_MQE_DEF_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define LPFC_RQE_DEF_COUNT 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define LPFC_QUEUE_NOARM false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define LPFC_QUEUE_REARM true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * SLI4 CT field defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SLI4_CT_RPI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SLI4_CT_VPI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SLI4_CT_VFI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SLI4_CT_FCFI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * SLI4 specific data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct lpfc_max_cfg_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint16_t max_xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint16_t xri_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint16_t xri_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint16_t max_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint16_t rpi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint16_t rpi_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint16_t max_vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uint16_t vpi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint16_t vpi_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint16_t max_vfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint16_t vfi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint16_t vfi_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint16_t max_fcfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint16_t fcfi_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint16_t max_eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint16_t max_rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint16_t max_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint16_t max_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct lpfc_hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* SLI4 HBA multi-fcp queue handler struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define LPFC_SLI4_HANDLER_NAME_SZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct lpfc_hba_eq_hdl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint32_t idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint16_t irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct lpfc_hba *phba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct lpfc_queue *eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct cpumask aff_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define lpfc_get_eq_hdl(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define lpfc_get_aff_mask(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx].aff_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define lpfc_get_irq(eqidx) (phba->sli4_hba.hba_eq_hdl[eqidx].irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*BB Credit recovery value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct lpfc_bbscn_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define lpfc_bbscn_min_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define lpfc_bbscn_min_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define lpfc_bbscn_min_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define lpfc_bbscn_max_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define lpfc_bbscn_max_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define lpfc_bbscn_max_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define lpfc_bbscn_def_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define lpfc_bbscn_def_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define lpfc_bbscn_def_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Port Capabilities for SLI4 Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct lpfc_pc_sli4_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uint32_t supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint32_t if_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uint32_t sli_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) uint32_t sli_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) uint32_t featurelevel_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uint32_t featurelevel_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uint32_t proto_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define LPFC_SLI4_PROTO_FCOE 0x0000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LPFC_SLI4_PROTO_FC 0x0000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define LPFC_SLI4_PROTO_NIC 0x0000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define LPFC_SLI4_PROTO_ISCSI 0x0000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define LPFC_SLI4_PROTO_RDMA 0x0000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uint32_t sge_supp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint32_t if_page_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uint32_t rq_db_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uint32_t loopbk_scope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) uint32_t oas_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uint32_t eq_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uint32_t eqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uint32_t cq_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uint32_t cqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uint32_t mq_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) uint32_t mqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) uint32_t mq_elem_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) uint32_t wq_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) uint32_t wqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) uint32_t rq_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint32_t rqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint32_t hdr_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uint32_t hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) uint32_t hdr_pp_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint32_t sgl_pages_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint32_t sgl_pp_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) uint8_t cqv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) uint8_t mqv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) uint8_t wqv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) uint8_t rqv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint8_t eqav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint8_t cqav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint8_t wqsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint8_t bv1s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uint8_t pls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define LPFC_WQ_SZ64_SUPPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define LPFC_WQ_SZ128_SUPPORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint8_t wqpcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint8_t nvme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define LPFC_CQ_4K_PAGE_SZ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define LPFC_CQ_16K_PAGE_SZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define LPFC_WQ_4K_PAGE_SZ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define LPFC_WQ_16K_PAGE_SZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct lpfc_iov {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) uint32_t pf_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) uint32_t vf_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct lpfc_sli4_lnk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) uint8_t lnk_dv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define LPFC_LNK_DAT_INVAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define LPFC_LNK_DAT_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uint8_t lnk_tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define LPFC_LNK_GE 0x0 /* FCoE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define LPFC_LNK_FC 0x1 /* FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint8_t lnk_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uint8_t optic_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) LPFC_FOF_IO_CHAN_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Used for tracking CPU mapping attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct lpfc_vector_map_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint16_t phys_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uint16_t core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uint16_t eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint16_t hdwq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uint16_t flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define LPFC_CPU_MAP_HYPER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define LPFC_CPU_MAP_UNASSIGN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define LPFC_CPU_FIRST_IRQ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define LPFC_VECTOR_MAP_EMPTY 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Multi-XRI pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define XRI_BATCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct lpfc_pbl_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spinlock_t lock; /* lock for pbl_pool*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct lpfc_pvt_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 low_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 high_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spinlock_t lock; /* lock for pvt_pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct lpfc_multixri_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 xri_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Starting point when searching a pbl_pool with round-robin method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 rrb_next_hwqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Used by lpfc_adjust_pvt_pool_count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * io_req_count is incremented by 1 during IO submission. The heartbeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * handler uses these two variables to determine if pvt_pool is idle or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 prev_io_req_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 io_req_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 pbl_empty_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #ifdef LPFC_MXP_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 above_limit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 below_limit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 local_pbl_hit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 other_pbl_hit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 stat_max_hwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 stat_pbl_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 stat_pvt_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 stat_busy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 stat_snapshot_taken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* TODO: Separate pvt_pool into get and put list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct lpfc_fc4_ctrl_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 input_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 output_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 control_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 io_cmpls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #ifdef LPFC_HDWQ_LOCK_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct lpfc_lock_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint32_t alloc_xri_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint32_t alloc_xri_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint32_t free_xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint32_t wq_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint32_t alloc_pvt_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uint32_t mv_from_pvt_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint32_t mv_to_pub_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint32_t mv_to_pvt_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint32_t free_pub_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint32_t free_pvt_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct lpfc_eq_intr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uint32_t icnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* SLI4 HBA data structure entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct lpfc_sli4_hdw_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Pointers to the constructed SLI4 queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct lpfc_queue *hba_eq; /* Event queues for HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uint16_t io_cq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Keep track of IO buffers for this hardware queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct list_head lpfc_io_buf_list_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spinlock_t io_buf_list_put_lock; /* Common buf free list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct list_head lpfc_io_buf_list_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct list_head lpfc_abts_io_buf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint32_t total_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint32_t get_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint32_t put_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) uint32_t empty_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) uint32_t abts_scsi_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) uint32_t abts_nvme_io_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Multi-XRI pool per HWQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct lpfc_multixri_pool *p_multixri_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* FC-4 Stats counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct lpfc_fc4_ctrl_stat nvme_cstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct lpfc_fc4_ctrl_stat scsi_cstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #ifdef LPFC_HDWQ_LOCK_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct lpfc_lock_stat lock_conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Per HDWQ pool resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct list_head sgl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct list_head cmd_rsp_buf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Lock for syncing Per HDWQ pool resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spinlock_t hdwq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #ifdef LPFC_HDWQ_LOCK_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* compile time trylock stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int only_once = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) while (spin_trylock_irqsave(lock, flag) == 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (only_once) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) only_once = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) qp->lock_conflict.lstat++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define lpfc_qp_spin_lock(lock, qp, lstat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int only_once = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) while (spin_trylock(lock) == 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (only_once) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) only_once = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) qp->lock_conflict.lstat++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spin_lock_irqsave(lock, flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct lpfc_hdwq_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 hdwq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 rcv_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 xmt_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 cmpl_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct lpfc_sli4_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * config space registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * doorbell registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * dpp registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* IF Type 0, BAR 0 PCI cfg space reg mem map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void __iomem *UERRLOregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) void __iomem *UERRHIregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) void __iomem *UEMASKLOregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) void __iomem *UEMASKHIregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } if_type0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void __iomem *STATUSregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void __iomem *CTRLregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) void __iomem *ERR1regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) void __iomem *ERR2regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SLIPORT_ERR2_REG_FW_RESTART 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) void __iomem *EQDregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } if_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void __iomem *PSMPHRregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Well-known SLI INTF register memory map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) void __iomem *SLIINTFregaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* IF type 0, BAR 1 function CSR register memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void __iomem *ISRregaddr; /* HST_ISR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void __iomem *IMRregaddr; /* HST_IMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) void __iomem *ISCRregaddr; /* HST_ISCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) void __iomem *CQDBregaddr; /* CQ_DOORBELL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) void __iomem *EQDBregaddr; /* EQ_DOORBELL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) void __iomem *BMBXregaddr; /* BootStrap MBX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint32_t ue_mask_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) uint32_t ue_mask_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) uint32_t ue_to_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uint32_t ue_to_rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct lpfc_register sli_intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct lpfc_pc_sli4_params pc_sli4_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct lpfc_bbscn_params bbscn_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Pointers to the constructed SLI4 queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct lpfc_sli4_hdw_queue *hdwq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct list_head lpfc_wq_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Pointers to the constructed SLI4 queues for NVMET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct lpfc_name wwnn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct lpfc_name wwpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) uint32_t fw_func_mode; /* FW function protocol mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) uint32_t ulp0_mode; /* ULP0 protocol mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) uint32_t ulp1_mode; /* ULP1 protocol mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Optimized Access Storage specific queues/structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint64_t oas_next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) uint8_t oas_next_tgt_wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uint8_t oas_next_vpt_wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Setup information for various queue parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int eq_esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int eq_ecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int cq_esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int cq_ecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int wq_esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int wq_ecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int mq_esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int mq_ecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int rq_esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int rq_ecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define LPFC_SP_EQ_MAX_INTR_SEC 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define LPFC_FP_EQ_MAX_INTR_SEC 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint32_t intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct lpfc_bmbx bmbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct lpfc_max_cfg_param max_cfg_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint16_t extents_in_use; /* must allocate resource extents. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint16_t next_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint16_t io_xri_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint16_t io_xri_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint16_t io_xri_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) uint16_t els_xri_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) uint16_t nvmet_xri_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) uint16_t nvmet_io_wait_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) uint16_t nvmet_io_wait_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) uint16_t cq_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct lpfc_queue **cq_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct list_head lpfc_els_sgl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct list_head lpfc_abts_els_sgl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct list_head lpfc_abts_io_buf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct list_head lpfc_nvmet_sgl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct list_head lpfc_abts_nvmet_ctx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) spinlock_t t_active_list_lock; /* list of active NVMET IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct list_head t_active_ctx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct list_head lpfc_nvmet_io_wait_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct lpfc_sglq **lpfc_sglq_active_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct list_head lpfc_rpi_hdr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned long *rpi_bmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) uint16_t *rpi_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint16_t rpi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct list_head lpfc_rpi_blk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned long *xri_bmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint16_t *xri_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct list_head lpfc_xri_blk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned long *vfi_bmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uint16_t *vfi_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint16_t vfi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct list_head lpfc_vfi_blk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct lpfc_sli4_flags sli4_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct list_head sp_queue_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct list_head sp_cqe_event_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct list_head sp_asynce_work_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) spinlock_t asynce_list_lock; /* protect sp_asynce_work_queue list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct list_head sp_els_xri_aborted_work_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spinlock_t els_xri_abrt_list_lock; /* protect els_xri_aborted list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct list_head sp_unsol_work_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct lpfc_sli4_link link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct lpfc_sli4_lnk_info lnk_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) uint32_t pport_name_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define LPFC_SLI4_PPNAME_NON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define LPFC_SLI4_PPNAME_GET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct lpfc_iov iov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) spinlock_t sgl_list_lock; /* list of aborted els IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) uint32_t physical_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* CPU to vector mapping information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct lpfc_vector_map_info *cpu_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) uint16_t num_possible_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uint16_t num_present_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct cpumask irq_aff_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) uint16_t curr_disp_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct lpfc_eq_intr_info __percpu *eq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct lpfc_hdwq_stat __percpu *c_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct lpfc_idle_stat *idle_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint32_t conf_trunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define lpfc_conf_trunk_port0_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define lpfc_conf_trunk_port0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define lpfc_conf_trunk_port0_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define lpfc_conf_trunk_port1_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define lpfc_conf_trunk_port1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define lpfc_conf_trunk_port1_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define lpfc_conf_trunk_port2_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define lpfc_conf_trunk_port2_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define lpfc_conf_trunk_port2_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define lpfc_conf_trunk_port3_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define lpfc_conf_trunk_port3_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define lpfc_conf_trunk_port3_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define lpfc_conf_trunk_port0_nd_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define lpfc_conf_trunk_port0_nd_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define lpfc_conf_trunk_port0_nd_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define lpfc_conf_trunk_port1_nd_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define lpfc_conf_trunk_port1_nd_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define lpfc_conf_trunk_port1_nd_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define lpfc_conf_trunk_port2_nd_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define lpfc_conf_trunk_port2_nd_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define lpfc_conf_trunk_port2_nd_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define lpfc_conf_trunk_port3_nd_WORD conf_trunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define lpfc_conf_trunk_port3_nd_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define lpfc_conf_trunk_port3_nd_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) enum lpfc_sge_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) GEN_BUFF_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) SCSI_BUFF_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) NVMET_BUFF_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) enum lpfc_sgl_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SGL_FREED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) SGL_ALLOCATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SGL_XRI_ABORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct lpfc_sglq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* lpfc_sglqs are used in double linked lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct list_head clist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) enum lpfc_sge_type buff_type; /* is this a scsi sgl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) enum lpfc_sgl_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint16_t iotag; /* pre-assigned IO tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint16_t sli4_lxritag; /* logical pre-assigned xri. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sli4_sge *sgl; /* pre-assigned SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) void *virt; /* virtual address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dma_addr_t phys; /* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct lpfc_rpi_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct lpfc_dmabuf *dmabuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint32_t page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint32_t start_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint16_t next_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct lpfc_rsrc_blks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint16_t rsrc_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint16_t rsrc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uint16_t rsrc_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct lpfc_rdp_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct lpfc_nodelist *ndlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) uint16_t ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) uint16_t rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) READ_LNK_VAR link_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct lpfc_lcb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) uint8_t sub_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint8_t capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) uint8_t frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) uint16_t duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) uint16_t ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) uint16_t rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct lpfc_nodelist *ndlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * SLI4 specific function prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int lpfc_pci_function_reset(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int lpfc_sli4_hba_setup(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) uint8_t, uint32_t, bool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct lpfc_mbx_sge *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) void lpfc_sli4_hba_reset(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) uint32_t page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) uint32_t entry_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) uint32_t entry_count, int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void lpfc_sli4_queue_free(struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) uint32_t numq, uint32_t usdelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct lpfc_queue *, uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) uint32_t subtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct lpfc_queue *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct lpfc_queue *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct lpfc_queue *, struct lpfc_queue *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct lpfc_queue **drqp, struct lpfc_queue **cqp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) uint32_t subtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int lpfc_sli4_queue_setup(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) void lpfc_sli4_queue_unset(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) void lpfc_sli4_free_xri(struct lpfc_hba *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) void lpfc_sli4_remove_rpis(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) void lpfc_sli4_async_event_proc(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct sli4_wcqe_xri_aborted *axri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct lpfc_io_buf *lpfc_ncmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct sli4_wcqe_xri_aborted *axri, int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct sli4_wcqe_xri_aborted *axri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct sli4_wcqe_xri_aborted *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int lpfc_sli4_brdreset(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int lpfc_sli4_init_vpi(struct lpfc_vport *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) uint32_t count, bool arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int lpfc_sli4_post_status_check(struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct lpfc_io_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct lpfc_io_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct lpfc_io_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct lpfc_sli4_hdw_queue *hdwq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct lpfc_sli4_hdw_queue *hdwq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return q->q_pgs[idx / q->entry_cnt_per_pg] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) (q->entry_size * (idx % q->entry_cnt_per_pg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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