^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is part of the Emulex Linux Device Driver for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Fibre Channel Host Bus Adapters. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2016 Emulex. All rights reserved. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * EMULEX and SLI are trademarks of Emulex. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * www.broadcom.com *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of version 2 of the GNU General *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Public License as published by the Free Software Foundation. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * TO BE LEGALLY INVALID. See the GNU General Public License for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * more details, a copy of which can be found in the file COPYING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * included with this package. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FDMI_DID 0xfffffaU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NameServer_DID 0xfffffcU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define Fabric_Cntl_DID 0xfffffdU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define Fabric_DID 0xfffffeU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define Bcast_DID 0xffffffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define Mask_DID 0xffffffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CT_DID_MASK 0xffff00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define Fabric_DID_MASK 0xfff000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WELL_KNOWN_DID_MASK 0xfffff0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PT2PT_LocalID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PT2PT_RemoteID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FCELSSIZE 1024 /* maximum ELS transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLI2_IOCB_CMD_R3_ENTRIES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLI2_IOCB_RSP_R3_ENTRIES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLI2_IOCB_CMD_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLI2_IOCB_RSP_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLI3_IOCB_CMD_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLI3_IOCB_RSP_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* vendor ID used in SCSI netlink calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FW_REV_STR_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Common Transport structures and definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) union CtRevisionId {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) uint32_t Revision:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) uint32_t InId:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint32_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) union CtCommandResponse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uint32_t CmdRsp:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint32_t Size:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint32_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* FC4 Feature bits for RFF_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FC4_FEATURE_TARGET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FC4_FEATURE_INIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FC4_FEATURE_NVME_DISC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct lpfc_sli_ct_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) union CtRevisionId RevisionId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uint8_t FsType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) uint8_t FsSubType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint8_t Options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint8_t Rsrvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) union CtCommandResponse CommandResponse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint8_t Rsrvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint8_t ReasonCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint8_t Explanation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint8_t VendorUnique;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint32_t PortID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct gid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t PortType; /* for GID_PT requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GID_PT_N_PORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) uint8_t DomainScope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint8_t AreaScope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint8_t Fc4Type; /* for GID_FT requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } gid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gid_ff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint8_t Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint8_t DomainScope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint8_t AreaScope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint8_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint8_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint8_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint8_t Fc4FBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint8_t Fc4Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } gid_ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct rft {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t PortId; /* For RFT_ID requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uint32_t rsvd0:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint32_t rsvd1:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint32_t fcpReg:1; /* Type 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint32_t rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint32_t ipReg:1; /* Type 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint32_t rsvd3:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t rsvd0:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uint32_t fcpReg:1; /* Type 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uint32_t rsvd1:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) uint32_t rsvd3:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uint32_t ipReg:1; /* Type 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) uint32_t rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint32_t rsvd[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } rft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct rnn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint32_t PortId; /* For RNN_ID requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } rnn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct rsnn { /* For RSNN_ID requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) uint8_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) uint8_t symbname[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } rsnn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct da_id { /* For DA_ID requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint32_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } da_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct rspn { /* For RSPN_ID requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint32_t PortId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint8_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint8_t symbname[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } rspn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct gff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint32_t PortId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } gff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct gff_acc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) uint8_t fbits[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } gff_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct gft {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) uint32_t PortId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } gft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct gft_acc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uint32_t fc4_types[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } gft_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FCP_TYPE_FEATURE_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct rff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint32_t PortId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) uint8_t fbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uint8_t type_code; /* type=8 for FCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } rff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LPFC_MAX_CT_SIZE (60 * 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SLI_CT_REVISION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sizeof(struct gid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sizeof(struct gid_ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sizeof(struct gff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sizeof(struct gft))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sizeof(struct rft))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sizeof(struct rff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sizeof(struct rnn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sizeof(struct rsnn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sizeof(struct da_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sizeof(struct rspn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * FsType Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SLI_CT_MANAGEMENT_SERVICE 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SLI_CT_TIME_SERVICE 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SLI_CT_DIRECTORY_SERVICE 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Directory Service Subtypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Response Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SLI_CT_RESPONSE_FS_RJT 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SLI_CT_RESPONSE_FS_ACC 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Reason Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SLI_CT_INVALID_COMMAND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SLI_CT_INVALID_VERSION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SLI_CT_LOGICAL_ERROR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SLI_CT_INVALID_IU_SIZE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SLI_CT_LOGICAL_BUSY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SLI_CT_PROTOCOL_ERROR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SLI_CT_VENDOR_UNIQUE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SLI_CT_NO_PORT_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SLI_CT_NO_PORT_NAME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SLI_CT_NO_NODE_NAME 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SLI_CT_NO_IP_ADDRESS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SLI_CT_NO_IPA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SLI_CT_NO_FC4_TYPES 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SLI_CT_NO_PORT_TYPE 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SLI_CT_ACCESS_DENIED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SLI_CT_INVALID_PORT_ID 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SLI_CT_DATABASE_EMPTY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Name Server Command Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SLI_CTNS_GA_NXT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SLI_CTNS_GPN_ID 0x0112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SLI_CTNS_GNN_ID 0x0113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SLI_CTNS_GCS_ID 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SLI_CTNS_GFT_ID 0x0117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SLI_CTNS_GSPN_ID 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SLI_CTNS_GPT_ID 0x011A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SLI_CTNS_GFF_ID 0x011F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SLI_CTNS_GID_PN 0x0121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SLI_CTNS_GID_NN 0x0131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SLI_CTNS_GIP_NN 0x0135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SLI_CTNS_GIPA_NN 0x0136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SLI_CTNS_GSNN_NN 0x0139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SLI_CTNS_GNN_IP 0x0153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SLI_CTNS_GIPA_IP 0x0156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SLI_CTNS_GID_FT 0x0171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SLI_CTNS_GID_FF 0x01F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SLI_CTNS_GID_PT 0x01A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SLI_CTNS_RPN_ID 0x0212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SLI_CTNS_RNN_ID 0x0213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SLI_CTNS_RCS_ID 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SLI_CTNS_RFT_ID 0x0217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SLI_CTNS_RSPN_ID 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SLI_CTNS_RPT_ID 0x021A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SLI_CTNS_RFF_ID 0x021F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SLI_CTNS_RIP_NN 0x0235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SLI_CTNS_RIPA_NN 0x0236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SLI_CTNS_RSNN_NN 0x0239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SLI_CTNS_DA_ID 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Port Types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SLI_CTPT_N_PORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SLI_CTPT_NL_PORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SLI_CTPT_FNL_PORT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SLI_CTPT_IP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SLI_CTPT_FCP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SLI_CTPT_NVME 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SLI_CTPT_NX_PORT 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SLI_CTPT_F_PORT 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SLI_CTPT_FL_PORT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SLI_CTPT_E_PORT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SLI_CT_LAST_ENTRY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Fibre Channel Service Parameter definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define FC_PH_4_0 6 /* FC-PH version 4.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FC_PH_4_1 7 /* FC-PH version 4.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FC_PH_4_2 8 /* FC-PH version 4.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FC_PH_4_3 9 /* FC-PH version 4.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define FC_PH3 0x20 /* FC-PH-3 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FF_FRAME_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct lpfc_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint8_t nameType:4; /* FC Word 0, bit 28:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 8:11 of IEEE ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 8:11 of IEEE ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) uint8_t nameType:4; /* FC Word 0, bit 28:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define NAME_IEEE 0x1 /* IEEE name - nameType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define NAME_FC_TYPE 0x3 /* FC native name type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define NAME_IP_TYPE 0x4 /* IP address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define NAME_CCITT_TYPE 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define NAME_CCITT_GR_TYPE 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) extended Lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) uint8_t IEEE[6]; /* FC IEEE address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uint8_t wwn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) uint64_t name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct csp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint8_t fcphHigh; /* FC Word 0, byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint8_t fcphLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint8_t bbCreditMsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Word 1 Bit 31 in common service parameter is overloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Word 1 Bit 31 in FLOGI request is multiple NPort request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Word 1 Bit 31 in FLOGI response is clean address bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Word 1 Bit 30 in common service parameter is overloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Word 1 Bit 30 in PLOGI request is random offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Word 1 Bit 29 in common service parameter is overloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint16_t randomOffset:1; /* FC Word 1, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) uint16_t fPort:1; /* FC Word 1, bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint16_t multicast:1; /* FC Word 1, bit 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint16_t broadcast:1; /* FC Word 1, bit 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint16_t huntgroup:1; /* FC Word 1, bit 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint16_t simplex:1; /* FC Word 1, bit 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint16_t dhd:1; /* FC Word 1, bit 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint16_t payloadlength:1; /* FC Word 1, bit 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) uint16_t broadcast:1; /* FC Word 1, bit 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint16_t multicast:1; /* FC Word 1, bit 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uint16_t fPort:1; /* FC Word 1, bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) uint16_t randomOffset:1; /* FC Word 1, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint16_t payloadlength:1; /* FC Word 1, bit 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint16_t dhd:1; /* FC Word 1, bit 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint16_t simplex:1; /* FC Word 1, bit 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uint16_t huntgroup:1; /* FC Word 1, bit 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uint8_t word2Reserved1; /* FC Word 2 byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } nPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } w2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct class_parms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uint8_t classValid:1; /* FC Word 0, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint8_t intermix:1; /* FC Word 0, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint8_t intermix:1; /* FC Word 0, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint8_t classValid:1; /* FC Word 0, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct serv_parm { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct csp cmn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct lpfc_name portName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct lpfc_name nodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct class_parms cls1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct class_parms cls2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct class_parms cls3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct class_parms cls4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uint8_t vendorVersion[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uint32_t vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define LPFC_VV_SUPPRESS_RSP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } vv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Virtual Fabric Tagging Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct fc_vft_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define fc_vft_hdr_r_ctl_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define fc_vft_hdr_r_ctl_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define fc_vft_hdr_r_ctl_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define fc_vft_hdr_ver_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define fc_vft_hdr_ver_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define fc_vft_hdr_ver_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define fc_vft_hdr_type_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define fc_vft_hdr_type_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define fc_vft_hdr_type_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define fc_vft_hdr_e_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define fc_vft_hdr_e_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define fc_vft_hdr_e_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define fc_vft_hdr_priority_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define fc_vft_hdr_priority_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define fc_vft_hdr_priority_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define fc_vft_hdr_vf_id_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define fc_vft_hdr_vf_id_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define fc_vft_hdr_vf_id_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint32_t word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define fc_vft_hdr_hopct_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define fc_vft_hdr_hopct_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define fc_vft_hdr_hopct_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #include <uapi/scsi/fc/fc_els.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Extended Link Service LS_COMMAND codes (Payload Word 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define ELS_CMD_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define ELS_RSP_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define ELS_CMD_LS_RJT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ELS_CMD_ACC 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define ELS_CMD_PLOGI 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ELS_CMD_FLOGI 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ELS_CMD_LOGO 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define ELS_CMD_ABTX 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define ELS_CMD_RCS 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define ELS_CMD_RES 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define ELS_CMD_RSS 0x09000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define ELS_CMD_RSI 0x0A000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define ELS_CMD_ESTS 0x0B000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define ELS_CMD_ESTC 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define ELS_CMD_ADVC 0x0D000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define ELS_CMD_RTV 0x0E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define ELS_CMD_RLS 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define ELS_CMD_ECHO 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define ELS_CMD_TEST 0x11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ELS_CMD_RRQ 0x12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ELS_CMD_REC 0x13000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ELS_CMD_RDP 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define ELS_CMD_RDF 0x19000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define ELS_CMD_PRLI 0x20100014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define ELS_CMD_NVMEPRLI 0x20140018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define ELS_CMD_PRLO 0x21100014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define ELS_CMD_PRLO_ACC 0x02100014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define ELS_CMD_PDISC 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define ELS_CMD_FDISC 0x51000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define ELS_CMD_ADISC 0x52000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define ELS_CMD_FARP 0x54000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ELS_CMD_FARPR 0x55000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define ELS_CMD_RPL 0x57000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define ELS_CMD_FAN 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define ELS_CMD_RSCN 0x61040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define ELS_CMD_RSCN_XMT 0x61040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define ELS_CMD_SCR 0x62000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define ELS_CMD_RNID 0x78000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define ELS_CMD_LIRR 0x7A000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define ELS_CMD_LCB 0x81000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define ELS_CMD_FPIN 0x16000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define ELS_CMD_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define ELS_RSP_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define ELS_CMD_LS_RJT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define ELS_CMD_ACC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define ELS_CMD_PLOGI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ELS_CMD_FLOGI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ELS_CMD_LOGO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ELS_CMD_ABTX 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define ELS_CMD_RCS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ELS_CMD_RES 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ELS_CMD_RSS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ELS_CMD_RSI 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ELS_CMD_ESTS 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define ELS_CMD_ESTC 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define ELS_CMD_ADVC 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define ELS_CMD_RTV 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define ELS_CMD_RLS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define ELS_CMD_ECHO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define ELS_CMD_TEST 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define ELS_CMD_RRQ 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ELS_CMD_REC 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ELS_CMD_RDP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ELS_CMD_RDF 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ELS_CMD_PRLI 0x14001020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define ELS_CMD_NVMEPRLI 0x18001420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define ELS_CMD_PRLO 0x14001021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define ELS_CMD_PRLO_ACC 0x14001002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define ELS_CMD_PDISC 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ELS_CMD_FDISC 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define ELS_CMD_ADISC 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ELS_CMD_FARP 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define ELS_CMD_FARPR 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ELS_CMD_RPL 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ELS_CMD_FAN 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ELS_CMD_RSCN 0x0461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define ELS_CMD_RSCN_XMT 0x08000461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define ELS_CMD_SCR 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define ELS_CMD_RNID 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ELS_CMD_LIRR 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ELS_CMD_LCB 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define ELS_CMD_FPIN ELS_FPIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * LS_RJT Payload Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct ls_rjt { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) uint32_t lsRjtError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* LS_RJT reason codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define LSRJT_INVALID_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define LSRJT_LOGICAL_ERR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define LSRJT_LOGICAL_BSY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define LSRJT_PROTOCOL_ERR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define LSRJT_CMD_UNSUPPORTED 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* LS_RJT reason explanation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define LSEXP_NOTHING_MORE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define LSEXP_SPARM_OPTIONS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define LSEXP_SPARM_ICTL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define LSEXP_SPARM_RCTL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define LSEXP_SPARM_RCV_SIZE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define LSEXP_SPARM_CONCUR_SEQ 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define LSEXP_SPARM_CREDIT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define LSEXP_INVALID_PNAME 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define LSEXP_INVALID_NNAME 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define LSEXP_INVALID_CSP 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define LSEXP_INVALID_ASSOC_HDR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define LSEXP_ASSOC_HDR_REQ 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define LSEXP_INVALID_O_SID 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define LSEXP_INVALID_OX_RX 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define LSEXP_CMD_IN_PROGRESS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define LSEXP_PORT_LOGIN_REQ 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define LSEXP_INVALID_NPORT_ID 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define LSEXP_INVALID_SEQ_ID 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define LSEXP_INVALID_XCHG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define LSEXP_INACTIVE_XCHG 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define LSEXP_RQ_REQUIRED 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define LSEXP_OUT_OF_RESOURCE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define LSEXP_CANT_GIVE_DATA 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define LSEXP_REQ_UNSUPPORTED 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * N_Port Login (FLOGO/PLOGO Request) Payload Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) typedef struct _LOGO { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint32_t nPortId32; /* Access nPortId as a word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct lpfc_name portName; /* N_port name field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) } LOGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * FCP Login (PRLI Request / ACC) Payload Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define PRLX_PAGE_LEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define TPRLO_PAGE_LEN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) typedef struct _PRLI { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define PRLI_FCP_TYPE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define PRLI_NVME_TYPE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* ACC = imagePairEstablished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* ACC = imagePairEstablished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define PRLI_NO_RESOURCES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PRLI_INIT_INCOMPLETE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PRLI_NO_SUCH_PA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PRLI_PREDEF_CONFIG 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PRLI_PARTIAL_SUCCESS 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PRLI_INVALID_PAGE_CNT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } PRLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * FCP Logout (PRLO Request / ACC) Payload Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) typedef struct _PRLO { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define PRLO_FCP_TYPE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define PRLO_NO_SUCH_IMAGE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define PRLO_INVALID_PAGE_CNT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } PRLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) typedef struct _ADISC { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) uint32_t hardAL_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct lpfc_name portName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct lpfc_name nodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uint32_t DID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) } __packed ADISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) typedef struct _FARP { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint32_t Mflags:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) uint32_t Odid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define FARP_NO_ACTION 0 /* FARP information enclosed, no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint32_t Rflags:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint32_t Rdid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct lpfc_name OportName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct lpfc_name OnodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct lpfc_name RportName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct lpfc_name RnodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) uint8_t Oipaddr[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uint8_t Ripaddr[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) } FARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) typedef struct _FAN { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint32_t Fdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct lpfc_name FportName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct lpfc_name FnodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } __packed FAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) typedef struct _SCR { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint8_t resvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint8_t resvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint8_t resvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint8_t Function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define SCR_FUNC_FABRIC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define SCR_FUNC_NPORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SCR_FUNC_FULL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SCR_CLEAR 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) typedef struct _RNID_TOP_DISC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct lpfc_name portName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) uint8_t resvd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) uint32_t unitType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define RNID_HBA 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define RNID_HOST 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define RNID_DRIVER 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uint32_t physPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uint32_t attachedNodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uint16_t ipVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define RNID_IPV4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define RNID_IPV6 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) uint16_t UDPport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) uint8_t ipAddr[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uint16_t resvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define RNID_TD_SUPPORT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define RNID_LP_VALID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } RNID_TOP_DISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) typedef struct _RNID { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint8_t Format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define RNID_TOPOLOGY_DISC 0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint8_t CommonLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint8_t resvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) uint8_t SpecificLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct lpfc_name portName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct lpfc_name nodeName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) } __packed RNID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct RLS { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) uint32_t rls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define rls_rsvd_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define rls_rsvd_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define rls_rsvd_WORD rls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define rls_did_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define rls_did_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define rls_did_WORD rls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct RLS_RSP { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) uint32_t linkFailureCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) uint32_t lossSyncCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) uint32_t lossSignalCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) uint32_t primSeqErrCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) uint32_t invalidXmitWord;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uint32_t crcCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct RRQ { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) uint32_t rrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define rrq_rsvd_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define rrq_rsvd_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define rrq_rsvd_WORD rrq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define rrq_did_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define rrq_did_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define rrq_did_WORD rrq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint32_t rrq_exchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define rrq_oxid_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define rrq_oxid_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define rrq_oxid_WORD rrq_exchg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define rrq_rxid_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define rrq_rxid_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define rrq_rxid_WORD rrq_exchg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct RTV_RSP { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) uint32_t ratov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) uint32_t edtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) uint32_t qtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define qtov_rsvd0_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define qtov_rsvd0_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define qtov_rsvd0_WORD qtov /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define qtov_edtovres_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define qtov_edtovres_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define qtov__rsvd1_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define qtov_rsvd1_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define qtov_rsvd1_WORD qtov /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define qtov_rttov_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define qtov_rttov_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define qtov_rttov_WORD qtov /* R_T_TOV value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define qtov_rsvd2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define qtov_rsvd2_MASK 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define qtov_rsvd2_WORD qtov /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) typedef struct _RPL { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) uint32_t maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) uint32_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } RPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) typedef struct _PORT_NUM_BLK {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uint32_t portNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uint32_t portID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct lpfc_name portName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) } PORT_NUM_BLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) typedef struct _RPL_RSP { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint32_t listLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint32_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PORT_NUM_BLK port_num_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } RPL_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* This is used for RSCN command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) typedef struct _D_ID { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) uint32_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint8_t resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) uint8_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) uint8_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint8_t resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) } D_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define RSCN_ADDRESS_FORMAT_PORT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define RSCN_ADDRESS_FORMAT_AREA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define RSCN_ADDRESS_FORMAT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Structure to define all ELS Payload types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) typedef struct _ELS_PKT { /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint8_t elsCode; /* FC Word 0, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) uint8_t elsByte1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) uint8_t elsByte2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) uint8_t elsByte3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PRLI prli; /* Payload for PRLI/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PRLO prlo; /* Payload for PRLO/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ADISC adisc; /* Payload for ADISC/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) FARP farp; /* Payload for FARP/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) FAN fan; /* Payload for FAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SCR scr; /* Payload for SCR/ACC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) RNID rnid; /* Payload for RNID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) } ELS_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * Link Cable Beacon (LCB) ELS Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct fc_lcb_request_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) uint32_t lcb_command; /* ELS command opcode (0x81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define LPFC_LCB_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define LPFC_LCB_OFF 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define LPFC_LCB_GREEN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define LPFC_LCB_AMBER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define LCB_CAPABILITY_DURATION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define BEACON_VERSION_V1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define BEACON_VERSION_V0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * Link Cable Beacon (LCB) ELS Response Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct fc_lcb_res_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Read Diagnostic Parameters (RDP) ELS frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SFF_PG0_IDENT_SFP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define SFP_FLAG_PT_OPTICAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define SFP_FLAG_PT_SWLASER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SFP_FLAG_PT_LWLASER_LC1310 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SFP_FLAG_PT_LWLASER_LL1550 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define SFP_FLAG_PT_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SFP_FLAG_PT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define SFP_FLAG_IS_OPTICAL_PORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SFP_FLAG_IS_OPTICAL_MASK 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SFP_FLAG_IS_OPTICAL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define SFP_FLAG_IS_DESC_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define SFP_FLAG_CT_UNKNOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define SFP_FLAG_CT_SFP_PLUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define SFP_FLAG_CT_MASK 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define SFP_FLAG_CT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct fc_rdp_port_name_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) uint8_t wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * Link Error Status Block Structure (FC-FS-3) for RDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * This similar to RPS ELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct fc_link_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) uint32_t link_failure_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) uint32_t loss_of_synch_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) uint32_t loss_of_signal_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) uint32_t primitive_seq_proto_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) uint32_t invalid_trans_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) uint32_t invalid_crc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define RDP_PORT_NAMES_DESC_TAG 0x00010003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct fc_rdp_port_name_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) uint32_t tag; /* 0001 0003h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) uint32_t length; /* set to size of payload struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct fc_rdp_port_name_info port_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct fc_rdp_fec_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) uint32_t CorrectedBlocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) uint32_t UncorrectableBlocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define RDP_FEC_DESC_TAG 0x00010005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct fc_fec_rdp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct fc_rdp_fec_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct fc_rdp_link_error_status_payload_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct fc_link_status link_status; /* 24 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) uint32_t port_type; /* bits 31-30 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct fc_rdp_link_error_status_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) uint32_t tag; /* 0001 0002h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) uint32_t length; /* set to size of payload struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct fc_rdp_link_error_status_payload_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define VN_PT_PHY_UNKNOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define VN_PT_PHY_PF_PORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define VN_PT_PHY_ETH_MAC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define VN_PT_PHY_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define RDP_PS_1GB 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define RDP_PS_2GB 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define RDP_PS_4GB 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define RDP_PS_10GB 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define RDP_PS_8GB 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define RDP_PS_16GB 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define RDP_PS_32GB 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define RDP_PS_64GB 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define RDP_PS_128GB 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define RDP_PS_256GB 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define RDP_CAP_USER_CONFIGURED 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define RDP_CAP_UNKNOWN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define RDP_PS_UNKNOWN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define RDP_PS_NOT_ESTABLISHED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct fc_rdp_port_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) uint16_t capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) uint16_t speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct fc_rdp_port_speed_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct fc_rdp_port_speed port_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define RDP_PORT_SPEED_DESC_TAG 0x00010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct fc_rdp_port_speed_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) uint32_t tag; /* 00010001h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) uint32_t length; /* set to size of payload struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct fc_rdp_port_speed_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define RDP_NPORT_ID_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define RDP_N_PORT_DESC_TAG 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct fc_rdp_nport_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) uint32_t tag; /* 0000 0003h, big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) uint32_t length; /* size of RDP_N_PORT_ID struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) uint32_t nport_id : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) uint32_t reserved : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct fc_rdp_link_service_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) uint32_t els_req; /* Request payload word 0 value.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct fc_rdp_link_service_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) uint32_t tag; /* Descriptor tag 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) uint32_t length; /* set to size of payload struct. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct fc_rdp_link_service_info payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* must be ELS req Word 0(0x18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct fc_rdp_sfp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) uint16_t temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) uint16_t vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) uint16_t tx_bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) uint16_t tx_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) uint16_t rx_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define RDP_SFP_DESC_TAG 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct fc_rdp_sfp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) uint32_t length; /* set to size of sfp_info struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct fc_rdp_sfp_info sfp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Buffer Credit Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct fc_rdp_bbc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) uint32_t attached_port_bbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) uint32_t rtt; /* Round trip time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define RDP_BBC_DESC_TAG 0x00010006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct fc_rdp_bbc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct fc_rdp_bbc_info bbc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* Optical Element Type Transgression Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define RDP_OET_LOW_WARNING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define RDP_OET_HIGH_WARNING 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define RDP_OET_LOW_ALARM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define RDP_OET_HIGH_ALARM 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define RDP_OED_TEMPERATURE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define RDP_OED_VOLTAGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define RDP_OED_TXBIAS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define RDP_OED_TXPOWER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define RDP_OED_RXPOWER 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define RDP_OED_TYPE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Optical Element Data descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct fc_rdp_oed_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) uint16_t hi_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) uint16_t lo_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) uint16_t hi_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) uint16_t lo_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) uint32_t function_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define RDP_OED_DESC_TAG 0x00010007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct fc_rdp_oed_sfp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct fc_rdp_oed_info oed_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* Optical Product Data descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct fc_rdp_opd_sfp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) uint8_t vendor_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) uint8_t model_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) uint8_t serial_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) uint8_t revision[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) uint8_t date[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define RDP_OPD_DESC_TAG 0x00010008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct fc_rdp_opd_sfp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct fc_rdp_opd_sfp_info opd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct fc_rdp_req_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) uint32_t rdp_command; /* ELS command opcode (0x18)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) uint32_t rdp_des_length; /* RDP Payload Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct fc_rdp_res_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) uint32_t length; /* FC Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /******** FDMI ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Definitions for HBA / Port attribute entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Attribute Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct lpfc_fdmi_attr_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) uint32_t AttrInt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) uint8_t AttrTypes[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) uint8_t AttrString[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct lpfc_name AttrWWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct lpfc_fdmi_attr_def { /* Defined in TLV format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Structure is in Big Endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) uint32_t AttrType:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) uint32_t AttrLen:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Marks start of Value (ATTRIBUTE_ENTRY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct lpfc_fdmi_attr_entry AttrValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * HBA Attribute Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct lpfc_fdmi_attr_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) uint32_t EntryCnt; /* Number of HBA attribute entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * Port Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct lpfc_fdmi_port_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct lpfc_name PortName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * HBA Identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct lpfc_fdmi_hba_ident {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct lpfc_name PortName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * Registered Port List Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct lpfc_fdmi_reg_port_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) uint32_t EntryCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct lpfc_fdmi_port_entry pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * Register HBA(RHBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct lpfc_fdmi_reg_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct lpfc_fdmi_hba_ident hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct lpfc_fdmi_reg_port_list rpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * Register HBA Attributes (RHAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct lpfc_fdmi_reg_hbaattr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct lpfc_name HBA_PortName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct lpfc_fdmi_attr_block ab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Register Port Attributes (RPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct lpfc_fdmi_reg_portattr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct lpfc_name PortName;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct lpfc_fdmi_attr_block ab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * HBA MAnagement Operations Command Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define SLI_MGMT_RHBA 0x200 /* Register HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define SLI_MGMT_RPRT 0x210 /* Register Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define SLI_MGMT_DPRT 0x310 /* De-register Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * HBA Attribute Types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* Bit mask for all individual HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define LPFC_FDMI_HBA_ATTR_model 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define LPFC_FDMI_HBA_ATTR_description 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* Bit mask for FDMI-1 defined HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define LPFC_FDMI1_HBA_ATTR 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Bit mask for FDMI-2 defined HBA attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Skip vendor_info and bios_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define LPFC_FDMI2_HBA_ATTR 0x0002efff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * Port Attrubute Types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* Bit mask for all individual PORT attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define LPFC_FDMI_PORT_ATTR_class 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* Bit mask for FDMI-1 defined PORT attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define LPFC_FDMI1_PORT_ATTR 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Bit mask for FDMI-2 defined PORT attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Bit mask for Smart SAN defined PORT attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define LPFC_FDMI2_SMART_ATTR 0x007fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Defines for PORT port state attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define LPFC_FDMI_PORTSTATE_ONLINE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* Defines for PORT port type attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define LPFC_FDMI_PORTTYPE_NPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define LPFC_FDMI_PORTTYPE_NLPORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * Begin HBA configuration parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * The PCI configuration register BAR assignments are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * BAR0, offset 0x10 - SLIM base memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * BAR1, offset 0x14 - SLIM base memory high address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * BAR2, offset 0x18 - REGISTER base memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * BAR3, offset 0x1c - REGISTER base memory high address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * BAR4, offset 0x20 - BIU I/O registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * BAR5, offset 0x24 - REGISTER base io high address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Number of rings currently used and available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define MAX_SLI3_CONFIGURED_RINGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define MAX_SLI3_RINGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* IOCB / Mailbox is owned by FireFly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define OWN_CHIP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* IOCB / Mailbox is owned by Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define OWN_HOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* Number of 4-byte words in an IOCB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define IOCB_WORD_SZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* network headers for Dfctl field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define FC_NET_HDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Start FireFly Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define PCI_VENDOR_ID_EMULEX 0x10df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define PCI_DEVICE_ID_FIREFLY 0x1ae5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define PCI_DEVICE_ID_BALIUS 0xe131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define PCI_DEVICE_ID_LANCER_FC 0xe200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define PCI_DEVICE_ID_SAT_SMB 0xf011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define PCI_DEVICE_ID_SAT_MID 0xf015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define PCI_DEVICE_ID_RFLY 0xf095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define PCI_DEVICE_ID_PFLY 0xf098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define PCI_DEVICE_ID_LP101 0xf0a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define PCI_DEVICE_ID_TFLY 0xf0a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define PCI_DEVICE_ID_BSMB 0xf0d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define PCI_DEVICE_ID_BMID 0xf0d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define PCI_DEVICE_ID_ZSMB 0xf0e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define PCI_DEVICE_ID_ZMID 0xf0e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define PCI_DEVICE_ID_SAT 0xf100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define PCI_DEVICE_ID_SAT_SCSP 0xf111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define PCI_DEVICE_ID_SAT_DCSP 0xf112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define PCI_DEVICE_ID_FALCON 0xf180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define PCI_DEVICE_ID_SUPERFLY 0xf700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define PCI_DEVICE_ID_DRAGONFLY 0xf800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define PCI_DEVICE_ID_CENTAUR 0xf900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define PCI_DEVICE_ID_PEGASUS 0xf980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define PCI_DEVICE_ID_THOR 0xfa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define PCI_DEVICE_ID_VIPER 0xfb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define PCI_DEVICE_ID_LP10000S 0xfc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define PCI_DEVICE_ID_LP11000S 0xfc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define PCI_DEVICE_ID_LPE11000S 0xfc20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define PCI_DEVICE_ID_SAT_S 0xfc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define PCI_DEVICE_ID_HELIOS 0xfd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define PCI_DEVICE_ID_ZEPHYR 0xfe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define PCI_DEVICE_ID_HORNET 0xfe05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define PCI_DEVICE_ID_TIGERSHARK 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define PCI_DEVICE_ID_TOMCAT 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define PCI_DEVICE_ID_SKYHAWK 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define JEDEC_ID_ADDRESS 0x0080001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define FIREFLY_JEDEC_ID 0x1ACC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define SUPERFLY_JEDEC_ID 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define DRAGONFLY_JEDEC_ID 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define DRAGONFLY_V2_JEDEC_ID 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define CENTAUR_2G_JEDEC_ID 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define CENTAUR_1G_JEDEC_ID 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define PEGASUS_ORION_JEDEC_ID 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define PEGASUS_JEDEC_ID 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define THOR_JEDEC_ID 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define HELIOS_JEDEC_ID 0x0364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define ZEPHYR_JEDEC_ID 0x0577
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define VIPER_JEDEC_ID 0x4838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define SATURN_JEDEC_ID 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define HORNET_JDEC_ID 0x2057706D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define JEDEC_ID_MASK 0x0FFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define JEDEC_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) typedef struct { /* FireFly BIU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) uint32_t hostAtt; /* See definitions for Host Attention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) uint32_t chipAtt; /* See definitions for Chip Attention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) uint32_t hostStatus; /* See definitions for Host Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) uint32_t hostControl; /* See definitions for Host Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) uint32_t buiConfig; /* See definitions for BIU configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } FF_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* IO Register size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define FF_REG_AREA_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* Host Attention Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define HA_REG_OFFSET 0 /* Byte offset from register base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define HA_R0ATT 0x00000008 /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define HA_R1ATT 0x00000080 /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define HA_R2ATT 0x00000800 /* Bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define HA_R3ATT 0x00008000 /* Bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define HA_LATT 0x20000000 /* Bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define HA_MBATT 0x40000000 /* Bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define HA_ERATT 0x80000000 /* Bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define HA_RXATT 0x00000008 /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define HA_RXMASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define HA_R0_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define HA_R1_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define HA_R2_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define HA_R3_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define HA_LE_POS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define HA_MB_POS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define HA_ER_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* Chip Attention Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define CA_REG_OFFSET 4 /* Byte offset from register base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define CA_R0ATT 0x00000008 /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define CA_R1ATT 0x00000080 /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define CA_R2ATT 0x00000800 /* Bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define CA_R3ATT 0x00008000 /* Bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define CA_MBATT 0x40000000 /* Bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* Host Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define HS_REG_OFFSET 8 /* Byte offset from register base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define HS_MBRDY 0x00400000 /* Bit 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define HS_FFRDY 0x00800000 /* Bit 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define HS_FFER8 0x01000000 /* Bit 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define HS_FFER7 0x02000000 /* Bit 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define HS_FFER6 0x04000000 /* Bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define HS_FFER5 0x08000000 /* Bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define HS_FFER4 0x10000000 /* Bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define HS_FFER3 0x20000000 /* Bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define HS_FFER2 0x40000000 /* Bit 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define HS_FFER1 0x80000000 /* Bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* Host Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define HC_REG_OFFSET 12 /* Byte offset from register base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define HC_INITHBI 0x02000000 /* Bit 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define HC_INITMB 0x04000000 /* Bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define HC_INITFF 0x08000000 /* Bit 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define MSIX_DFLT_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define MSIX_RNG0_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define MSIX_RNG1_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define MSIX_RNG2_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define MSIX_RNG3_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define MSIX_LINK_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define MSIX_MBOX_ID 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define MSIX_SPARE0_ID 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define MSIX_SPARE1_ID 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* Mailbox Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define MBX_SHUTDOWN 0x00 /* terminate testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define MBX_LOAD_SM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define MBX_READ_NV 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define MBX_WRITE_NV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define MBX_RUN_BIU_DIAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define MBX_INIT_LINK 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define MBX_DOWN_LINK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define MBX_CONFIG_LINK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define MBX_CONFIG_RING 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define MBX_RESET_RING 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define MBX_READ_CONFIG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define MBX_READ_RCONFIG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define MBX_READ_SPARM 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define MBX_READ_STATUS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define MBX_READ_RPI 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define MBX_READ_XRI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define MBX_READ_REV 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define MBX_READ_LNK_STAT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define MBX_REG_LOGIN 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define MBX_UNREG_LOGIN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define MBX_CLEAR_LA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define MBX_DUMP_MEMORY 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define MBX_DUMP_CONTEXT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define MBX_RUN_DIAGS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define MBX_RESTART 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define MBX_UPDATE_CFG 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define MBX_DOWN_LOAD 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define MBX_DEL_LD_ENTRY 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define MBX_RUN_PROGRAM 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define MBX_SET_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define MBX_SET_VARIABLE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define MBX_UNREG_D_ID 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define MBX_KILL_BOARD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define MBX_CONFIG_FARP 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define MBX_BEACON 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define MBX_CONFIG_MSI 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define MBX_HEARTBEAT 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define MBX_WRITE_VPARMS 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define MBX_ASYNCEVT_ENABLE 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define MBX_READ_EVENT_LOG_STATUS 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define MBX_READ_EVENT_LOG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define MBX_WRITE_EVENT_LOG 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define MBX_PORT_CAPABILITIES 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define MBX_PORT_IOV_CONTROL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define MBX_CONFIG_HBQ 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define MBX_LOAD_AREA 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define MBX_RUN_BIU_DIAG64 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define MBX_CONFIG_PORT 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define MBX_READ_SPARM64 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define MBX_READ_RPI64 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define MBX_REG_LOGIN64 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define MBX_READ_TOPOLOGY 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define MBX_REG_VPI 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define MBX_UNREG_VPI 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define MBX_WRITE_WWN 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define MBX_SET_DEBUG 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define MBX_LOAD_EXP_ROM 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define MBX_SLI4_CONFIG 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define MBX_SLI4_REQ_FTRS 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define MBX_MAX_CMDS 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define MBX_RESUME_RPI 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define MBX_SLI2_CMD_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define MBX_REG_VFI 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define MBX_REG_FCFI 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define MBX_UNREG_VFI 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define MBX_UNREG_FCFI 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define MBX_INIT_VFI 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define MBX_INIT_VPI 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define MBX_ACCESS_VDATA 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define MBX_REG_FCFI_MRQ 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define MBX_AUTH_PORT 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define MBX_SECURITY_MGMT 0xF9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* IOCB Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define CMD_RCV_SEQUENCE_CX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define CMD_XMIT_SEQUENCE_CR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define CMD_XMIT_SEQUENCE_CX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define CMD_XMIT_BCAST_CN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define CMD_XMIT_BCAST_CX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define CMD_QUE_RING_BUF_CN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define CMD_QUE_XRI_BUF_CX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define CMD_IOCB_CONTINUE_CN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define CMD_RET_XRI_BUF_CX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define CMD_ELS_REQUEST_CR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define CMD_ELS_REQUEST_CX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define CMD_RCV_ELS_REQ_CX 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define CMD_ABORT_XRI_CN 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define CMD_ABORT_XRI_CX 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define CMD_CLOSE_XRI_CN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define CMD_CLOSE_XRI_CX 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define CMD_CREATE_XRI_CR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define CMD_CREATE_XRI_CX 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define CMD_GET_RPI_CN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define CMD_XMIT_ELS_RSP_CX 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define CMD_GET_RPI_CR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define CMD_XRI_ABORTED_CX 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define CMD_FCP_IWRITE_CR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define CMD_FCP_IWRITE_CX 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define CMD_FCP_IREAD_CR 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define CMD_FCP_IREAD_CX 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define CMD_FCP_ICMND_CR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define CMD_FCP_ICMND_CX 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define CMD_FCP_TSEND_CX 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define CMD_FCP_TRECEIVE_CX 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define CMD_FCP_TRSP_CX 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define CMD_FCP_AUTO_TRSP_CX 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define CMD_ADAPTER_MSG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define CMD_ADAPTER_DUMP 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* SLI_2 IOCB Command Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define CMD_ASYNC_STATUS 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define CMD_RCV_SEQUENCE64_CX 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define CMD_XMIT_SEQUENCE64_CR 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define CMD_XMIT_SEQUENCE64_CX 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define CMD_XMIT_BCAST64_CN 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define CMD_XMIT_BCAST64_CX 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define CMD_QUE_RING_BUF64_CN 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define CMD_QUE_XRI_BUF64_CX 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define CMD_IOCB_CONTINUE64_CN 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define CMD_RET_XRI_BUF64_CX 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define CMD_ELS_REQUEST64_CR 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define CMD_ELS_REQUEST64_CX 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define CMD_ABORT_MXRI64_CN 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define CMD_RCV_ELS_REQ64_CX 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define CMD_XMIT_ELS_RSP64_CX 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define CMD_XMIT_BLS_RSP64_CX 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define CMD_FCP_IWRITE64_CR 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define CMD_FCP_IWRITE64_CX 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define CMD_FCP_IREAD64_CR 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define CMD_FCP_IREAD64_CX 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define CMD_FCP_ICMND64_CR 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define CMD_FCP_ICMND64_CX 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define CMD_FCP_TSEND64_CX 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define CMD_FCP_TRECEIVE64_CX 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define CMD_FCP_TRSP64_CX 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define CMD_QUE_XRI64_CX 0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define CMD_IOCB_RCV_SEQ64_CX 0xB5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define CMD_IOCB_RCV_ELS64_CX 0xB7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define CMD_IOCB_RET_XRI64_CX 0xB9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define CMD_IOCB_RCV_CONT64_CX 0xBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define CMD_GEN_REQUEST64_CR 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define CMD_GEN_REQUEST64_CX 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* Unhandled SLI-3 Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define CMD_IOCB_RET_HBQE64_CN 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define CMD_IOCB_LOGENTRY_CN 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* Data Security SLI Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define DSSCMD_IWRITE64_CR 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define DSSCMD_IWRITE64_CX 0xF9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define DSSCMD_IREAD64_CR 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define DSSCMD_IREAD64_CX 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define CMD_MAX_IOCB_CMD 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define CMD_IOCB_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) iocb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define LPFC_MAX_ADPTMSG 32 /* max msg data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * Define Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define MBX_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define MBXERR_NUM_RINGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define MBXERR_NUM_IOCBS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define MBXERR_IOCBS_EXCEEDED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define MBXERR_BAD_RING_NUMBER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define MBXERR_MASK_ENTRIES_RANGE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define MBXERR_MASKS_EXCEEDED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define MBXERR_BAD_PROFILE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define MBXERR_BAD_DEF_CLASS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define MBXERR_BAD_MAX_RESPONDER 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define MBXERR_BAD_MAX_ORIGINATOR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define MBXERR_RPI_REGISTERED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define MBXERR_RPI_FULL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define MBXERR_NO_RESOURCES 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define MBXERR_BAD_RCV_LENGTH 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define MBXERR_DMA_ERROR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define MBXERR_ERROR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define MBXERR_LINK_DOWN 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define MBXERR_SEC_NO_PERMISSION 0xF02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define MBX_NOT_FINISHED 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * return code Fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define FAILURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * Begin Structure Definitions for Mailbox Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) uint8_t tval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) uint8_t tmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) uint8_t rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) uint8_t rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) uint8_t rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) uint8_t rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) uint8_t tmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) uint8_t tval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) } RR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct ulp_bde {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) uint32_t bdeAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) uint32_t bdeReserved:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) uint32_t bdeAddrHigh:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) uint32_t bdeSize:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) uint32_t bdeSize:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) uint32_t bdeAddrHigh:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) uint32_t bdeReserved:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) typedef struct ULP_BDL { /* SLI-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) uint32_t bdeFlags:8; /* BDL Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) uint32_t bdeFlags:8; /* BDL Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) uint32_t addrLow; /* Address 0:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) uint32_t addrHigh; /* Address 32:63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) } ULP_BDL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * BlockGuard Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) enum lpfc_protgrp_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* PDE Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define LPFC_PDE5_DESCRIPTOR 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define LPFC_PDE6_DESCRIPTOR 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define LPFC_PDE7_DESCRIPTOR 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* BlockGuard Opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define BG_OP_IN_NODIF_OUT_CRC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define BG_OP_IN_CRC_OUT_NODIF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define BG_OP_IN_NODIF_OUT_CSUM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define BG_OP_IN_CSUM_OUT_NODIF 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define BG_OP_IN_CRC_OUT_CRC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define BG_OP_IN_CSUM_OUT_CSUM 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define BG_OP_IN_CRC_OUT_CSUM 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define BG_OP_IN_CSUM_OUT_CRC 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define BG_OP_RAW_MODE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct lpfc_pde5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define pde5_type_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define pde5_type_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define pde5_type_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define pde5_rsvd0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define pde5_rsvd0_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define pde5_rsvd0_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) uint32_t reftag; /* Reference Tag Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) uint32_t reftagtr; /* Reference Tag Translation Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct lpfc_pde6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define pde6_type_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define pde6_type_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define pde6_type_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define pde6_rsvd0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define pde6_rsvd0_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define pde6_rsvd0_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) uint32_t word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define pde6_rsvd1_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define pde6_rsvd1_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define pde6_rsvd1_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define pde6_na_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define pde6_na_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define pde6_na_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define pde6_rsvd2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define pde6_rsvd2_MASK 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define pde6_rsvd2_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define pde6_apptagtr_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define pde6_apptagtr_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define pde6_apptagtr_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) uint32_t word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define pde6_optx_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define pde6_optx_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define pde6_optx_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define pde6_oprx_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define pde6_oprx_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define pde6_oprx_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define pde6_nr_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define pde6_nr_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define pde6_nr_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define pde6_ce_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define pde6_ce_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define pde6_ce_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define pde6_re_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define pde6_re_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define pde6_re_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define pde6_ae_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define pde6_ae_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define pde6_ae_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define pde6_ai_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define pde6_ai_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define pde6_ai_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define pde6_bs_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define pde6_bs_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define pde6_bs_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define pde6_apptagval_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define pde6_apptagval_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define pde6_apptagval_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) struct lpfc_pde7 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define pde7_type_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define pde7_type_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define pde7_type_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define pde7_rsvd0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define pde7_rsvd0_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define pde7_rsvd0_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) uint32_t addrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) uint32_t addrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /* Structure for MB Command LOAD_SM and DOWN_LOAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) uint32_t rsvd2:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) uint32_t acknowledgment:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) uint32_t version:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) uint32_t erase_or_prog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) uint32_t update_flash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) uint32_t update_ram:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) uint32_t method:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) uint32_t load_cmplt:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) uint32_t load_cmplt:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) uint32_t method:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) uint32_t update_ram:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) uint32_t update_flash:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) uint32_t erase_or_prog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) uint32_t version:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) uint32_t acknowledgment:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) uint32_t rsvd2:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) uint32_t dl_to_adr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) uint32_t dl_to_adr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) uint32_t dl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) uint32_t dl_from_mbx_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct ulp_bde dl_from_bde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) struct ulp_bde64 dl_from_bde64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) } LOAD_SM_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /* Structure for MB Command READ_NVPARM (02) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) uint32_t rsvd1[3]; /* Read as all one's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) uint32_t rsvd2; /* Read as all zero's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) uint32_t portname[2]; /* N_PORT name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) uint32_t nodename[2]; /* NODE name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) uint32_t pref_DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) uint32_t hardAL_PA:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) uint32_t hardAL_PA:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) uint32_t pref_DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) uint32_t rsvd3[21]; /* Read as all one's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) } READ_NV_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Structure for MB Command WRITE_NVPARMS (03) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) uint32_t rsvd1[3]; /* Must be all one's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) uint32_t rsvd2; /* Must be all zero's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) uint32_t portname[2]; /* N_PORT name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) uint32_t nodename[2]; /* NODE name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) uint32_t pref_DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) uint32_t hardAL_PA:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) uint32_t hardAL_PA:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) uint32_t pref_DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) uint32_t rsvd3[21]; /* Must be all one's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) } WRITE_NV_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* Structure for MB Command RUN_BIU_DIAG (04) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) struct ulp_bde xmit_bde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct ulp_bde rcv_bde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) } s1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct ulp_bde64 xmit_bde64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct ulp_bde64 rcv_bde64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) } s2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) } BIU_DIAG_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) /* Structure for MB command READ_EVENT_LOG (0x38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) struct READ_EVENT_LOG_VAR {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) uint32_t word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define lpfc_event_log_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #define lpfc_event_log_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define lpfc_event_log_WORD word1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define USE_MAILBOX_RESPONSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct ulp_bde64 rcv_bde64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* Structure for MB Command INIT_LINK (05) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) uint32_t rsvd1:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) uint32_t rsvd1:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) uint8_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) uint16_t link_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) uint16_t link_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) uint8_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) uint32_t link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define LINK_SPEED_AUTO 0x0 /* Auto selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) } INIT_LINK_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /* Structure for MB Command DOWN_LINK (06) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) } DOWN_LINK_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* Structure for MB Command CONFIG_LINK (07) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) uint32_t cr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) uint32_t ci:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) uint32_t cr_delay:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) uint32_t cr_count:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) uint32_t rsvd1:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) uint32_t MaxBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) uint32_t MaxBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) uint32_t rsvd1:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) uint32_t cr_count:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) uint32_t cr_delay:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) uint32_t ci:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) uint32_t cr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) uint32_t myId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) uint32_t edtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) uint32_t arbtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) uint32_t ratov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) uint32_t rttov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) uint32_t altov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) uint32_t crtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) uint32_t rsvd4:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) uint32_t cscn:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) uint32_t bbscn:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) uint32_t rsvd3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) uint32_t rsvd3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) uint32_t bbscn:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) uint32_t cscn:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) uint32_t rsvd4:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) uint32_t rrq_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) uint32_t rrq_immed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) uint32_t rsvd5:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) uint32_t ack0_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) uint32_t ack0_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) uint32_t rsvd5:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) uint32_t rrq_immed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) uint32_t rrq_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) } CONFIG_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /* Structure for MB Command PART_SLIM (08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) * will be removed since SLI1 is no longer supported!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) uint16_t offCiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) uint16_t numCiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) uint16_t offRiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) uint16_t numRiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) uint16_t numCiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) uint16_t offCiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) uint16_t numRiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) uint16_t offRiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) } RING_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) uint32_t unused1:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) uint32_t numRing:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) uint32_t numRing:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) uint32_t unused1:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) RING_DEF ringdef[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) uint32_t hbainit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) } PART_SLIM_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* Structure for MB Command CONFIG_RING (09) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) uint32_t unused2:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) uint32_t recvSeq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) uint32_t recvNotify:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) uint32_t numMask:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) uint32_t profile:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) uint32_t unused1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) uint32_t ring:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) uint32_t ring:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) uint32_t unused1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) uint32_t profile:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) uint32_t numMask:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) uint32_t recvNotify:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) uint32_t recvSeq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) uint32_t unused2:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) uint16_t maxRespXchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) uint16_t maxOrigXchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) uint16_t maxOrigXchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) uint16_t maxRespXchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) RR_REG rrRegs[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) } CONFIG_RING_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* Structure for MB Command RESET_RING (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) uint32_t ring_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) } RESET_RING_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /* Structure for MB Command READ_CONFIG (11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) uint32_t cr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) uint32_t ci:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) uint32_t cr_delay:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) uint32_t cr_count:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) uint32_t InitBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) uint32_t MaxBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) uint32_t MaxBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) uint32_t InitBBC:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) uint32_t cr_count:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) uint32_t cr_delay:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) uint32_t ci:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) uint32_t cr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) uint32_t topology:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) uint32_t myDid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) uint32_t myDid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) uint32_t topology:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* Defines for topology (defined previously) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) uint32_t AR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) uint32_t IR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) uint32_t rsvd1:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) uint32_t ack0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) uint32_t ack0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) uint32_t rsvd1:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) uint32_t IR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) uint32_t AR:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) uint32_t edtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) uint32_t arbtov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) uint32_t ratov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) uint32_t rttov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) uint32_t altov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) uint32_t lmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #define LMT_RESERVED 0x000 /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #define LMT_1Gb 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define LMT_2Gb 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) #define LMT_4Gb 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #define LMT_8Gb 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) #define LMT_10Gb 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) #define LMT_16Gb 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define LMT_32Gb 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define LMT_64Gb 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define LMT_128Gb 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define LMT_256Gb 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) uint32_t max_xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) uint32_t max_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) uint32_t max_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) uint32_t avail_xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) uint32_t avail_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) uint32_t avail_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) uint32_t max_vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) uint32_t avail_vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) } READ_CONFIG_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) /* Structure for MB Command READ_RCONFIG (12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) uint32_t rsvd2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) uint32_t recvNotify:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) uint32_t numMask:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) uint32_t profile:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) uint32_t rsvd1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) uint32_t ring:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) uint32_t ring:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) uint32_t rsvd1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) uint32_t profile:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) uint32_t numMask:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) uint32_t recvNotify:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) uint32_t rsvd2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) uint16_t maxResp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) uint16_t maxOrig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) uint16_t maxOrig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) uint16_t maxResp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) RR_REG rrRegs[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) uint16_t cmdRingOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) uint16_t cmdEntryCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) uint16_t rspRingOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) uint16_t rspEntryCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) uint16_t nextCmdOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) uint16_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) uint16_t nextRspOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) uint16_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) uint16_t cmdEntryCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) uint16_t cmdRingOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) uint16_t rspEntryCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) uint16_t rspRingOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) uint16_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) uint16_t nextCmdOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) uint16_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) uint16_t nextRspOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) } READ_RCONF_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* Structure for MB Command READ_SPARM (13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* Structure for MB Command READ_SPARM64 (0x8D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) struct ulp_bde sp; /* This BDE points to struct serv_parm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) struct ulp_bde64 sp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) uint16_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) uint16_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) } READ_SPARM_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* Structure for MB Command READ_STATUS (14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) uint32_t rsvd1:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) uint32_t clrCounters:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) uint16_t activeXriCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) uint16_t activeRpiCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) uint32_t clrCounters:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) uint32_t rsvd1:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) uint16_t activeRpiCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) uint16_t activeXriCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) uint32_t xmitByteCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) uint32_t rcvByteCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) uint32_t xmitFrameCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) uint32_t rcvFrameCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) uint32_t xmitSeqCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) uint32_t rcvSeqCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) uint32_t totalOrigExchanges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) uint32_t totalRespExchanges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) uint32_t rcvPbsyCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) uint32_t rcvFbsyCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) } READ_STATUS_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) /* Structure for MB Command READ_RPI (15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) /* Structure for MB Command READ_RPI64 (0x8F) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) uint16_t nextRpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) uint16_t reqRpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) uint32_t DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) uint16_t reqRpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) uint16_t nextRpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) uint32_t DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) struct ulp_bde sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) struct ulp_bde64 sp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) } READ_RPI_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /* Structure for MB Command READ_XRI (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) uint16_t nextXri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) uint16_t reqXri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) uint32_t DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) uint32_t rsvd3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) uint32_t SID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) uint8_t seqId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) uint8_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) uint16_t seqCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) uint16_t oxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) uint16_t rxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) uint32_t rsvd6:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) uint32_t si:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) uint32_t exchOrig:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) uint16_t reqXri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) uint16_t nextXri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) uint32_t DID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) uint32_t SID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) uint32_t rsvd3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) uint16_t seqCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) uint8_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) uint8_t seqId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) uint16_t rxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) uint16_t oxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) uint32_t exchOrig:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) uint32_t si:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) uint32_t rsvd6:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) } READ_XRI_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) /* Structure for MB Command READ_REV (17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) uint32_t rr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) uint32_t rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) uint32_t v3req:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) uint32_t v3rsp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) uint32_t rsvd1:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) uint32_t rv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) uint32_t rv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) uint32_t rsvd1:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) uint32_t v3rsp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) uint32_t v3req:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) uint32_t rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) uint32_t rr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) uint32_t biuRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) uint32_t smRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) uint32_t smFwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) uint8_t ProgType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) uint8_t ProgId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) uint16_t ProgVer:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) uint16_t ProgRev:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) uint16_t ProgFixLvl:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) uint16_t ProgDistType:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) uint16_t DistCnt:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) uint16_t DistCnt:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) uint16_t ProgDistType:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) uint16_t ProgFixLvl:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) uint16_t ProgRev:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) uint16_t ProgVer:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) uint8_t ProgId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) uint8_t ProgType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) uint32_t endecRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) uint8_t feaLevelHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) uint8_t feaLevelLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) uint8_t fcphHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) uint8_t fcphLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) uint8_t fcphLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) uint8_t fcphHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) uint8_t feaLevelLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) uint8_t feaLevelHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) uint32_t postKernRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) uint32_t opFwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) uint8_t opFwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) uint32_t sli1FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) uint8_t sli1FwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) uint32_t sli2FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) uint8_t sli2FwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) uint32_t sli3Feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) uint32_t RandomData[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) } READ_REV_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /* Structure for MB Command READ_LINK_STAT (18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) uint32_t word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) #define lpfc_read_link_stat_rec_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #define lpfc_read_link_stat_rec_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #define lpfc_read_link_stat_rec_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) #define lpfc_read_link_stat_gec_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) #define lpfc_read_link_stat_gec_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) #define lpfc_read_link_stat_gec_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #define lpfc_read_link_stat_w02oftow23of_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define lpfc_read_link_stat_rsvd_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #define lpfc_read_link_stat_rsvd_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #define lpfc_read_link_stat_rsvd_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) #define lpfc_read_link_stat_gec2_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #define lpfc_read_link_stat_gec2_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define lpfc_read_link_stat_gec2_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) #define lpfc_read_link_stat_clrc_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #define lpfc_read_link_stat_clrc_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define lpfc_read_link_stat_clrc_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #define lpfc_read_link_stat_clof_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) #define lpfc_read_link_stat_clof_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) #define lpfc_read_link_stat_clof_WORD word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) uint32_t linkFailureCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) uint32_t lossSyncCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) uint32_t lossSignalCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) uint32_t primSeqErrCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) uint32_t invalidXmitWord;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) uint32_t crcCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) uint32_t primSeqTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) uint32_t elasticOverrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) uint32_t arbTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) uint32_t advRecBufCredit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) uint32_t curRecBufCredit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) uint32_t advTransBufCredit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) uint32_t curTransBufCredit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) uint32_t recEofCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) uint32_t recEofdtiCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) uint32_t recEofniCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) uint32_t recSofcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) uint32_t recDrpXriCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) uint32_t fecCorrBlkCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) uint32_t fecUncorrBlkCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) } READ_LNK_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* Structure for MB Command REG_LOGIN (19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) /* Structure for MB Command REG_LOGIN64 (0x93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) uint32_t did:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) uint32_t did:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) uint32_t rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) struct ulp_bde sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) struct ulp_bde64 sp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) } REG_LOGIN_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) /* Word 30 contents for REG_LOGIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) uint16_t rsvd1:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) uint16_t wd30_class:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) uint16_t xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) uint16_t xri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) uint16_t wd30_class:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) uint16_t rsvd1:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) } f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) uint32_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) } REG_WD30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) /* Structure for MB Command UNREG_LOGIN (20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) uint16_t rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) uint16_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) } UNREG_LOGIN_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) /* Structure for MB Command REG_VPI (0x96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) uint32_t rsvd2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) uint32_t upd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) uint32_t sid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) uint32_t wwn[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) uint16_t vfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) uint32_t sid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) uint32_t upd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) uint32_t rsvd2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) uint32_t wwn[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) uint16_t vfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) } REG_VPI_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) /* Structure for MB Command UNREG_VPI (0x97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) uint16_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) uint16_t sli4_vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) uint16_t sli4_vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) uint16_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) } UNREG_VPI_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /* Structure for MB Command UNREG_D_ID (0x23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) uint32_t did;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) uint32_t rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) uint16_t rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) } UNREG_D_ID_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /* Structure for MB Command READ_TOPOLOGY (0x95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) struct lpfc_mbx_read_top {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) uint32_t eventTag; /* Event tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) uint32_t word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) #define lpfc_mbx_read_top_fa_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #define lpfc_mbx_read_top_fa_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) #define lpfc_mbx_read_top_fa_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define lpfc_mbx_read_top_mm_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #define lpfc_mbx_read_top_mm_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) #define lpfc_mbx_read_top_mm_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) #define lpfc_mbx_read_top_pb_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) #define lpfc_mbx_read_top_pb_MASK 0X00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) #define lpfc_mbx_read_top_pb_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) #define lpfc_mbx_read_top_il_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) #define lpfc_mbx_read_top_il_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) #define lpfc_mbx_read_top_il_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) #define lpfc_mbx_read_top_att_type_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) #define lpfc_mbx_read_top_att_type_WORD word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) uint32_t word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define lpfc_mbx_read_top_alpa_granted_WORD word3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #define lpfc_mbx_read_top_lip_alps_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) #define lpfc_mbx_read_top_lip_alps_WORD word3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) #define lpfc_mbx_read_top_lip_type_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) #define lpfc_mbx_read_top_lip_type_WORD word3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) #define lpfc_mbx_read_top_topology_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) #define lpfc_mbx_read_top_topology_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) #define lpfc_mbx_read_top_topology_WORD word3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) /* store the LILP AL_PA position map into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) struct ulp_bde64 lilpBde64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) #define LPFC_ALPA_MAP_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) uint32_t word7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) #define lpfc_mbx_read_top_ld_lu_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) #define lpfc_mbx_read_top_ld_lu_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) #define lpfc_mbx_read_top_ld_tf_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) #define lpfc_mbx_read_top_ld_tf_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) #define lpfc_mbx_read_top_ld_link_spd_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) #define lpfc_mbx_read_top_ld_nl_port_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) #define lpfc_mbx_read_top_ld_tx_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) #define lpfc_mbx_read_top_ld_tx_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) #define lpfc_mbx_read_top_ld_rx_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) #define lpfc_mbx_read_top_ld_rx_WORD word7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) uint32_t word8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) #define lpfc_mbx_read_top_lu_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) #define lpfc_mbx_read_top_lu_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) #define lpfc_mbx_read_top_lu_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) #define lpfc_mbx_read_top_tf_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) #define lpfc_mbx_read_top_tf_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) #define lpfc_mbx_read_top_tf_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) #define lpfc_mbx_read_top_link_spd_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) #define lpfc_mbx_read_top_link_spd_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) #define lpfc_mbx_read_top_nl_port_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) #define lpfc_mbx_read_top_nl_port_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define lpfc_mbx_read_top_tx_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) #define lpfc_mbx_read_top_tx_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) #define lpfc_mbx_read_top_tx_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define lpfc_mbx_read_top_rx_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) #define lpfc_mbx_read_top_rx_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) #define lpfc_mbx_read_top_rx_WORD word8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define LPFC_LINK_SPEED_UNKNOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) #define LPFC_LINK_SPEED_1GHZ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) #define LPFC_LINK_SPEED_2GHZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) #define LPFC_LINK_SPEED_4GHZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define LPFC_LINK_SPEED_8GHZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) #define LPFC_LINK_SPEED_10GHZ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define LPFC_LINK_SPEED_16GHZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) #define LPFC_LINK_SPEED_32GHZ 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #define LPFC_LINK_SPEED_64GHZ 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define LPFC_LINK_SPEED_128GHZ 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define LPFC_LINK_SPEED_256GHZ 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) /* Structure for MB Command CLEAR_LA (22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) uint32_t eventTag; /* Event tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) } CLEAR_LA_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* Structure for MB Command DUMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) uint32_t rsvd:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) uint32_t ra:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) uint32_t co:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) uint32_t type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) uint32_t entry_index:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) uint32_t region_id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) uint32_t type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) uint32_t co:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) uint32_t ra:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) uint32_t rsvd:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) uint32_t region_id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) uint32_t entry_index:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) uint32_t sli4_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) uint32_t word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) uint32_t resp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) } DUMP_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) #define DMP_MEM_REG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) #define DMP_NV_PARAMS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) #define DMP_LMSD 0x3 /* Link Module Serial Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) #define DMP_WELL_KNOWN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) #define DMP_REGION_VPD 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) #define DMP_REGION_VPORT 0x16 /* VPort info region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) #define DMP_VPORT_REGION_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) #define DMP_MBOX_OFFSET_WORD 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) #define DMP_REGION_23 0x17 /* fcoe param and port state region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) #define DMP_RGN23_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) #define WAKE_UP_PARMS_REGION_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) #define WAKE_UP_PARMS_WORD_SIZE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) struct vport_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) uint8_t wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) #define VPORT_INFO_SIG 0x32324752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) #define VPORT_INFO_REV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) #define VPORT_INFO_REV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define MAX_STATIC_VPORT_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) struct static_vport_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) uint32_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) uint32_t resvd[66];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* Option rom version structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) struct prog_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) uint8_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) uint32_t ver:4; /* Major Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) uint32_t rev:4; /* Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) uint32_t lev:2; /* Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) uint32_t dist:2; /* Dist Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) uint32_t num:4; /* number after dist type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) uint32_t num:4; /* number after dist type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) uint32_t dist:2; /* Dist Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) uint32_t lev:2; /* Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) uint32_t rev:4; /* Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) uint32_t ver:4; /* Major Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) uint8_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /* Structure for MB Command UPDATE_CFG (0x1B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) struct update_cfg_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) uint32_t rsvd2:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) uint32_t rsvd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) uint32_t ra:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) uint32_t co:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) uint32_t req:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) uint32_t entry_length:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) uint32_t region_id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) uint32_t req:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) uint32_t cv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) uint32_t co:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) uint32_t ra:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) uint32_t rsvd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) uint32_t rsvd2:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) uint32_t region_id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) uint32_t entry_length:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) uint32_t resp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) uint32_t byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) uint32_t data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) struct hbq_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) uint8_t tmatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) uint8_t tmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) uint8_t rctlmatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) uint8_t rctlmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) uint8_t rctlmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) uint8_t rctlmatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) uint8_t tmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) uint8_t tmatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) /* Structure for MB Command CONFIG_HBQ (7c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) struct config_hbq_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) uint32_t rsvd1 :7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) uint32_t recvNotify :1; /* Receive Notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) uint32_t numMask :8; /* # Mask Entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) uint32_t profile :8; /* Selection Profile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) uint32_t rsvd2 :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) uint32_t rsvd2 :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) uint32_t profile :8; /* Selection Profile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) uint32_t numMask :8; /* # Mask Entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) uint32_t recvNotify :1; /* Receive Notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) uint32_t rsvd1 :7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) uint32_t hbqId :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) uint32_t rsvd3 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) uint32_t ringMask :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) uint32_t ringMask :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) uint32_t rsvd3 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) uint32_t hbqId :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) uint32_t entry_count :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) uint32_t rsvd4 :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) uint32_t headerLen :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) uint32_t headerLen :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) uint32_t rsvd4 :8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) uint32_t entry_count :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) uint32_t hbqaddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) uint32_t hbqaddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) uint32_t rsvd5 :31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) uint32_t logEntry :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) uint32_t logEntry :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) uint32_t rsvd5 :31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) uint32_t rsvd6; /* w7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) uint32_t rsvd7; /* w8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) uint32_t rsvd8; /* w9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) struct hbq_mask hbqMasks[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) uint32_t allprofiles[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) uint32_t rsvd1 :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) uint32_t rsvd1 :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) uint32_t rsvd[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) } profile2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) uint32_t cmdcodeoff :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) uint32_t rsvd1 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) uint32_t rsvd1 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) uint32_t cmdcodeoff :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) uint32_t cmdmatch[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) uint32_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) } profile3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) uint32_t maxlen :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) uint32_t seqlenoff :16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) uint32_t cmdcodeoff :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) uint32_t rsvd1 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) uint32_t seqlenbcnt :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) uint32_t rsvd1 :12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) uint32_t cmdcodeoff :28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) uint32_t cmdmatch[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) uint32_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) } profile5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) } profiles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* Structure for MB Command CONFIG_PORT (0x88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) uint32_t cBE : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) uint32_t cET : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) uint32_t cHpcb : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) uint32_t cMA : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) uint32_t sli_mode : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) uint32_t pcbLen : 24; /* bit 23:0 of memory based port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) * config block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) uint32_t pcbLen : 24; /* bit 23:0 of memory based port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) * config block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) uint32_t sli_mode : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) uint32_t cMA : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) uint32_t cHpcb : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) uint32_t cET : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) uint32_t cBE : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) uint32_t pcbLow; /* bit 31:0 of memory based port config block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) uint32_t hbainit[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) uint32_t rsvd1 : 20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) uint32_t casabt : 1; /* Configure async abts status notice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) uint32_t rsvd2 : 2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) uint32_t cbg : 1; /* Configure BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) uint32_t cmv : 1; /* Configure Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) uint32_t ccrp : 1; /* Config Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) uint32_t csah : 1; /* Configure Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) uint32_t chbs : 1; /* Cofigure Host Backing store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) uint32_t cinb : 1; /* Enable Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) uint32_t cmx : 1; /* Configure Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) uint32_t cmr : 1; /* Configure Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) uint32_t cmr : 1; /* Configure Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) uint32_t cmx : 1; /* Configure Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) uint32_t cinb : 1; /* Enable Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) uint32_t chbs : 1; /* Cofigure Host Backing store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) uint32_t csah : 1; /* Configure Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) uint32_t ccrp : 1; /* Config Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) uint32_t cmv : 1; /* Configure Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) uint32_t cbg : 1; /* Configure BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) uint32_t rsvd2 : 2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) uint32_t casabt : 1; /* Configure async abts status notice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) uint32_t rsvd1 : 20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) uint32_t rsvd3 : 20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) uint32_t gasabt : 1; /* Grant async abts status notice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) uint32_t rsvd4 : 2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) uint32_t gbg : 1; /* Grant BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) uint32_t gmv : 1; /* Grant Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) uint32_t gcrp : 1; /* Grant Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) uint32_t ghbs : 1; /* Grant Host Backing Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) uint32_t ginb : 1; /* Grant Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) uint32_t gerbm : 1; /* Grant ERBM Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) uint32_t gmx : 1; /* Grant Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) uint32_t gmr : 1; /* Grant Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) uint32_t gmr : 1; /* Grant Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) uint32_t gmx : 1; /* Grant Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) uint32_t gerbm : 1; /* Grant ERBM Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) uint32_t ginb : 1; /* Grant Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) uint32_t ghbs : 1; /* Grant Host Backing Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) uint32_t gcrp : 1; /* Grant Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) uint32_t gmv : 1; /* Grant Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) uint32_t gbg : 1; /* Grant BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) uint32_t rsvd4 : 2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) uint32_t gasabt : 1; /* Grant async abts status notice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) uint32_t rsvd3 : 20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) uint32_t max_rpi : 16; /* Max RPIs Port should configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) uint32_t max_xri : 16; /* Max XRIs Port should configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) uint32_t max_xri : 16; /* Max XRIs Port should configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) uint32_t max_rpi : 16; /* Max RPIs Port should configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) uint32_t rsvd6; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) uint32_t rsvd7 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) uint32_t max_vpi : 16; /* Max number of virt N-Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) uint32_t max_vpi : 16; /* Max number of virt N-Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) uint32_t rsvd7 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) } CONFIG_PORT_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) /* Structure for MB Command CONFIG_MSI (0x30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) struct config_msi_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) uint32_t dfltMsgNum:8; /* Default message number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) uint32_t rsvd1:11; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) uint32_t NID:5; /* Number of secondary attention IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) uint32_t rsvd2:5; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) uint32_t dfltPresent:1; /* Default message number present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) uint32_t addFlag:1; /* Add association flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) uint32_t reportFlag:1; /* Report association flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) uint32_t reportFlag:1; /* Report association flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) uint32_t addFlag:1; /* Add association flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) uint32_t dfltPresent:1; /* Default message number present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) uint32_t rsvd2:5; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) uint32_t NID:5; /* Number of secondary attention IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) uint32_t rsvd1:11; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) uint32_t dfltMsgNum:8; /* Default message number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) uint32_t attentionConditions[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) uint8_t attentionId[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) uint8_t messageNumberByHA[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) uint8_t messageNumberByID[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) uint32_t autoClearHA[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) uint32_t rsvd3:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) uint32_t autoClearID:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) uint32_t autoClearID:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) uint32_t rsvd3:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) uint32_t rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) /* SLI-2 Port Control Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) /* SLIM POINTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) #define SLIMOFF 0x30 /* WORD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) typedef struct _SLI2_RDSC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) uint32_t cmdEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) uint32_t cmdAddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) uint32_t cmdAddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) uint32_t rspEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) uint32_t rspAddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) uint32_t rspAddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) } SLI2_RDSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) typedef struct _PCB {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) #define TYPE_NATIVE_SLI2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) uint32_t feature:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) #define FEATURE_INITIAL_SLI2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) uint32_t rsvd:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) uint32_t maxRing:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) uint32_t maxRing:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) uint32_t rsvd:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) uint32_t feature:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) #define FEATURE_INITIAL_SLI2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) #define TYPE_NATIVE_SLI2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) uint32_t mailBoxSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) uint32_t mbAddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) uint32_t mbAddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) uint32_t hgpAddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) uint32_t hgpAddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) uint32_t pgpAddrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) uint32_t pgpAddrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) SLI2_RDSC rdsc[MAX_SLI3_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) } PCB_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) /* NEW_FEATURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) uint32_t rsvd0:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) uint32_t discardFarp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) uint32_t IPEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) uint32_t nodeName:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) uint32_t portName:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) uint32_t filterEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) uint32_t filterEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) uint32_t portName:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) uint32_t nodeName:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) uint32_t IPEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) uint32_t discardFarp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) uint32_t rsvd:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) uint8_t portname[8]; /* Used to be struct lpfc_name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) uint8_t nodename[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) uint32_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) uint32_t rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) uint32_t IPAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) } CONFIG_FARP_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) uint32_t rsvd:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) uint32_t rsvd:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) } ASYNCEVT_ENABLE_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) /* Union of all Mailbox Command types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) #define MAILBOX_CMD_WSIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) /* ext_wsize times 4 bytes should not be greater than max xmit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) #define MAILBOX_EXT_WSIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) #define MAILBOX_HBA_EXT_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) /* max mbox xmit size is a page size for sysfs IO operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) #define MAILBOX_SYSFS_MAX 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) * feature/max ring number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) * NEW_FEATURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) * (READ_EVENT_LOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) } MAILVARIANTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) * SLI-2 specific structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) struct lpfc_hgp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) __le32 cmdPutInx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) __le32 rspGetInx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) struct lpfc_pgp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) __le32 cmdGetInx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) __le32 rspPutInx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) struct sli2_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) uint32_t unused1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) struct lpfc_hgp host[MAX_SLI3_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) struct lpfc_pgp port[MAX_SLI3_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) struct sli3_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) struct lpfc_hgp host[MAX_SLI3_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) uint32_t reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) uint32_t hbq_put[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) struct sli3_pgp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) struct lpfc_pgp port[MAX_SLI3_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) uint32_t hbq_get[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) union sli_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) struct sli2_desc s2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) struct sli3_desc s3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) struct sli3_pgp s3_pgp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) uint16_t mbxStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) uint8_t mbxCommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) uint8_t mbxReserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) uint8_t mbxHc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) uint8_t mbxOwner:1; /* Low order bit first word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) uint8_t mbxOwner:1; /* Low order bit first word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) uint8_t mbxHc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) uint8_t mbxReserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) uint8_t mbxCommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) uint16_t mbxStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) MAILVARIANTS un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) union sli_var us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) } MAILBOX_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) * Begin Structure Definitions for IOCB Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) uint8_t statAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) uint8_t statRsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) uint8_t statBaExp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) uint8_t statLocalError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) uint8_t statLocalError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) uint8_t statBaExp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) uint8_t statRsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) uint8_t statAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) /* statRsn P/F_RJT reason codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) #define RJT_BAD_PARM 0x10 /* Param. field invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) #define RJT_XCHG_ERR 0x11 /* Exchange error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) #define RJT_PROT_ERR 0x12 /* Protocol error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) #define IOERR_SUCCESS 0x00 /* statLocalError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) #define IOERR_MISSING_CONTINUE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) #define IOERR_SEQUENCE_TIMEOUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) #define IOERR_INTERNAL_ERROR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) #define IOERR_INVALID_RPI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) #define IOERR_NO_XRI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) #define IOERR_ILLEGAL_COMMAND 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) #define IOERR_XCHG_DROPPED 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) #define IOERR_ILLEGAL_FIELD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) #define IOERR_BAD_CONTINUE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) #define IOERR_TOO_MANY_BUFFERS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) #define IOERR_RCV_BUFFER_WAITING 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) #define IOERR_NO_CONNECTION 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) #define IOERR_TX_DMA_FAILED 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #define IOERR_RX_DMA_FAILED 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) #define IOERR_ILLEGAL_FRAME 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) #define IOERR_EXTRA_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) #define IOERR_NO_RESOURCES 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) #define IOERR_RESERVED 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) #define IOERR_ILLEGAL_LENGTH 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) #define IOERR_UNSUPPORTED_FEATURE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) #define IOERR_ABORT_IN_PROGRESS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) #define IOERR_ABORT_REQUESTED 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) #define IOERR_LOOP_OPEN_FAILURE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) #define IOERR_RING_RESET 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) #define IOERR_LINK_DOWN 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) #define IOERR_CORRUPTED_DATA 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) #define IOERR_CORRUPTED_RPI 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) #define IOERR_OUT_OF_ORDER_DATA 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) #define IOERR_OUT_OF_ORDER_ACK 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) #define IOERR_DUP_FRAME 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) #define IOERR_BAD_HOST_ADDRESS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) #define IOERR_RCV_HDRBUF_WAITING 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) #define IOERR_MISSING_HDR_BUFFER 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) #define IOERR_ABORTMULT_REQUESTED 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) #define IOERR_BUFFER_SHORTAGE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) #define IOERR_DEFAULT 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) #define IOERR_CNT 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) #define IOERR_SLER_FAILURE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) #define IOERR_SLER_CMD_RCV_FAILURE 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) #define IOERR_SLER_REC_RJT_ERR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) #define IOERR_SLER_SRR_RJT_ERR 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) #define IOERR_SLER_RRQ_RJT_ERR 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) #define IOERR_SLER_ABTS_ERR 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) #define IOERR_DRVR_MASK 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) #define IOERR_SLI_BRESET 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) #define IOERR_SLI_ABORTED 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) #define IOERR_PARAM_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) } PARM_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) uint8_t Rctl; /* R_CTL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) uint8_t Type; /* TYPE field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) uint8_t Dfctl; /* DF_CTL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) uint8_t Dfctl; /* DF_CTL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) uint8_t Type; /* TYPE field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) uint8_t Rctl; /* R_CTL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) #define BC 0x02 /* Broadcast Received - Fctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) #define SI 0x04 /* Sequence Initiative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) #define LA 0x08 /* Ignore Link Attention state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) #define LS 0x80 /* Last Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) } hcsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) } WORD5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) /* IOCB Command template for a generic response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) uint32_t reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) PARM_ERR perr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) } GENERIC_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) struct ulp_bde xrsqbde[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) uint32_t xrsqRo; /* Starting Relative Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) WORD5 w5; /* Header control/status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) } XR_SEQ_FIELDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) /* IOCB Command template for ELS_REQUEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) struct ulp_bde elsReq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) struct ulp_bde elsRsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) uint32_t word4Rsvd:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) uint32_t fl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) uint32_t myID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) uint32_t myID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) uint32_t fl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) uint32_t word4Rsvd:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) } ELS_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) /* IOCB Command template for RCV_ELS_REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) struct ulp_bde elsReq[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) uint32_t parmRo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) } RCV_ELS_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) /* IOCB Command template for ABORT / CLOSE_XRI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) uint32_t rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) uint32_t abortType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) #define ABORT_TYPE_ABTX 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define ABORT_TYPE_ABTS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) uint32_t parm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) uint16_t abortContextTag; /* ulpContext from command to abort/close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) uint16_t abortContextTag; /* ulpContext from command to abort/close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) } AC_XRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) /* IOCB Command template for ABORT_MXRI64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) uint32_t rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) uint32_t abortType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) uint32_t parm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) uint32_t iotag32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) } A_MXRI64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /* IOCB Command template for GET_RPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) uint32_t rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) uint32_t parmRo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) } GET_RPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) /* IOCB Command template for all FCP Initiator commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) struct ulp_bde fcpi_rsp; /* Rcv buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) uint32_t fcpi_parm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) } FCPI_FIELDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) /* IOCB Command template for all FCP Target commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) uint32_t fcpt_Offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) uint32_t fcpt_Length; /* transfer ready for IWRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) } FCPT_FIELDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /* SLI-2 IOCB structure definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) ULP_BDL bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) uint32_t xrsqRo; /* Starting Relative Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) WORD5 w5; /* Header control/status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) } XMT_SEQ_FIELDS64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) #define xmit_els_remoteID xrsqRo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) struct ulp_bde64 rcvBde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) uint32_t xrsqRo; /* Starting Relative Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) WORD5 w5; /* Header control/status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) } RCV_SEQ_FIELDS64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) /* IOCB Command template for ELS_REQUEST64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) ULP_BDL bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) uint32_t word4Rsvd:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) uint32_t fl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) uint32_t myID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) uint32_t myID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) uint32_t fl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) uint32_t word4Rsvd:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) } ELS_REQUEST64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) /* IOCB Command template for GEN_REQUEST64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) ULP_BDL bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) uint32_t xrsqRo; /* Starting Relative Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) WORD5 w5; /* Header control/status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) } GEN_REQUEST64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /* IOCB Command template for RCV_ELS_REQ64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) struct ulp_bde64 elsReq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) uint32_t rcvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) uint32_t parmRo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) uint32_t remoteID:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) uint32_t word5Rsvd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) } RCV_ELS_REQ64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) /* IOCB Command template for RCV_SEQ64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) struct rcv_seq64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) struct ulp_bde64 elsReq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) uint32_t hbq_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) uint32_t parmRo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) uint32_t rctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) uint32_t dfctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) uint32_t ls:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) uint32_t fs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) uint32_t rsvd2:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) uint32_t si:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) uint32_t bc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) uint32_t rsvd3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) uint32_t rsvd3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) uint32_t bc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) uint32_t si:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) uint32_t rsvd2:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) uint32_t fs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) uint32_t ls:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) uint32_t dfctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) uint32_t type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) uint32_t rctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) /* IOCB Command template for all 64 bit FCP Initiator commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) ULP_BDL bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) uint32_t fcpi_parm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) } FCPI_FIELDS64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) /* IOCB Command template for all 64 bit FCP Target commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) ULP_BDL bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) uint32_t fcpt_Offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) uint32_t fcpt_Length; /* transfer ready for IWRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) } FCPT_FIELDS64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) /* IOCB Command template for Async Status iocb commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) uint32_t rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) uint32_t param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) uint16_t evt_code; /* High order bits word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) uint16_t sub_ctxt_tag; /* Low order bits word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) uint16_t sub_ctxt_tag; /* High order bits word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) uint16_t evt_code; /* Low order bits word 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) } ASYNCSTAT_FIELDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) #define ASYNC_TEMP_WARN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) #define ASYNC_TEMP_SAFE 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) #define ASYNC_STATUS_CN 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) struct rcv_sli3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) uint16_t ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) uint16_t seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) uint16_t word9Rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) uint16_t seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) uint16_t ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) uint16_t word9Rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) uint32_t word10Rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) uint32_t acc_len; /* accumulated length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) struct ulp_bde64 bde2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) /* Structure used for a single HBQ entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) struct lpfc_hbq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) struct ulp_bde64 bde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) uint32_t buffer_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) struct lpfc_hbq_entry buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) uint32_t rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) } QUE_XRI64_CX_FIELDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) struct que_xri64cx_ext_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) uint32_t iotag64_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) uint32_t iotag64_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) uint32_t ebde_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) struct lpfc_hbq_entry buff[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) struct sli3_bg_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) uint32_t filler[6]; /* word 8-13 in IOCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) #define BGS_BIDIR_BG_PROF_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) #define BGS_BIDIR_BG_PROF_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) #define BGS_BIDIR_ERR_COND_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) #define BGS_BG_PROFILE_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) #define BGS_BG_PROFILE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) #define BGS_INVALID_PROF_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) #define BGS_INVALID_PROF_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) #define BGS_REFTAG_ERR_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) #define BGS_REFTAG_ERR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) #define BGS_APPTAG_ERR_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) #define BGS_APPTAG_ERR_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) #define BGS_GUARD_ERR_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) #define BGS_GUARD_ERR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) uint32_t bgstat; /* word 15 - BlockGuard Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) BGS_BIDIR_BG_PROF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) BGS_BIDIR_ERR_COND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) lpfc_bgs_get_bg_prof(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) return (bgstat & BGS_BG_PROFILE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) BGS_BG_PROFILE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) lpfc_bgs_get_invalid_prof(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) return (bgstat & BGS_INVALID_PROF_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) BGS_INVALID_PROF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) BGS_UNINIT_DIF_BLOCK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) BGS_HI_WATER_MARK_PRESENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) lpfc_bgs_get_reftag_err(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) return (bgstat & BGS_REFTAG_ERR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) BGS_REFTAG_ERR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) lpfc_bgs_get_apptag_err(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) return (bgstat & BGS_APPTAG_ERR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) BGS_APPTAG_ERR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) lpfc_bgs_get_guard_err(uint32_t bgstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) return (bgstat & BGS_GUARD_ERR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) BGS_GUARD_ERR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) #define LPFC_EXT_DATA_BDE_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) struct fcp_irw_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) uint32_t io_tag64_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) uint32_t io_tag64_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) uint8_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) uint8_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) uint8_t ebde_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) uint8_t ebde_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) uint8_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) uint8_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) uint32_t reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) struct ulp_bde64 rbde; /* response bde */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) uint8_t icd[32]; /* immediate command data (32 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) typedef struct _IOCB { /* IOCB structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) GENERIC_RSP grsp; /* Generic response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) struct ulp_bde cont[3]; /* up to 3 continuation bdes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) AC_XRI acxri; /* ABORT / CLOSE_XRI template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) A_MXRI64 amxri; /* abort multiple xri command overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) GET_RPI getrpi; /* GET_RPI template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) FCPI_FIELDS fcpi; /* FCP Initiator template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) FCPT_FIELDS fcpt; /* FCP target template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) /* SLI-2 structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) * bde_64s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) uint16_t ulpContext; /* High order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) uint16_t ulpIoTag; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) uint16_t ulpIoTag; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) uint16_t ulpContext; /* High order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) } t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) uint16_t ulpContext; /* High order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) uint16_t ulpIoTag1:2; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) uint16_t ulpIoTag0:14; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) uint16_t ulpIoTag0:14; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) uint16_t ulpIoTag1:2; /* Low order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) uint16_t ulpContext; /* High order bits word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) } t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) } un1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) #define ulpContext un1.t1.ulpContext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) #define ulpIoTag un1.t1.ulpIoTag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) #define ulpIoTag0 un1.t2.ulpIoTag0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) uint32_t ulpTimeout:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) uint32_t ulpXS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) uint32_t ulpFCP2Rcvy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) uint32_t ulpPU:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) uint32_t ulpIr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) uint32_t ulpClass:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) uint32_t ulpCommand:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) uint32_t ulpStatus:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) uint32_t ulpBdeCount:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) uint32_t ulpLe:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) uint32_t ulpOwner:1; /* Low order bit word 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) #else /* __LITTLE_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) uint32_t ulpOwner:1; /* Low order bit word 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) uint32_t ulpLe:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) uint32_t ulpBdeCount:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) uint32_t ulpStatus:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) uint32_t ulpCommand:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) uint32_t ulpClass:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) uint32_t ulpIr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) uint32_t ulpPU:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) uint32_t ulpFCP2Rcvy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) uint32_t ulpXS:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) uint32_t ulpTimeout:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) struct rcv_sli3 rcvsli3; /* words 8 - 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) /* words 8-31 used for que_xri_cx iocb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) struct que_xri64cx_ext_fields que_xri64cx_ext_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) struct fcp_irw_ext fcp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) /* words 8-15 for BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) struct sli3_bg_fields sli3_bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) } unsli3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) #define ulpCt_h ulpXS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) #define ulpCt_l ulpFCP2Rcvy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) #define PARM_UNUSED 0 /* PU field (Word 4) not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) #define PARM_NPIV_DID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) #define CLASS1 0 /* Class 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) #define CLASS2 1 /* Class 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) #define CLASS3 2 /* Class 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) #define IOSTAT_FCP_RSP_ERROR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) #define IOSTAT_REMOTE_STOP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) #define IOSTAT_LOCAL_REJECT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) #define IOSTAT_NPORT_RJT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) #define IOSTAT_FABRIC_RJT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) #define IOSTAT_NPORT_BSY 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) #define IOSTAT_FABRIC_BSY 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) #define IOSTAT_INTERMED_RSP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) #define IOSTAT_LS_RJT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) #define IOSTAT_BA_RJT 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) #define IOSTAT_RSVD1 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) #define IOSTAT_RSVD2 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) #define IOSTAT_RSVD3 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) #define IOSTAT_RSVD4 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) #define IOSTAT_NEED_BUFFER 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) #define IOSTAT_CNT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) } IOCB_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) #define SLI1_SLIM_SIZE (4 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) /* Up to 498 IOCBs will fit into 16k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) #define SLI2_SLIM_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) /* Maximum IOCBs that will fit in SLI2 slim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) #define MAX_SLI2_IOCB 498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) /* HBQ entries are 4 words each = 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) lpfc_sli_hbq_count())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) struct lpfc_sli2_slim {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) MAILBOX_t mbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) PCB_t pcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) * This function checks PCI device to allow special handling for LC HBAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) * device : struct pci_dev 's device field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) * return 1 => TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * 0 => FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) lpfc_is_LC_HBA(unsigned short device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) if ((device == PCI_DEVICE_ID_TFLY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) (device == PCI_DEVICE_ID_PFLY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) (device == PCI_DEVICE_ID_LP101) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) (device == PCI_DEVICE_ID_BMID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) (device == PCI_DEVICE_ID_BSMB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) (device == PCI_DEVICE_ID_ZMID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) (device == PCI_DEVICE_ID_ZSMB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) (device == PCI_DEVICE_ID_SAT_MID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) (device == PCI_DEVICE_ID_SAT_SMB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) (device == PCI_DEVICE_ID_RFLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) * Determine if an IOCB failed because of a link event or firmware reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) lpfc_error_lost_link(IOCB_t *iocbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) #define MENLO_TRANSPORT_TYPE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) #define MENLO_CONTEXT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) #define MENLO_PU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) #define MENLO_TIMEOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) #define SETVAR_MLOMNT 0x103107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) #define SETVAR_MLORST 0x103007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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