^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is part of the Emulex Linux Device Driver for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Fibre Channel Host Bus Adapters. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2016 Emulex. All rights reserved. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * EMULEX and SLI are trademarks of Emulex. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * www.broadcom.com *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Portions Copyright (C) 2004-2005 Christoph Hellwig *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modify it under the terms of version 2 of the GNU General *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Public License as published by the Free Software Foundation. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed in the hope that it will be useful. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * TO BE LEGALLY INVALID. See the GNU General Public License for *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * more details, a copy of which can be found in the file COPYING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * included with this package. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct lpfc_sli2_slim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ELX_MODEL_NAME_SIZE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPFC_PCI_DEV_LP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPFC_PCI_DEV_OC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPFC_SLI_REV2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPFC_SLI_REV3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPFC_SLI_REV4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPFC_MAX_TARGET 4096 /* max number of targets supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) the NameServer before giving up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) cmnd for menlo needs nearly twice as for firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) downloads using bsg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPFC_DEFAULT_XPSGL_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPFC_MAX_SG_TABLESIZE 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPFC_MAX_BG_SLI4_SEG_CNT_DIF 128 /* sg element count for BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LPFC_MIN_SG_SEG_CNT 32 /* sg element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LPFC_MAX_NVME_SEG_CNT 256 /* max SGL element cnt per NVME cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LPFC_VNAME_LEN 100 /* vport symbolic name length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LPFC_MIN_TGT_QDEPTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LPFC_MAX_TGT_QDEPTH 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) collection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Following time intervals are used of adjusting SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * queue depths when there are driver resource error or Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * resource error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 1 Second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Number of exchanges reserved for discovery to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LPFC_DISC_IOCB_BUFF_COUNT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Error Attention event polling interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Define macros for 64 bit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define getPaddr(high, low) ((dma_addr_t)( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Provide maximum configuration definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FC_MAX_ADPTMSG 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX_HBAEVT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX_HBAS_NO_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Number of MSI-X vectors the driver uses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LPFC_MSIX_VECTORS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* lpfc wait event data ready flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LPFC_DATA_READY 0 /* bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* queue dump line buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LPFC_LBUF_SZ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* mailbox system shutdown options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LPFC_MBX_NO_WAIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LPFC_MBX_WAIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum lpfc_polling_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ENABLE_FCP_RING_POLLING = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DISABLE_FCP_RING_INT = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct perf_prof {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint16_t cmd_cpu[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint16_t rsp_cpu[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint16_t qh_cpu[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint16_t wqidx[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Provide for FC4 TYPE x28 - NVME. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * bit mask for FCP and NVME is 0x8 identically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * because they are 32 bit positions distance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LPFC_FC4_TYPE_BITMASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Provide DMA memory definitions the driver uses per port instance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct lpfc_dmabuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void *virt; /* virtual address ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_addr_t phys; /* mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint32_t buffer_tag; /* used for tagged queue ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct lpfc_nvmet_ctxbuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct lpfc_async_xchg_ctx *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct lpfc_iocbq *iocbq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct lpfc_sglq *sglq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct work_struct defer_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct lpfc_dma_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct lpfc_dmabuf *elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uint32_t max_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint32_t current_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct hbq_dmabuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct lpfc_dmabuf hbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct lpfc_dmabuf dbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) uint16_t total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint16_t bytes_recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) uint32_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct lpfc_cq_event cq_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct rqb_dmabuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct lpfc_dmabuf hbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct lpfc_dmabuf dbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint16_t total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint16_t bytes_recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint16_t idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct lpfc_queue *hrq; /* ptr to associated Header RQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct lpfc_queue *drq; /* ptr to associated Data RQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Priority bit. Set value to exceed low water mark in lpfc_mem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MEM_PRI 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Device VPD save area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) typedef struct lpfc_vpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) uint32_t status; /* vpd status value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uint32_t length; /* number of bytes actually returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint32_t rsvd1; /* Revision numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint32_t biuRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint32_t smRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint32_t smFwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint32_t endecRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) uint16_t rBit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint8_t fcphHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint8_t fcphLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) uint8_t feaLevelHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) uint8_t feaLevelLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) uint32_t postKernRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uint32_t opFwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint8_t opFwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uint32_t sli1FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) uint8_t sli1FwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uint32_t sli2FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) uint8_t sli2FwName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uint32_t rsvd3 :20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uint32_t rsvd2 : 3; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint32_t cbg : 1; /* Configure BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) uint32_t cmv : 1; /* Configure Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint32_t ccrp : 1; /* Config Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint32_t csah : 1; /* Configure Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint32_t chbs : 1; /* Cofigure Host Backing store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint32_t cinb : 1; /* Enable Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uint32_t cmx : 1; /* Configure Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uint32_t cmr : 1; /* Configure Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint32_t cmr : 1; /* Configure Max RPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint32_t cmx : 1; /* Configure Max XRIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint32_t cinb : 1; /* Enable Interrupt Notification Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint32_t chbs : 1; /* Cofigure Host Backing store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uint32_t csah : 1; /* Configure Synchronous Abort Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uint32_t ccrp : 1; /* Config Command Ring Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uint32_t cmv : 1; /* Configure Max VPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uint32_t cbg : 1; /* Configure BlockGuard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint32_t rsvd2 : 3; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uint32_t rsvd3 :20; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } sli3Feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } lpfc_vpd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * lpfc stat counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct lpfc_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Statistics for ELS commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uint32_t elsLogiCol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint32_t elsRetryExceeded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint32_t elsXmitRetry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uint32_t elsDelayRetry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) uint32_t elsRcvDrop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint32_t elsRcvFrame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) uint32_t elsRcvRSCN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uint32_t elsRcvRNID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint32_t elsRcvFARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) uint32_t elsRcvFARPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint32_t elsRcvFLOGI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint32_t elsRcvPLOGI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) uint32_t elsRcvADISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint32_t elsRcvPDISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint32_t elsRcvFAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint32_t elsRcvLOGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) uint32_t elsRcvPRLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uint32_t elsRcvPRLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint32_t elsRcvLIRR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint32_t elsRcvRLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t elsRcvRPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint32_t elsRcvRRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint32_t elsRcvRTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uint32_t elsRcvECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uint32_t elsRcvLCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uint32_t elsRcvRDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint32_t elsXmitFLOGI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) uint32_t elsXmitFDISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint32_t elsXmitPLOGI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint32_t elsXmitPRLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint32_t elsXmitADISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint32_t elsXmitLOGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint32_t elsXmitSCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint32_t elsXmitRSCN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uint32_t elsXmitRNID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uint32_t elsXmitFARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint32_t elsXmitFARPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uint32_t elsXmitACC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) uint32_t elsXmitLSRJT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) uint32_t frameRcvBcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint32_t frameRcvMulti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint32_t strayXmitCmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint32_t frameXmitDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint32_t xriCmdCmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint32_t xriStatErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint32_t LinkUp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint32_t LinkDown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint32_t LinkMultiEvent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint32_t NoRcvBuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint32_t fcpCmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uint32_t fcpCmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint32_t fcpRspErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint32_t fcpRemoteStop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uint32_t fcpPortRjt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) uint32_t fcpPortBusy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint32_t fcpError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint32_t fcpLocalErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct lpfc_hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum discovery_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) LPFC_VPORT_FAILED = 1, /* vport has failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LPFC_FDISC = 8, /* FDISC sent for vport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LPFC_NS_REG = 10, /* Register with NameServer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * device authentication / discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LPFC_DISC_AUTH = 13, /* Processing ADISC list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LPFC_VPORT_READY = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum hba_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) LPFC_WARM_START = 1, /* HBA state after selective reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) LPFC_INIT_START = 2, /* Initial state after board reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * CLEAR_LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LPFC_HBA_READY = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) LPFC_HBA_ERROR = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct lpfc_trunk_link_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum hba_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uint8_t fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct lpfc_trunk_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct lpfc_trunk_link_state link0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) link1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) link2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) link3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct lpfc_vport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct lpfc_hba *phba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct list_head listentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint8_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define LPFC_PHYSICAL_PORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define LPFC_NPIV_PORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define LPFC_FABRIC_PORT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum discovery_state port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uint16_t vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint16_t vfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint8_t vpi_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define LPFC_VPI_REGISTERED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint32_t fc_flag; /* FC flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Several of these flags are HBA centric and should be moved to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FC_PT2PT 0x1 /* pt2pt with no fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FC_DISC_TMO 0x4 /* Discovery timer running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define FC_PUBLIC_LOOP 0x8 /* Public loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define FC_NLP_MORE 0x40 /* More node to process in node tbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define FC_FABRIC 0x100 /* We are fabric attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define FC_PT2PT_NO_NVME 0x1000 /* Don't send NVME PRLI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uint32_t ct_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct list_head fc_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Keep counters for the number of entries in each list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uint16_t fc_plogi_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint16_t fc_adisc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint16_t fc_reglogin_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint16_t fc_prli_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) uint16_t fc_unmap_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint16_t fc_map_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint16_t fc_npr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint16_t fc_unused_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct serv_parm fc_sparam; /* buffer for our service parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint32_t fc_myDID; /* fibre channel S_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uint32_t fc_prevDID; /* previous fibre channel S_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct lpfc_name fabric_portname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct lpfc_name fabric_nodename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int32_t stopped; /* HBA has not been restarted since last ERATT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uint8_t fc_linkspeed; /* Link speed after last READ_LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) uint32_t num_disc_nodes; /* in addition to hba_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct lpfc_name fc_nodename; /* fc nodename */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct lpfc_name fc_portname; /* fc portname */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct lpfc_work_evt disc_timeout_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct timer_list fc_disctmo; /* Discovery rescue timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uint8_t fc_ns_retry; /* retries for fabric nameserver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spinlock_t work_port_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint32_t work_port_events; /* Timeout to be handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct timer_list els_tmofunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct timer_list delayed_disc_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int unreg_vpi_cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint8_t load_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define FC_LOADING 0x1 /* HBA in process of loading drvr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FC_ALLOW_FDMI 0x4 /* port is ready for FDMI requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Vport Config Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint32_t cfg_scan_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint32_t cfg_lun_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint32_t cfg_nodev_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint32_t cfg_devloss_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uint32_t cfg_restrict_login;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uint32_t cfg_peer_port_login;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uint32_t cfg_fcp_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uint32_t cfg_use_adisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint32_t cfg_discovery_threads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint32_t cfg_log_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint32_t cfg_enable_fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint32_t cfg_max_luns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint32_t cfg_enable_da_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint32_t cfg_max_scsicmpl_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint32_t cfg_tgt_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint32_t cfg_first_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint32_t dev_loss_tmo_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct fc_vport *fc_vport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct dentry *debug_disc_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct dentry *debug_nodelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct dentry *debug_nvmestat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct dentry *debug_scsistat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct dentry *debug_ioktime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct dentry *debug_hdwqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct dentry *vport_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct lpfc_debugfs_trc *disc_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) atomic_t disc_trc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t stat_data_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) uint8_t stat_data_blocked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct list_head rcv_buffer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned long rcv_buffer_time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint32_t vport_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define STATIC_VPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define FAWWPN_SET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define FAWWPN_PARAM_CHG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint16_t fdmi_num_disc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) uint32_t fdmi_hba_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint32_t fdmi_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* There is a single nvme instance per vport. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct nvme_fc_local_port *localport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) uint8_t nvmei_support; /* driver supports NVME Initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uint32_t last_fcp_wqidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint32_t rcv_flogi_cnt; /* How many unsol FLOGIs ACK'd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct hbq_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) uint16_t entry_count; /* Current number of HBQ slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uint16_t buffer_count; /* Current number of buffers posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uint32_t hbqPutIdx; /* HBQ slot to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void *hbq_virt; /* Virtual ptr to this hbq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Callback for HBQ buffer allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Callback for HBQ buffer free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) void (*hbq_free_buffer) (struct lpfc_hba *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct hbq_dmabuf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* this matches the position in the lpfc_hbq_defs array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define LPFC_ELS_HBQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define LPFC_MAX_HBQS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) enum hba_temp_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) HBA_NORMAL_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) HBA_OVER_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) enum intr_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) INTx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define LPFC_CT_CTX_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct unsol_rcv_ct_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) uint32_t ctxt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) uint32_t SID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) uint32_t valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define UNSOL_INVALID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define UNSOL_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint16_t oxid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint16_t rxid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define LPFC_USER_LINK_SPEED_64G 64 /* 64 Gigabaud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_64G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32, 64"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) enum nemb_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) nemb_mse = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) nemb_hbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum mbox_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mbox_rd = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mbox_wr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) enum dma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dma_mbox = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dma_ebuf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enum sta_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sta_pre_addr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sta_pos_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct lpfc_mbox_ext_buf_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uint32_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define LPFC_BSG_MBOX_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define LPFC_BSG_MBOX_HOST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define LPFC_BSG_MBOX_PORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define LPFC_BSG_MBOX_DONE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define LPFC_BSG_MBOX_ABTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) enum nemb_type nembType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) enum mbox_type mboxType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uint32_t numBuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uint32_t mbxTag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint32_t seqNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct lpfc_dmabuf *mbx_dmabuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct list_head ext_dmabuf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct lpfc_epd_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Expedite pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spinlock_t lock; /* lock for expedite pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) enum ras_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) REG_INPROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct lpfc_ras_fwlog {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) uint8_t *fwlog_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) uint32_t fw_buffcount; /* Buffer size posted to FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define LPFC_RAS_BUFF_ENTERIES 16 /* Each entry can hold max of 64k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define LPFC_RAS_MAX_ENTRY_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define LPFC_RAS_MIN_BUFF_POST_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define LPFC_RAS_MAX_BUFF_POST_SIZE (1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint32_t fw_loglevel; /* Log level set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct lpfc_dmabuf lwpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct list_head fwlog_buff_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* RAS support status on adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bool ras_hwsupport; /* RAS Support available on HW or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) bool ras_enabled; /* Ras Enabled for the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define LPFC_RAS_DISABLE_LOGGING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define LPFC_RAS_ENABLE_LOGGING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) enum ras_state state; /* RAS logging running state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DBG_LOG_STR_SZ 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define DBG_LOG_SZ 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct dbg_log_ent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) char log[DBG_LOG_STR_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u64 t_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) enum lpfc_irq_chann_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Assign IRQs to all possible cpus that have hardware queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) NORMAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Assign IRQs only to cpus on the same numa node as HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) NUMA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Assign IRQs only on non-hyperthreaded CPUs. This is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * same as normal_mode, but assign IRQS only on physical CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) NHT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct lpfc_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* SCSI interface function jump table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct lpfc_io_buf * (*lpfc_get_scsi_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (struct lpfc_hba *phba, struct lpfc_nodelist *ndlp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct scsi_cmnd *cmnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int (*lpfc_scsi_prep_dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (struct lpfc_hba *, struct lpfc_io_buf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void (*lpfc_scsi_unprep_dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (struct lpfc_hba *, struct lpfc_io_buf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void (*lpfc_release_scsi_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (struct lpfc_hba *, struct lpfc_io_buf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void (*lpfc_rampdown_queue_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) void (*lpfc_scsi_prep_cmnd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (struct lpfc_vport *, struct lpfc_io_buf *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct lpfc_nodelist *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* IOCB interface function jump table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int (*__lpfc_sli_issue_iocb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) (struct lpfc_hba *, uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct lpfc_iocbq *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct lpfc_iocbq *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) IOCB_t * (*lpfc_get_iocb_from_iocbq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (struct lpfc_iocbq *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void (*lpfc_scsi_cmd_iocb_cmpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* MBOX interface function jump table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int (*lpfc_sli_issue_mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Slow-path IOCB process function jump table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) void (*lpfc_sli_handle_slow_ring_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uint32_t mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* INIT device interface function jump table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int (*lpfc_sli_hbq_to_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int (*lpfc_sli_brdrestart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int (*lpfc_sli_brdready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) (struct lpfc_hba *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void (*lpfc_handle_eratt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) void (*lpfc_stop_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int (*lpfc_hba_init_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (struct lpfc_hba *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int (*lpfc_hba_down_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) (struct lpfc_hba *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int (*lpfc_selective_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (struct lpfc_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int (*lpfc_bg_scsi_prep_dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) (struct lpfc_hba *, struct lpfc_io_buf *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Add new entries here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* expedite pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct lpfc_epd_pool epd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* SLI4 specific HBA data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct lpfc_sli4_hba sli4_hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct delayed_work eq_delay_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define LPFC_IDLE_STAT_DELAY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct delayed_work idle_stat_delay_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct lpfc_sli sli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) uint32_t sli3_options; /* Mask of enabled SLI3 options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define LPFC_SLI3_HBQ_ENABLED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define LPFC_SLI3_NPIV_ENABLED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define LPFC_SLI3_VPORT_TEARDOWN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define LPFC_SLI3_CRP_ENABLED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define LPFC_SLI3_BG_ENABLED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define LPFC_SLI3_DSS_ENABLED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define LPFC_SLI4_PERFH_ENABLED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define LPFC_SLI4_PHWQ_ENABLED 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uint32_t iocb_cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uint32_t iocb_rsp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct lpfc_trunk_link trunk_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) enum hba_state link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uint32_t link_flag; /* link state flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* This flag is set while issuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* INIT_LINK mailbox command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define LS_MDS_LINK_DOWN 0x8 /* MDS Diagnostics Link Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define LS_MDS_LOOPBACK 0x10 /* MDS Diagnostics Link Up (Loopback) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uint32_t hba_flag; /* hba generic flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define DEFER_ERATT 0x2 /* Deferred error attention in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define HBA_PERSISTENT_TOPO 0x20 /* Persistent topology support in hba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define ELS_XRI_ABORT_EVENT 0x40 /* ELS_XRI abort event was queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define ASYNC_EVENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define LINK_DISABLED 0x100 /* Link disabled by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define HBA_IOQ_FLUSH 0x8000 /* FCP/NVME I/O queues being flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define HBA_FORCED_LINK_SPEED 0x40000 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Firmware supports Forced Link Speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define HBA_FLOGI_ISSUED 0x100000 /* FLOGI was issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define HBA_DEFER_FLOGI 0x800000 /* Defer FLOGI till read_sparm cmpl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct completion *fw_dump_cmpl; /* cmpl event tracker for fw_dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct lpfc_dmabuf slim2p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) MAILBOX_t *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint32_t *mbox_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint32_t ha_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct _PCB *pcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct _IOCB *IOCBs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct lpfc_dmabuf hbqslimp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint16_t pci_cfg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint8_t fc_linkspeed; /* Link speed after last READ_LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uint32_t fc_eventTag; /* event tag for link attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uint32_t link_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* These fields used to be binfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) uint32_t fc_pref_DID; /* preferred D_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint8_t fc_pref_ALPA; /* preferred AL_PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) uint32_t fc_edtov; /* E_D_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) uint32_t fc_arbtov; /* ARB_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) uint32_t fc_ratov; /* R_A_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint32_t fc_rttov; /* R_T_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) uint32_t fc_altov; /* AL_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) uint32_t fc_crtov; /* C_R_TOV timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct serv_parm fc_fabparam; /* fabric service parameters buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) uint32_t lmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) uint32_t fc_topology; /* link topology, from LINK INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) uint32_t fc_topology_changed; /* link topology, from LINK INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct lpfc_stats fc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) uint32_t nport_event_cnt; /* timestamp for nlplist entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint8_t wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) uint32_t RandomData[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) uint8_t fcp_embed_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uint8_t nvme_support; /* Firmware supports NVME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uint8_t nvmet_support; /* driver supports NVMET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define LPFC_NVMET_MAX_PORTS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) uint8_t mds_diags_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) uint8_t bbcredit_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uint8_t enab_exp_wqcq_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 nsler; /* Firmware supports FC-NVMe-2 SLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* HBA Config Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint32_t cfg_ack0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) uint32_t cfg_xri_rebalancing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) uint32_t cfg_xpsgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) uint32_t cfg_enable_npiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) uint32_t cfg_enable_rrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) uint32_t cfg_topology;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) uint32_t cfg_link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define LPFC_FCF_FOV 1 /* Fast fcf failover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint32_t cfg_fcf_failover_policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) uint32_t cfg_fcp_io_sched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint32_t cfg_ns_query;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint32_t cfg_fcp2_no_tgt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uint32_t cfg_cr_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) uint32_t cfg_cr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) uint32_t cfg_multi_ring_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) uint32_t cfg_multi_ring_rctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint32_t cfg_multi_ring_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) uint32_t cfg_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) uint32_t cfg_poll_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) uint32_t cfg_task_mgmt_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) uint32_t cfg_use_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) uint32_t cfg_auto_imax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) uint32_t cfg_fcp_imax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) uint32_t cfg_force_rscn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) uint32_t cfg_cq_poll_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) uint32_t cfg_cq_max_proc_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) uint32_t cfg_fcp_cpu_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint32_t cfg_fcp_mq_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint32_t cfg_hdw_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) uint32_t cfg_irq_chann;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uint32_t cfg_suppress_rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) uint32_t cfg_nvme_oas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) uint32_t cfg_nvme_embed_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) uint32_t cfg_nvmet_mrq_post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) uint32_t cfg_nvmet_mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) uint32_t cfg_enable_nvmet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uint32_t cfg_nvme_enable_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) uint32_t cfg_nvmet_fb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uint32_t cfg_total_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) uint32_t cfg_sg_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint32_t cfg_nvme_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uint32_t cfg_scsi_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uint32_t cfg_sg_dma_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uint64_t cfg_soft_wwnn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) uint64_t cfg_soft_wwpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) uint32_t cfg_hba_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint32_t cfg_enable_hba_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint32_t cfg_enable_hba_heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint32_t cfg_fof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint32_t cfg_EnableXLane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint8_t cfg_oas_tgt_wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint8_t cfg_oas_vpt_wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint32_t cfg_oas_lun_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define OAS_LUN_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define OAS_LUN_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint32_t cfg_oas_lun_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define OAS_LUN_STATUS_EXISTS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) uint32_t cfg_oas_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define OAS_FIND_ANY_VPORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define OAS_FIND_ANY_TARGET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define OAS_LUN_VALID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) uint32_t cfg_oas_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) uint32_t cfg_XLanePriority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uint32_t cfg_enable_bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uint32_t cfg_prot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uint32_t cfg_prot_guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) uint32_t cfg_hostmem_hgp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) uint32_t cfg_log_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) uint32_t cfg_enable_fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define LPFC_ENABLE_FCP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define LPFC_ENABLE_NVME 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define LPFC_ENABLE_BOTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #if (IS_ENABLED(CONFIG_NVME_FC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define LPFC_MAX_ENBL_FC4_TYPE LPFC_ENABLE_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define LPFC_DEF_ENBL_FC4_TYPE LPFC_ENABLE_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define LPFC_MAX_ENBL_FC4_TYPE LPFC_ENABLE_FCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define LPFC_DEF_ENBL_FC4_TYPE LPFC_ENABLE_FCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint32_t cfg_aer_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint32_t cfg_sriov_nr_virtfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) uint32_t cfg_request_firmware_upgrade;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uint32_t cfg_suppress_link_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uint32_t cfg_rrq_xri_bitmap_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint32_t cfg_delay_discovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uint32_t cfg_sli_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) uint32_t cfg_fdmi_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) uint32_t cfg_enable_SmartSAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uint32_t cfg_enable_mds_diags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) uint32_t cfg_ras_fwlog_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) uint32_t cfg_ras_fwlog_buffsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) uint32_t cfg_ras_fwlog_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) uint32_t cfg_enable_bbcr; /* Enable BB Credit Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) uint32_t cfg_enable_dpp; /* Enable Direct Packet Push */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) uint32_t cfg_enable_pbde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct nvmet_fc_target_port *targetport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) lpfc_vpd_t vpd; /* vital product data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct pci_dev *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct list_head work_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uint32_t work_ha; /* Host Attention Bits for WT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) uint32_t work_ha_mask; /* HA Bits owned by WT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uint32_t work_hs; /* HS stored in case of ERRAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) uint32_t work_status[2]; /* Extra status from SLIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) wait_queue_head_t work_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct task_struct *worker_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned long data_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) uint32_t border_sge_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint32_t hbq_in_use; /* HBQs in use flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint32_t hbq_count; /* Count of configured HBQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) void __iomem *slim_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PCI BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PCI BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PCI BAR0 with dual-ULP support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PCI BAR2 with dual-ULP support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PCI BAR4 with dual-ULP support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define PCI_64BIT_BAR0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define PCI_64BIT_BAR2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define PCI_64BIT_BAR4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) void __iomem *MBslimaddr; /* virtual address for mbox cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) void __iomem *HAregaddr; /* virtual address for host attn reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) void __iomem *CAregaddr; /* virtual address for chip attn reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) void __iomem *HSregaddr; /* virtual address for host status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) void __iomem *HCregaddr; /* virtual address for host ctl reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct lpfc_pgp *port_gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int brd_no; /* FC board number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) char SerialNumber[32]; /* adapter Serial Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) char BIOSVersion[16]; /* Boot BIOS version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) char ModelDesc[256]; /* Model Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) char ModelName[80]; /* Model Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) char ProgramType[256]; /* Program Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) char Port[20]; /* Port No */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) uint8_t vpd_flag; /* VPD data flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define VPD_MODEL_DESC 0x1 /* valid vpd model description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define VPD_MODEL_NAME 0x2 /* valid vpd model name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define VPD_PORT 0x8 /* valid vpd port data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define VPD_MASK 0xf /* mask for any vpd data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint8_t soft_wwn_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct timer_list fcp_poll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct timer_list eratt_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint32_t eratt_poll_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint64_t bg_guard_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint64_t bg_apptag_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint64_t bg_reftag_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* fastpath list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct list_head lpfc_scsi_buf_list_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct list_head lpfc_scsi_buf_list_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uint32_t total_scsi_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct list_head lpfc_iocb_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) uint32_t total_iocbq_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct list_head active_rrq_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) spinlock_t hbalock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* dma_mem_pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct dma_pool *lpfc_sg_dma_buf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct dma_pool *lpfc_mbuf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct dma_pool *lpfc_hrb_pool; /* header receive buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct dma_pool *lpfc_drb_pool; /* data receive buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct dma_pool *lpfc_nvmet_drb_pool; /* data receive buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct dma_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct dma_pool *lpfc_cmd_rsp_buf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct lpfc_dma_pool lpfc_mbuf_safety_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mempool_t *mbox_mem_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mempool_t *nlp_mem_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) mempool_t *rrq_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mempool_t *active_rrq_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct fc_host_statistics link_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) enum lpfc_irq_chann_mode irq_chann_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) enum intr_type_t intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) uint32_t intr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define LPFC_INTR_ERROR 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct list_head port_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) spinlock_t port_list_lock; /* lock for port_list mutations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct lpfc_vport *pport; /* physical lpfc_vport pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) uint16_t max_vpi; /* Maximum virtual nports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define LPFC_MAX_VPI 0xFF /* Max number VPI supported 0 - 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define LPFC_MAX_VPORTS 0x100 /* Max vports per port, with pport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) uint16_t max_vports; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * For IOV HBAs max_vpi can change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * after a reset. max_vports is max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * number of vports present. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * be greater than max_vpi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) uint16_t vpi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) uint16_t vfi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) unsigned long *vpi_bmask; /* vpi allocation table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) uint16_t *vpi_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) uint16_t vpi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct list_head lpfc_vpi_blk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Data structure used by fabric iocb scheduler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct list_head fabric_iocb_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) atomic_t fabric_iocb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct timer_list fabric_block_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned long bit_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define FABRIC_COMANDS_BLOCKED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) atomic_t num_rsrc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) atomic_t num_cmd_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned long last_rsrc_error_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned long last_ramp_down_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct dentry *hba_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) atomic_t debugfs_vport_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct dentry *debug_multixri_pools;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct dentry *debug_hbqinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct dentry *debug_dumpHostSlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct dentry *debug_dumpHBASlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct dentry *debug_writeGuard; /* inject write guard_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct dentry *debug_writeApp; /* inject write app_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct dentry *debug_writeRef; /* inject write ref_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct dentry *debug_readGuard; /* inject read guard_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct dentry *debug_readApp; /* inject read app_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct dentry *debug_readRef; /* inject read ref_tag errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct dentry *debug_nvmeio_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct dentry *debug_hdwqinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #ifdef LPFC_HDWQ_LOCK_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct dentry *debug_lockstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct dentry *debug_ras_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) atomic_t nvmeio_trc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) uint32_t nvmeio_trc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) uint32_t nvmeio_trc_output_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* T10 DIF error injection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) uint32_t lpfc_injerr_wgrd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) uint32_t lpfc_injerr_wapp_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) uint32_t lpfc_injerr_wref_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) uint32_t lpfc_injerr_rgrd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) uint32_t lpfc_injerr_rapp_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) uint32_t lpfc_injerr_rref_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) uint32_t lpfc_injerr_nportid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct lpfc_name lpfc_injerr_wwpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) sector_t lpfc_injerr_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define LPFC_INJERR_LBA_OFF (sector_t)(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct dentry *debug_slow_ring_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct lpfc_debugfs_trc *slow_ring_trc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) atomic_t slow_ring_trc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* iDiag debugfs sub-directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct dentry *idiag_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct dentry *idiag_pci_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct dentry *idiag_bar_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct dentry *idiag_que_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct dentry *idiag_que_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct dentry *idiag_drb_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct dentry *idiag_ctl_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct dentry *idiag_mbx_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct dentry *idiag_ext_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) uint8_t lpfc_idiag_last_eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) uint16_t nvmeio_trc_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Used for deferred freeing of ELS data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct list_head elsbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int elsbuf_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int elsbuf_prev_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) uint8_t temp_sensor_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Fields used for heart beat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned long last_completion_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unsigned long skipped_hb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct timer_list hb_tmofunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) uint8_t hb_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct timer_list rrq_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) enum hba_temp_state over_temp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* ndlp reference management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) spinlock_t ndlp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * Following bit will be set for all buffer tags which are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * associated with any HBQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define QUE_BUFTAG_BIT (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) uint32_t buffer_tag_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int wait_4_mlo_maint_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) wait_queue_head_t wait_4_mlo_m_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* data structure used for latency data collection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define LPFC_NO_BUCKET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define LPFC_LINEAR_BUCKET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define LPFC_POWER2_BUCKET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) uint8_t bucket_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) uint32_t bucket_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) uint32_t bucket_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Maximum number of events that can be outstanding at any time*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define LPFC_MAX_EVT_COUNT 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) atomic_t fast_event_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) uint32_t fcoe_eventtag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) uint32_t fcoe_eventtag_at_fcf_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) uint32_t fcoe_cvl_eventtag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) uint32_t fcoe_cvl_eventtag_attn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct lpfc_fcf fcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) uint8_t fc_map[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) uint8_t valid_vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) uint16_t vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct list_head fcf_conn_rec_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) bool defer_flogi_acc_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) uint16_t defer_flogi_acc_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) uint16_t defer_flogi_acc_ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct list_head ct_ev_waiters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) uint32_t ctx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* RAS Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct lpfc_ras_fwlog ras_fwlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) uint8_t menlo_flag; /* menlo generic flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) uint32_t iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) uint32_t iocb_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) atomic_t sdev_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) spinlock_t devicelock; /* lock for luns list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) mempool_t *device_data_mem_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct list_head luns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) uint16_t sfp_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) uint16_t sfp_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) uint16_t hdwqstat_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define LPFC_CHECK_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define LPFC_CHECK_NVME_IO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define LPFC_CHECK_NVMET_IO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define LPFC_CHECK_SCSI_IO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) uint16_t ktime_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) uint64_t ktime_data_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) uint64_t ktime_status_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) uint64_t ktime_last_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) uint64_t ktime_seg1_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) uint64_t ktime_seg1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) uint64_t ktime_seg1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) uint64_t ktime_seg2_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) uint64_t ktime_seg2_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) uint64_t ktime_seg2_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) uint64_t ktime_seg3_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) uint64_t ktime_seg3_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) uint64_t ktime_seg3_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) uint64_t ktime_seg4_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) uint64_t ktime_seg4_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) uint64_t ktime_seg4_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) uint64_t ktime_seg5_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) uint64_t ktime_seg5_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) uint64_t ktime_seg5_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) uint64_t ktime_seg6_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) uint64_t ktime_seg6_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) uint64_t ktime_seg6_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) uint64_t ktime_seg7_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) uint64_t ktime_seg7_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) uint64_t ktime_seg7_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) uint64_t ktime_seg8_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) uint64_t ktime_seg8_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) uint64_t ktime_seg8_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) uint64_t ktime_seg9_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) uint64_t ktime_seg9_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) uint64_t ktime_seg9_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) uint64_t ktime_seg10_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) uint64_t ktime_seg10_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) uint64_t ktime_seg10_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct hlist_node cpuhp; /* used for cpuhp per hba callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct timer_list cpuhp_poll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct list_head poll_list; /* slowpath eq polling list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define LPFC_POLL_HB 1 /* slowpath heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define LPFC_POLL_FASTPATH 0 /* called from fastpath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define LPFC_POLL_SLOWPATH 1 /* called from slowpath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) char os_host_name[MAXHOSTNAMELEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* SCSI host template information - for physical port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct scsi_host_template port_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* SCSI host template information - for all vports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct scsi_host_template vport_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) atomic_t dbg_log_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) atomic_t dbg_log_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) atomic_t dbg_log_dmping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct dbg_log_ent dbg_log[DBG_LOG_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static inline struct Scsi_Host *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) lpfc_shost_from_vport(struct lpfc_vport *vport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) lpfc_set_loopback_flag(struct lpfc_hba *phba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (phba->cfg_topology == FLAGS_LOCAL_LB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) phba->link_flag |= LS_LOOPBACK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) phba->link_flag &= ~LS_LOOPBACK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) lpfc_is_link_up(struct lpfc_hba *phba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return phba->link_state == LPFC_LINK_UP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) phba->link_state == LPFC_CLEAR_LA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) phba->link_state == LPFC_HBA_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) lpfc_worker_wake_up(struct lpfc_hba *phba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* Set the lpfc data pending flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) set_bit(LPFC_DATA_READY, &phba->data_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Wake up worker thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) wake_up(&phba->work_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) lpfc_readl(void __iomem *addr, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) temp = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (temp == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) *data = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) lpfc_sli_read_hs(struct lpfc_hba *phba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * There was a link/board error. Read the status register to retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * the error event and process it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) phba->sli.slistat.err_attn_event++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Save status info and check for unplug error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Clear chip Host Attention error bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) writel(HA_ERATT, phba->HAregaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) readl(phba->HAregaddr); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) phba->pport->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static inline struct lpfc_sli_ring *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) lpfc_phba_elsring(struct lpfc_hba *phba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Return NULL if sli_rev has become invalid due to bad fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (phba->sli_rev != LPFC_SLI_REV4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) phba->sli_rev != LPFC_SLI_REV3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) phba->sli_rev != LPFC_SLI_REV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (phba->sli_rev == LPFC_SLI_REV4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (phba->sli4_hba.els_wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return phba->sli4_hba.els_wq->pring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return &phba->sli.sli3_ring[LPFC_ELS_RING];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * lpfc_next_online_cpu - Finds next online CPU on cpumask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * @mask: Pointer to phba's cpumask member.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * @start: starting cpu index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * Note: If no valid cpu found, then nr_cpu_ids is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) lpfc_next_online_cpu(const struct cpumask *mask, unsigned int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) unsigned int cpu_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for_each_cpu_wrap(cpu_it, mask, start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (cpu_online(cpu_it))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return cpu_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * lpfc_sli4_mod_hba_eq_delay - update EQ delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * @phba: Pointer to HBA context object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * @q: The Event Queue to update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * @delay: The delay value (in us) to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) lpfc_sli4_mod_hba_eq_delay(struct lpfc_hba *phba, struct lpfc_queue *eq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u32 delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct lpfc_register reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) reg_data.word0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bf_set(lpfc_sliport_eqdelay_id, ®_data, eq->queue_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) bf_set(lpfc_sliport_eqdelay_delay, ®_data, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) writel(reg_data.word0, phba->sli4_hba.u.if_type2.EQDregaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) eq->q_mode = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * Macro that declares tables and a routine to perform enum type to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * ascii string lookup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * Defines a <key,value> table for an enum. Uses xxx_INIT defines for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * the enum to populate the table. Macro defines a routine (named
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * by caller) that will search all elements of the table for the key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * and return the name string if found or "Unrecognized" if not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define DECLARE_ENUM2STR_LOOKUP(routine, enum_name, enum_init) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static struct { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) enum enum_name value; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) char *name; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) } fc_##enum_name##_e2str_names[] = enum_init; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static const char *routine(enum enum_name table_key) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) char *name = "Unrecognized"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) for (i = 0; i < ARRAY_SIZE(fc_##enum_name##_e2str_names); i++) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (fc_##enum_name##_e2str_names[i].value == table_key) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) name = fc_##enum_name##_e2str_names[i].name; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return name; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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