^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The full GNU General Public License is included in this distribution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * in the file called LICENSE.GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * * Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifndef _SCU_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define _SCU_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * This file contains the constants and structures for the SCU memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCU_VIIT_ENTRY_ID_SHIFT (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCU_VIIT_ENTRY_FUNCTION_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCU_VIIT_ENTRY_IPPTMODE_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCU_VIIT_ENTRY_LPVIE_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCU_VIIT_ENTRY_ID_VIIT (1 << SCU_VIIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCU_VIIT_ENTRY_ID_IIT (2 << SCU_VIIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SCU_VIIT_ENTRY_ID_VIRT_EXP (3 << SCU_VIIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCU_VIIT_IPPT_INITIATOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SCU_VIIT_IPPT_SSP_INITIATOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) | SCU_VIIT_IPPT_SMP_INITIATOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | SCU_VIIT_IPPT_STP_INITIATOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCU_VIIT_STATUS_RNC_VALID (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCU_VIIT_STATUS_ADDRESS_VALID (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCU_VIIT_STATUS_RNI_VALID (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCU_VIIT_STATUS_ALL_VALID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SCU_VIIT_STATUS_RNC_VALID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | SCU_VIIT_STATUS_ADDRESS_VALID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) | SCU_VIIT_STATUS_RNI_VALID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCU_VIIT_IPPT_SMP_TARGET (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * struct scu_viit_entry - This is the SCU Virtual Initiator Table Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct scu_viit_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * This must be encoded as to the type of initiator that is being constructed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * for this port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Virtual initiator high SAS Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 initiator_sas_address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Virtual initiator low SAS Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 initiator_sas_address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * This must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* IIT Status Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SCU_IIT_ENTRY_ID_MASK (0xC0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SCU_IIT_ENTRY_ID_SHIFT (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SCU_IIT_ENTRY_STATUS_UPDATE_MASK (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SCU_IIT_ENTRY_STATUS_UPDATE_SHIFT (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SCU_IIT_ENTRY_LPI_MASK (0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SCU_IIT_ENTRY_LPI_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SCU_IIT_ENTRY_STATUS_MASK (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SCU_IIT_ENTRY_STATUS_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* IIT Remote Initiator Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SCU_IIT_ENTRY_REMOTE_TAG_MASK (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SCU_IIT_ENTRY_REMOTE_RNC_MASK (0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SCU_IIT_ENTRY_REMOTE_RNC_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SCU_IIT_ENTRY_ID_INVALID (0 << SCU_IIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SCU_IIT_ENTRY_ID_VIIT (1 << SCU_IIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SCU_IIT_ENTRY_ID_IIT (2 << SCU_IIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SCU_IIT_ENTRY_ID_VIRT_EXP (3 << SCU_IIT_ENTRY_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * struct scu_iit_entry - This will be implemented later when we support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * virtual functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct scu_iit_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 remote_initiator_sas_address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 remote_initiator_sas_address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 remote_initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Generate a value for an SCU register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SCU_GEN_VALUE(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (((value) << name ## _SHIFT) & (name ## _MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Generate a bit value for an SCU register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Make sure that the register MASK is just a single bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SCU_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SCU_GEN_VALUE(name, ((u32)1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SCU_SET_BIT(name, reg_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ((reg_value) | SCU_GEN_BIT(name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SCU_CLEAR_BIT(name, reg_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ((reg_value)$ ~(SCU_GEN_BIT(name)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Unions for bitfield definitions of SCU Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * SMU Post Context Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SMU_PCP_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SMU_ISR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SMU_ISR_QUEUE_ERROR SMU_ISR_GEN_BIT(QUEUE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SMU_ISR_COMPLETION SMU_ISR_GEN_BIT(COMPLETION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SMU_IMR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SMU_IMR_QUEUE_ERROR SMU_IMR_GEN_BIT(QUEUE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SMU_IMR_COMPLETION SMU_IMR_GEN_BIT(COMPLETION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SMU_ICC_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SMU_TCR_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SMU_TCR_GEN_BIT(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SMU_CQPR_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SMU_CQPR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SMU_CQGR_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SMU_CQGR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SMU_CQGR_CYCLE_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SMU_CQGR_GEN_BIT(CYCLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SMU_CQGR_EVENT_CYCLE_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SMU_CQGR_GET_POINTER_SET(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SMU_CQGR_GEN_VAL(POINTER, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SMU_CQC_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SMU_CQC_QUEUE_LIMIT_SET(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SMU_CQC_EVENT_LIMIT_SET(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SMU_CQC_GEN_VAL(EVENT_LIMIT, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SMU_DCC_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SMU_DCC_GET_MAX_PEG(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SMU_DCC_GET_MAX_LP(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SMU_DCC_GET_MAX_TC(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SMU_DCC_GET_MAX_RNC(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK (0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK (0x7FF0FFF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SMU_CGUCR_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SMU_CGUCR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SMU_SMUCSR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SCU_RAM_INIT_COMPLETED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ((1 << (pe)) << ((peg) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SMU_RESET_ALL_PROTOCOL_ENGINES() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * It seems to make sense that if you are going to reset the protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * engine group that you would also reset all of the protocol engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (1 << ((peg) + 20)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SMU_RESET_SCU() (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SMU_TCA_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SMU_TCA_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SCU_UFQC_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SCU_UFQC_QUEUE_SIZE_SET(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SCU_UFQPP_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SCU_UFQPP_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * * SDMA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SCU_UFQGP_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SCU_UFQGP_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SCU_UFQGP_CYCLE_BIT(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SCU_UFQGP_GET_POINTER(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SCU_UFQGP_GEN_VALUE(POINTER, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SCU_UFQGP_ENABLE(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) (SCU_UFQGP_GEN_BIT(ENABLE) | value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SCU_UFQGP_DISABLE(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SCU_UFQGP_VALUE(bit, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SCU_PDMACR_GEN_VALUE(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SCU_PDMACR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SCU_PDMACR_BE_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SCU_CDMACR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * * SCU Link Layer Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SCU_SAS_LLSTA_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* TODO: Where is the SATA_PSELTOV register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * * SCU SAS Maximum Arbitration Wait Time Timeout Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define SCU_SAS_MAWTTOV_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * TODO: Where is the SAS_LNKTOV register?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * TODO: Where is the SAS_PHYTOV register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SCU_SAS_TIID_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SCU_SAS_TIID_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* SAS Identify Frame PHY Identifier Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define SCU_SAS_TIPID_GEN_VALUE(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SCU_SAS_TIPID_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SCU_SAS_PCFG_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SCU_ENSPINUP_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SCU_ENSPINUP_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define SCU_SAS_PHYCAP_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define SCU_SAS_PHYCAP_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFFFF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SCU_PSZGCR_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define SCU_PSZGCR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444FFC9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define SCU_PEG_SCUVZECR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * * Port Task Scheduler registers shift and mask values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SCU_PTSGCR_GEN_VAL(name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define SCU_PTSGCR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define SCU_RTCR_GEN_VAL(name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) SCU_GEN_VALUE(SCU_PTSG_ ## name, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SCU_RTCCR_GEN_VAL(name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define SCU_PTSxCR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define SCU_PTSxSR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * * SMU Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * SMU Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * These registers are based off of BAR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * To calculate the offset for other functions use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * BAR0 + FN# * SystemPageSize * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * The TCA is only accessable from FN#0 (Physical Function) and each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * TCA0 for FN#0 is at BAR0 + 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * TCA1 for FN#1 is at BAR0 + 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Accessable to all FN#s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define SCU_SMU_PCP_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define SCU_SMU_AMR_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define SCU_SMU_ISR_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SCU_SMU_IMR_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define SCU_SMU_ICC_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define SCU_SMU_HTTLBAR_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define SCU_SMU_HTTUBAR_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define SCU_SMU_TCR_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define SCU_SMU_CQLBAR_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define SCU_SMU_CQUBAR_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define SCU_SMU_CQPR_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define SCU_SMU_CQGR_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define SCU_SMU_CQC_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Accessable to FN#0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define SCU_SMU_RNCLBAR_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define SCU_SMU_RNCUBAR_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define SCU_SMU_DCC_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define SCU_SMU_DFC_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define SCU_SMU_SMUCSR_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define SCU_SMU_SCUSRCR_OFFSET 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define SCU_SMU_SMAW_OFFSET 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define SCU_SMU_SMDW_OFFSET 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Accessable to FN#0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define SCU_SMU_TCA_OFFSET 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Accessable to all FN#s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SCU_SMU_MT_MLAR0_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SCU_SMU_MT_MUAR0_OFFSET 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SCU_SMU_MT_MDR0_OFFSET 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define SCU_SMU_MT_VCR0_OFFSET 0x200C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define SCU_SMU_MT_MLAR1_OFFSET 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define SCU_SMU_MT_MUAR1_OFFSET 0x2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define SCU_SMU_MT_MDR1_OFFSET 0x2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define SCU_SMU_MT_VCR1_OFFSET 0x201C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define SCU_SMU_MPBA_OFFSET 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * struct smu_registers - These are the SMU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct smu_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* 0x0000 PCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 post_context_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* 0x0004 AMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 address_modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 reserved_08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 reserved_0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* 0x0010 ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* 0x0014 IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* 0x0018 ICC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 interrupt_coalesce_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 reserved_1C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* 0x0020 HTTLBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 host_task_table_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* 0x0024 HTTUBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u32 host_task_table_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* 0x0028 TCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 task_context_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 reserved_2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* 0x0030 CQLBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 completion_queue_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* 0x0034 CQUBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 completion_queue_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u32 reserved_38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 reserved_3C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* 0x0040 CQPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 completion_queue_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* 0x0044 CQGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 completion_queue_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* 0x0048 CQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 completion_queue_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 reserved_4C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 reserved_5x[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 reserved_6x[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 reserved_7x[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Accessable to FN#0 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * 0x0080 RNCLBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 remote_node_context_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* 0x0084 RNCUBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 remote_node_context_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 reserved_88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 reserved_8C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* 0x0090 DCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 device_context_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* 0x0094 DFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u32 device_function_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* 0x0098 SMUCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 control_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* 0x009C SCUSRCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 soft_reset_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* 0x00A0 SMAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u32 mmr_address_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* 0x00A4 SMDW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u32 mmr_data_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* 0x00A8 CGUCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 clock_gating_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* 0x00AC CGUPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 clock_gating_performance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* A whole bunch of reserved space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 reserved_Bx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u32 reserved_Cx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 reserved_Dx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) u32 reserved_Ex[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u32 reserved_Fx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u32 reserved_1xx[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u32 reserved_2xx[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u32 reserved_3xx[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Accessable to FN#0 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * 0x0400 TCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u32 task_context_assignment[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* MSI-X registers not included */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * SDMA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define SCU_SDMA_BASE 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define SCU_SDMA_PUFATLHAR_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define SCU_SDMA_PUFATUHAR_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define SCU_SDMA_UFLHBAR_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define SCU_SDMA_UFUHBAR_OFFSET 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define SCU_SDMA_UFQC_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define SCU_SDMA_UFQPP_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define SCU_SDMA_UFQGP_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define SCU_SDMA_PDMACR_OFFSET 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define SCU_SDMA_CDMACR_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * struct scu_sdma_registers - These are the SCU SDMA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct scu_sdma_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* 0x0000 PUFATLHAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 uf_address_table_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* 0x0004 PUFATUHAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u32 uf_address_table_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* 0x0008 UFLHBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 uf_header_base_address_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* 0x000C UFUHBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 uf_header_base_address_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* 0x0010 UFQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) u32 unsolicited_frame_queue_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* 0x0014 UFQPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 unsolicited_frame_put_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* 0x0018 UFQGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 unsolicited_frame_get_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* 0x001C PDMACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 pdma_configuration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Reserved until offset 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 reserved_0020_007C[0x18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* 0x0080 CDMACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u32 cdma_configuration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Remainder SDMA register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 reserved_0084_0400[0xDF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * * SCU Link Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define SCU_PEG0_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SCU_PEG1_OFFSET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define SCU_TL0_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define SCU_TL1_OFFSET 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SCU_TL2_OFFSET 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SCU_TL3_OFFSET 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SCU_LL_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define SCU_LL0_OFFSET (SCU_TL0_OFFSET + SCU_LL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define SCU_LL1_OFFSET (SCU_TL1_OFFSET + SCU_LL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SCU_LL2_OFFSET (SCU_TL2_OFFSET + SCU_LL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SCU_LL3_OFFSET (SCU_TL3_OFFSET + SCU_LL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Transport Layer Offsets (PEG + TL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define SCU_TLCR_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define SCU_TLADTR_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define SCU_TLTTMR_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define SCU_TLEECR0_OFFSET 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define SCU_STPTLDARNI_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define SCU_TLCR_RESERVED_MASK (0xFFFFFFEB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define SCU_TLCR_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SCU_GEN_BIT(SCU_TLCR_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * struct scu_transport_layer_registers - These are the SCU Transport Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct scu_transport_layer_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* 0x0000 TLCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* 0x0004 TLADTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u32 arbitration_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* 0x0008 TLTTMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u32 timer_test_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* 0x000C reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 reserved_0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* 0x0010 STPTLDARNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 stp_rni;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* 0x0014 TLFEWPORCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u32 tlfe_wpo_read_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* 0x0018 TLFEWPORDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) u32 tlfe_wpo_read_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* 0x001C RXTLSSCSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u32 rxtl_single_step_control_status_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* 0x0020 RXTLSSCSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u32 rxtl_single_step_control_status_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* 0x0024 AWTRDDCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 tlfe_awt_retry_delay_debug_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Remainder of TL memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u32 reserved_0028_007F[0x16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Protocol Engine Group Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define SCU_SCUVZECRx_OFFSET 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Link Layer Offsets (PEG + TL + LL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SCU_SAS_SPDTOV_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SCU_SAS_LLSTA_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define SCU_SATA_PSELTOV_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SCU_SAS_TIMETOV_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SCU_SAS_LOSTOT_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SCU_SAS_LNKTOV_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SCU_SAS_PHYTOV_OFFSET 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define SCU_SAS_AFERCNT_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define SCU_SAS_WERCNT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SCU_SAS_TIID_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SCU_SAS_TIDNH_OFFSET 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define SCU_SAS_TIDNL_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SCU_SAS_TISSAH_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define SCU_SAS_TISSAL_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define SCU_SAS_TIPID_OFFSET 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define SCU_SAS_TIRES2_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define SCU_SAS_ADRSTA_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SCU_SAS_MAWTTOV_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define SCU_SAS_FRPLDFIL_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SCU_SAS_RFCNT_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define SCU_SAS_TFCNT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define SCU_SAS_RFDCNT_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define SCU_SAS_TFDCNT_OFFSET 0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define SCU_SAS_LERCNT_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define SCU_SAS_RDISERRCNT_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define SCU_SAS_CRERCNT_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define SCU_STPCTL_OFFSET 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SCU_SAS_PCFG_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SCU_SAS_CLKSM_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SCU_SAS_TXCOMWAKE_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define SCU_SAS_TXCOMINIT_OFFSET 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SCU_SAS_TXCOMSAS_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define SCU_SAS_COMINIT_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define SCU_SAS_COMWAKE_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SCU_SAS_COMSAS_OFFSET 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SCU_SAS_SFERCNT_OFFSET 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SCU_SAS_CDFERCNT_OFFSET 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SCU_SAS_DNFERCNT_OFFSET 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define SCU_SAS_PRSTERCNT_OFFSET 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define SCU_SAS_CNTCTL_OFFSET 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define SCU_SAS_SSPTOV_OFFSET 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define SCU_FTCTL_OFFSET 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define SCU_FRCTL_OFFSET 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define SCU_FTWMRK_OFFSET 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define SCU_ENSPINUP_OFFSET 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define SCU_SAS_TRNTOV_OFFSET 0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define SCU_SAS_PHYCAP_OFFSET 0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define SCU_SAS_PHYCTL_OFFSET 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define SCU_SAS_LLCTL_OFFSET 0x00D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define SCU_AFE_XCVRCR_OFFSET 0x00DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define SCU_AFE_LUTCR_OFFSET 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT (8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT (16UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT (24UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define SCU_SAS_PHYTOV_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define SCU_SAS_LLCTL_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define SCU_SAS_LLCTL_GEN_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED (0x1FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK (0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define SCU_SAS_LLTXCOMSAS_GEN_VAL(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_TXCOMSAS_ ## name, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* #define SCU_FRXHECR_DCNT_OFFSET 0x00B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define SCU_PSZGCR_OFFSET 0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define SCU_SAS_RECPHYCAP_OFFSET 0x00E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* #define SCU_TX_LUTSEL_OFFSET 0x00B8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define SCU_SAS_PTxC_OFFSET 0x00D4 /* Same offset as SAS_TCTSTM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * struct scu_link_layer_registers - SCU Link Layer Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct scu_link_layer_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* 0x0000 SAS_SPDTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 speed_negotiation_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* 0x0004 SAS_LLSTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) u32 link_layer_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* 0x0008 SATA_PSELTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 port_selector_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) u32 reserved0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* 0x0010 SAS_TIMETOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 timeout_unit_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* 0x0014 SAS_RCDTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u32 rcd_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* 0x0018 SAS_LNKTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 link_timer_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* 0x001C SAS_PHYTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) u32 sas_phy_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* 0x0020 SAS_AFERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u32 received_address_frame_error_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* 0x0024 SAS_WERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u32 invalid_dword_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* 0x0028 SAS_TIID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u32 transmit_identification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* 0x002C SAS_TIDNH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u32 sas_device_name_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* 0x0030 SAS_TIDNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) u32 sas_device_name_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* 0x0034 SAS_TISSAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 source_sas_address_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* 0x0038 SAS_TISSAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u32 source_sas_address_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* 0x003C SAS_TIPID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 identify_frame_phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* 0x0040 SAS_TIRES2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) u32 identify_frame_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* 0x0044 SAS_ADRSTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u32 received_address_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* 0x0048 SAS_MAWTTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) u32 maximum_arbitration_wait_timer_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* 0x004C SAS_PTxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) u32 transmit_primitive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* 0x0050 SAS_RORES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u32 error_counter_event_notification_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* 0x0054 SAS_FRPLDFIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 frxq_payload_fill_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* 0x0058 SAS_LLHANG_TOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u32 link_layer_hang_detection_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 reserved_5C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* 0x0060 SAS_RFCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 received_frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* 0x0064 SAS_TFCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u32 transmit_frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* 0x0068 SAS_RFDCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u32 received_dword_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* 0x006C SAS_TFDCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u32 transmit_dword_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* 0x0070 SAS_LERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) u32 loss_of_sync_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* 0x0074 SAS_RDISERRCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u32 running_disparity_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* 0x0078 SAS_CRERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u32 received_frame_crc_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* 0x007C STPCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u32 stp_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* 0x0080 SAS_PCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) u32 phy_configuration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* 0x0084 SAS_CLKSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u32 clock_skew_management;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* 0x0088 SAS_TXCOMWAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) u32 transmit_comwake_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* 0x008C SAS_TXCOMINIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) u32 transmit_cominit_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* 0x0090 SAS_TXCOMSAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) u32 transmit_comsas_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* 0x0094 SAS_COMINIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u32 cominit_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* 0x0098 SAS_COMWAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 comwake_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* 0x009C SAS_COMSAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) u32 comsas_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* 0x00A0 SAS_SFERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) u32 received_short_frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* 0x00A4 SAS_CDFERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) u32 received_frame_without_credit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* 0x00A8 SAS_DNFERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u32 received_frame_after_done_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* 0x00AC SAS_PRSTERCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u32 phy_reset_problem_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* 0x00B0 SAS_CNTCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 counter_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* 0x00B4 SAS_SSPTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u32 ssp_timer_timeout_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* 0x00B8 FTCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 ftx_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* 0x00BC FRCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) u32 frx_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* 0x00C0 FTWMRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) u32 ftx_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* 0x00C4 ENSPINUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) u32 notify_enable_spinup_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* 0x00C8 SAS_TRNTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 sas_training_sequence_timer_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* 0x00CC SAS_PHYCAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u32 phy_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* 0x00D0 SAS_PHYCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u32 phy_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) u32 reserved_d4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* 0x00D8 LLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u32 link_layer_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* 0x00DC AFE_XCVRCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) u32 afe_xcvr_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* 0x00E0 AFE_LUTCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) u32 afe_lookup_table_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* 0x00E4 PSZGCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 phy_source_zone_group_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* 0x00E8 SAS_RECPHYCAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) u32 receive_phycap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u32 reserved_ec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* 0x00F0 SNAFERXRSTCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u32 speed_negotiation_afe_rx_reset_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* 0x00F4 SAS_SSIPMCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) u32 power_management_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* 0x00F8 SAS_PSPREQ_PRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u32 sas_pm_partial_request_primitive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* 0x00FC SAS_PSSREQ_PRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u32 sas_pm_slumber_request_primitive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* 0x0100 SAS_PPSACK_PRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u32 sas_pm_ack_primitive_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* 0x0104 SAS_PSNAK_PRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 sas_pm_nak_primitive_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* 0x0108 SAS_SSIPMTOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u32 sas_primitive_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u32 reserved_10c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* 0x0110 - 0x011C PLAPRDCTRLxREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) u32 pla_product_control[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* 0x0120 PLAPRDSUMREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) u32 pla_product_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* 0x0124 PLACONTROLREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) u32 pla_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Remainder of memory space 896 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) u32 reserved_0128_037f[0x96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * u32 primitive_transmit_control; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * SGPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * ---------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define SCU_SGPIO_OFFSET 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* #define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define SCU_SGPIO_SGICR_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define SCU_SGPIO_SGPBR_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define SCU_SGPIO_SGSDLR_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define SCU_SGPIO_SGSDUR_OFFSET 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define SCU_SGPIO_SGVSCR_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* Address from 0x0820 to 0x083C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define SCU_SGPIO_SGODSR_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * struct scu_sgpio_registers - SCU SGPIO Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct scu_sgpio_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* 0x0000 SGPIO_SGICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u32 interface_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* 0x0004 SGPIO_SGPBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) u32 blink_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* 0x0008 SGPIO_SGSDLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) u32 start_drive_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* 0x000C SGPIO_SGSDUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u32 start_drive_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* 0x0010 SGPIO_SGSIDLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 serial_input_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* 0x0014 SGPIO_SGSIDUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u32 serial_input_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* 0x0018 SGPIO_SGVSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u32 vendor_specific_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* 0x001C Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 reserved_001c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* 0x0020 SGPIO_SGODSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u32 output_data_select[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Remainder of memory space 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u32 reserved_1444_14ff[0x30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * * Defines for VIIT entry offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * * Access additional entries by SCU_VIIT_BASE + index * 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define SCU_VIIT_BASE 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct scu_viit_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u32 registers[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * * SCU PORT TASK SCHEDULER REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define SCU_PTSG_BASE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define SCU_PTSG_PTSGCR_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define SCU_PTSG_RTCR_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define SCU_PTSG_RTCCR_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define SCU_PTSG_PTS0CR_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define SCU_PTSG_PTS0SR_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define SCU_PTSG_PTS1CR_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define SCU_PTSG_PTS1SR_OFFSET 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define SCU_PTSG_PTS2CR_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define SCU_PTSG_PTS2SR_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define SCU_PTSG_PTS3CR_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define SCU_PTSG_PTS3SR_OFFSET 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define SCU_PTSG_PCSPE0CR_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define SCU_PTSG_PCSPE1CR_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define SCU_PTSG_PCSPE2CR_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define SCU_PTSG_PCSPE3CR_OFFSET 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define SCU_PTSG_ETMTSCCR_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * struct scu_port_task_scheduler_registers - These are the control/stats pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * for each Port Task Scheduler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) struct scu_port_task_scheduler_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * struct scu_port_task_scheduler_group_registers - These are the PORT Task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * Scheduler registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct scu_port_task_scheduler_group_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* 0x0000 PTSGCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* 0x0004 RTCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) u32 real_time_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* 0x0008 RTCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) u32 real_time_clock_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* 0x000C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) u32 reserved_0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * 0x0010 PTS0CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * 0x0014 PTS0SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * 0x0018 PTS1CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * 0x001C PTS1SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * 0x0020 PTS2CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * 0x0024 PTS2SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * 0x0028 PTS3CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * 0x002C PTS3SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct scu_port_task_scheduler_registers port[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * 0x0030 PCSPE0CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * 0x0034 PCSPE1CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * 0x0038 PCSPE2CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * 0x003C PCSPE3CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u32 protocol_engine[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* 0x0040 ETMTSCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u32 tc_scanning_interval_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* 0x0044 ETMRNSCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) u32 rnc_scanning_interval_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* Remainder of memory space 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) u32 reserved_1048_107f[0x0E];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define SCU_PTSG_SCUVZECR_OFFSET 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * * AFE REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * ***************************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define SCU_AFE_MMR_BASE 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * AFE 0 is at offset 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * AFE 1 is at offset 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * AFE 2 is at offset 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * AFE 3 is at offset 0x0b00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct scu_afe_transceiver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* 0x0000 AFE_XCVR_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) u32 afe_xcvr_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* 0x0004 AFE_XCVR_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) u32 afe_xcvr_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) u32 reserved_0008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* 0x000c afe_dfx_rx_control0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) u32 afe_dfx_rx_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* 0x0010 AFE_DFX_RX_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u32 afe_dfx_rx_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /* 0x0014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 reserved_0014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* 0x0018 AFE_DFX_RX_STS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u32 afe_dfx_rx_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* 0x001c AFE_DFX_RX_STS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) u32 afe_dfx_rx_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) u32 reserved_0020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* 0x0024 AFE_TX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) u32 afe_tx_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* 0x0028 AFE_TX_AMP_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) u32 afe_tx_amp_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* 0x002c AFE_TX_AMP_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) u32 afe_tx_amp_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* 0x0030 AFE_TX_AMP_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) u32 afe_tx_amp_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* 0x0034 AFE_TX_AMP_CTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) u32 afe_tx_amp_control3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* 0x0038 afe_tx_ssc_control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) u32 afe_tx_ssc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* 0x003c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u32 reserved_003c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* 0x0040 AFE_RX_SSC_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) u32 afe_rx_ssc_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* 0x0044 AFE_RX_SSC_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u32 afe_rx_ssc_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* 0x0048 AFE_RX_SSC_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) u32 afe_rx_ssc_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* 0x004c AFE_RX_EQ_STS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) u32 afe_rx_eq_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* 0x0050 AFE_RX_EQ_STS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) u32 afe_rx_eq_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* 0x0054 AFE_RX_CDR_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) u32 afe_rx_cdr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* 0x0058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) u32 reserved_0058;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* 0x005c AFE_CHAN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) u32 afe_channel_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* 0x0060-0x006c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 reserved_0060_006c[0x04];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* 0x0070 AFE_XCVR_EC_STS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) u32 afe_xcvr_error_capture_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* 0x0074 AFE_XCVR_EC_STS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u32 afe_xcvr_error_capture_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* 0x0078 AFE_XCVR_EC_STS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) u32 afe_xcvr_error_capture_status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* 0x007c afe_xcvr_ec_status3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) u32 afe_xcvr_error_capture_status3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* 0x0080 AFE_XCVR_EC_STS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u32 afe_xcvr_error_capture_status4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* 0x0084 AFE_XCVR_EC_STS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u32 afe_xcvr_error_capture_status5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* 0x0088-0x00fc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u32 reserved_008c_00fc[0x1e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * struct scu_afe_registers - AFE Regsiters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* Uaoa AFE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct scu_afe_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* 0Xe000 AFE_BIAS_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) u32 afe_bias_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) u32 reserved_0004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* 0x0008 AFE_PLL_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) u32 afe_pll_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* 0x000c AFE_PLL_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 afe_pll_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* 0x0010 AFE_PLL_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) u32 afe_pll_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* 0x0014 AFE_CB_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) u32 afe_common_block_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* 0x0018-0x007c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) u32 reserved_18_7c[0x1a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* 0x0080 AFE_PMSN_MCTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) u32 afe_pmsn_master_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* 0x0084 AFE_PMSN_MCTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) u32 afe_pmsn_master_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* 0x0088 AFE_PMSN_MCTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) u32 afe_pmsn_master_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* 0x008C-0x00fc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) u32 reserved_008c_00fc[0x1D];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* 0x0100 AFE_DFX_MST_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u32 afe_dfx_master_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* 0x0104 AFE_DFX_MST_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 afe_dfx_master_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* 0x0108 AFE_DFX_DCL_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 afe_dfx_dcl_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* 0x010c AFE_DFX_DMON_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 afe_dfx_digital_monitor_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* 0x0110 AFE_DFX_AMONP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) u32 afe_dfx_analog_p_monitor_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /* 0x0114 AFE_DFX_AMONN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) u32 afe_dfx_analog_n_monitor_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* 0x0118 AFE_DFX_NTL_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) u32 afe_dfx_ntl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* 0x011c AFE_DFX_FIFO_STS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u32 afe_dfx_fifo_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* 0x0120 AFE_DFX_FIFO_STS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 afe_dfx_fifo_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* 0x0124 AFE_DFX_MPAT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) u32 afe_dfx_master_pattern_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* 0x0128 AFE_DFX_P0_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u32 afe_dfx_p0_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* 0x012c-0x01a8 AFE_DFX_P0_DRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u32 afe_dfx_p0_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* 0x01ac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u32 reserved_01ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* 0x01b0-0x020c AFE_DFX_P0_IRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u32 afe_dfx_p0_instruction[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* 0x0210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u32 reserved_0210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* 0x0214 AFE_DFX_P1_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u32 afe_dfx_p1_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* 0x0218-0x245 AFE_DFX_P1_DRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) u32 afe_dfx_p1_data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* 0x0258-0x029c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) u32 reserved_0258_029c[0x12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* 0x02a0-0x02bc AFE_DFX_P1_IRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 afe_dfx_p1_instruction[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* 0x02c0-0x2fc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u32 reserved_02c0_02fc[0x10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* 0x0300 AFE_DFX_TX_PMSN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) u32 afe_dfx_tx_pmsn_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* 0x0304 AFE_DFX_RX_PMSN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u32 afe_dfx_rx_pmsn_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 reserved_0308;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* 0x030c AFE_DFX_NOA_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u32 afe_dfx_noa_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* 0x0310 AFE_DFX_NOA_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) u32 afe_dfx_noa_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* 0x0314 AFE_DFX_NOA_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u32 afe_dfx_noa_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* 0x0318 AFE_DFX_NOA_CTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u32 afe_dfx_noa_control3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* 0x031c AFE_DFX_NOA_CTRL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u32 afe_dfx_noa_control4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* 0x0320 AFE_DFX_NOA_CTRL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) u32 afe_dfx_noa_control5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* 0x0324 AFE_DFX_NOA_CTRL6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u32 afe_dfx_noa_control6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* 0x0328 AFE_DFX_NOA_CTRL7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u32 afe_dfx_noa_control7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* 0x032c-0x07fc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) u32 reserved_032c_07fc[0x135];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* 0x0800-0x0bfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct scu_afe_transceiver scu_afe_xcvr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* 0x0c00-0x0ffc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u32 reserved_0c00_0ffc[0x0100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct scu_protocol_engine_group_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) u32 table[0xE0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct scu_viit_iit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) u32 table[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * Placeholder for the ZONE Partition Table information ZONING will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * included in the 1.1 release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct scu_zone_partition_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) u32 table[2048];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * Placeholder for the CRAM register since I am not sure if we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * read/write to these registers as yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct scu_completion_ram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u32 ram[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * Placeholder for the FBRAM registers since I am not sure if we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * read/write to these registers as yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct scu_frame_buffer_ram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u32 ram[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define scu_scratch_ram_SIZE_IN_DWORDS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * Placeholder for the scratch RAM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct scu_scratch_ram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) u32 ram[scu_scratch_ram_SIZE_IN_DWORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * Placeholder since I am not yet sure what these registers are here for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) struct noa_protocol_engine_partition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u32 reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * Placeholder since I am not yet sure what these registers are here for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct noa_hub_partition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * Placeholder since I am not yet sure what these registers are here for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct noa_host_interface_partition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) u32 reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * struct transport_link_layer_pair - The SCU Hardware pairs up the TL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * registers with the LL registers so we must place them adjcent to make the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * array of registers in the PEG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct transport_link_layer_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct scu_transport_layer_registers tl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct scu_link_layer_registers ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * struct scu_peg_registers - SCU Protocol Engine Memory mapped register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * These registers are unique to each protocol engine group. There can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * at most two PEG for a single SCU part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct scu_peg_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct transport_link_layer_pair pe[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct scu_port_task_scheduler_group_registers ptsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct scu_protocol_engine_group_registers peg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct scu_sgpio_registers sgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 reserved_01500_1BFF[0x1C0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct scu_viit_entry viit[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct scu_zone_partition_table zpt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct scu_zone_partition_table zpt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * struct scu_registers - SCU registers including both PEG registers if we turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * on that compile option. All of these registers are in the memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * space returned from BAR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct scu_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* 0x0000 - PEG 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct scu_peg_registers peg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* 0x6000 - SDMA and Miscellaneous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) struct scu_sdma_registers sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct scu_completion_ram cram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct scu_frame_buffer_ram fbram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u32 reserved_6800_69FF[0x80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct noa_protocol_engine_partition noa_pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct noa_hub_partition noa_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) struct noa_host_interface_partition noa_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) u32 reserved_6d00_7fff[0x4c0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* 0x8000 - PEG 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct scu_peg_registers peg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* 0xE000 - AFE Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct scu_afe_registers afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* 0xF000 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u32 reserved_f000_211fff[0x80c00];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* 0x212000 - scratch RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) struct scu_scratch_ram scratch_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #endif /* _SCU_REGISTERS_HEADER_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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