Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * The full GNU General Public License is included in this distribution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * in the file called LICENSE.GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *   * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *     notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *   * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *     notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *     the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *     distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *   * Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *     contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *     from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #ifndef _ISCI_PROBE_ROMS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define _ISCI_PROBE_ROMS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #include <linux/efi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #include "isci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCIC_SDS_PARM_NO_SPEED   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* generation 1 (i.e. 1.5 Gb/s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCIC_SDS_PARM_GEN1_SPEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* generation 2 (i.e. 3.0 Gb/s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCIC_SDS_PARM_GEN2_SPEED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* generation 3 (i.e. 6.0 Gb/s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCIC_SDS_PARM_GEN3_SPEED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* parameters that can be set by module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct sci_user_parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct sci_phy_user_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		 * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		 * insertion frequency for this phy index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		u32 notify_enable_spin_up_insertion_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		 * This method specifies the number of transmitted DWORDs within which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 * to transmit a single ALIGN primitive.  This value applies regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		 * of what type of device is attached or connection state.  A value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		 * 0 indicates that no ALIGN primitives will be inserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		u16 align_insertion_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * This method specifies the number of transmitted DWORDs within which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * to transmit 2 ALIGN primitives.  This applies for SAS connections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * only.  A minimum value of 3 is required for this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		u16 in_connection_align_insertion_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 * This field indicates the maximum speed generation to be utilized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 * by phys in the supplied port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		u8 max_speed_generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	} phys[SCI_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * This field specifies the maximum number of direct attached devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * that can have power supplied to them simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u8 max_concurr_spinup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * This field specifies the number of seconds to allow a phy to consume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * power before yielding to another phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8 phy_spin_up_delay_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * These timer values specifies how long a link will remain open with no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * activity in increments of a microsecond, it can be in increments of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * 100 microseconds if the upper most bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u16 stp_inactivity_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u16 ssp_inactivity_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * These timer values specifies how long a link will remain open in increments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * of 100 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u16 stp_max_occupancy_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u16 ssp_max_occupancy_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * This timer value specifies how long a link will remain open with no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * outbound traffic in increments of a microsecond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u8 no_outbound_task_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct sci_oem_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct isci_orom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct isci_oem_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u8 sig[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u8 rev_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u8 rev_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SCI_MAX_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SCI_MAX_PHYS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SCI_MAX_CONTROLLERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ISCI_FW_NAME		"isci/isci_firmware.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ROMSIGNATURE		0xaa55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ISCI_OEM_SIG		"$OEM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ISCI_OEM_SIG_SIZE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ISCI_ROM_SIG		"ISCUOEMB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ISCI_ROM_SIG_SIZE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ISCI_EFI_VENDOR_GUID	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			0x1a, 0x04, 0xc6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ISCI_EFI_VAR_NAME	"RstScuO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ISCI_ROM_VER_1_0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ISCI_ROM_VER_1_1	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ISCI_ROM_VER_1_3	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ISCI_ROM_VER_LATEST	ISCI_ROM_VER_1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * defined by the OEM configuration parameters providing no PHY_MASK parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * for any PORT. i.e. There are no phys assigned to any of the ports at start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * MPC Manual PORT configuration mode is defined by the OEM configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * parameters providing a PHY_MASK value for any PORT.  It is assumed that any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * being assigned is sufficient to declare manual PORT configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum sci_port_configuration_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sci_bios_oem_param_block_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	uint8_t signature[ISCI_ROM_SIG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	uint16_t total_block_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	uint8_t hdr_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	uint8_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	uint8_t preboot_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	uint8_t num_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	uint16_t element_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	uint8_t reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct sci_oem_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		uint8_t mode_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		uint8_t max_concurr_spin_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		 * This bitfield indicates the OEM's desired default Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			 * NOTE: Max spread for SATA is +0 / -5000 PPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			 * Down-spreading SSC (only method allowed for SATA):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			 *  SATA SSC Tx Disabled                    = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			 *  SATA SSC Tx at +0 / -1419 PPM Spread    = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			 *  SATA SSC Tx at +0 / -2129 PPM Spread    = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			 *  SATA SSC Tx at +0 / -4257 PPM Spread    = 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			 *  SATA SSC Tx at +0 / -4967 PPM Spread    = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				uint8_t ssc_sata_tx_spread_level:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			 * SAS SSC Tx Disabled                     = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			 * NOTE: Max spread for SAS down-spreading +0 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			 *	 -2300 PPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			 * Down-spreading SSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			 *  SAS SSC Tx at +0 / -1419 PPM Spread     = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			 *  SAS SSC Tx at +0 / -2129 PPM Spread     = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			 * NOTE: Max spread for SAS center-spreading +2300 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 *	 -2300 PPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			 * Center-spreading SSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			 *  SAS SSC Tx at +1064 / -1064 PPM Spread  = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			 *  SAS SSC Tx at +2129 / -2129 PPM Spread  = 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				uint8_t ssc_sas_tx_spread_level:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			 * NOTE: Refer to the SSC section of the SAS 2.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			 * Specification for proper setting of this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			 * For standard SAS Initiator SAS PHY operation it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			 * should be 0 for Down-spreading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			 * SAS SSC Tx spread type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 *  Down-spreading SSC      = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			 *  Center-spreading SSC    = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				uint8_t ssc_sas_tx_type:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			uint8_t do_enable_ssc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		 * This field indicates length of the SAS/SATA cable between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		 * host and device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		 * This field is used make relationship between analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		 * parameters of the phy in the silicon and length of the cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		 * Supported cable attenuation levels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		 * 6m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		 * This is bit mask field:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		 * BIT:      (MSB) 7     6     5     4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		 * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Medium cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		 *                                           length assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		 * BIT:            3     2     1     0  (LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Long cable length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		 *                                           assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		 * BITS 7-4 are set when the cable length is assigned to medium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		 * BITS 3-0 are set when the cable length is assigned to long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		 * The BIT positions are clear when the cable length is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		 * assigned to short.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		 * Setting the bits for both long and medium cable length is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		 * undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		 * A value of 0x84 would assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		 *    phy3 - medium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		 *    phy2 - long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		 *    phy1 - short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		 *    phy0 - short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		uint8_t cable_selection_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	} controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		uint8_t phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	} ports[SCI_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct sci_phy_oem_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			uint32_t high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			uint32_t low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		} sas_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		uint32_t afe_tx_amp_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		uint32_t afe_tx_amp_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		uint32_t afe_tx_amp_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		uint32_t afe_tx_amp_control3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	} phys[SCI_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct isci_orom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	struct sci_bios_oem_param_block_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif