^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The full GNU General Public License is included in this distribution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * in the file called LICENSE.GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * * Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <scsi/sas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "host.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "isci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "port.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "probe_roms.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "remote_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "request.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include "scu_completion_codes.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "scu_event_codes.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include "registers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "scu_remote_node_context.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "scu_task_context.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define smu_max_ports(dcc_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define smu_max_task_contexts(dcc_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define smu_max_rncs(dcc_value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * The number of milliseconds to wait while a given phy is consuming power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * before allowing another set of phys to consume power. Ultimately, this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * be specified by OEM parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * NORMALIZE_PUT_POINTER() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * This macro will normalize the completion queue put pointer so its value can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * be used as an array inde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NORMALIZE_PUT_POINTER(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * NORMALIZE_EVENT_POINTER() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * This macro will normalize the completion queue event entry so its value can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * be used as an index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NORMALIZE_EVENT_POINTER(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * NORMALIZE_GET_POINTER() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * This macro will normalize the completion queue get pointer so its value can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * be used as an index into an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NORMALIZE_GET_POINTER(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * NORMALIZE_GET_POINTER_CYCLE_BIT() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * This macro will normalize the completion queue cycle pointer so it matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * the completion queue cycle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * COMPLETION_QUEUE_CYCLE_BIT() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * This macro will return the cycle bit of the completion queue entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Init the state machine and call the state entry function (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void sci_init_sm(struct sci_base_state_machine *sm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct sci_base_state *state_table, u32 initial_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sci_state_transition_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sm->initial_state_id = initial_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sm->previous_state_id = initial_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sm->current_state_id = initial_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sm->state_table = state_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) handler = sm->state_table[initial_state].enter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) handler(sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Call the state exit fn, update the current state, call the state entry fn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sci_state_transition_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) handler = sm->state_table[sm->current_state_id].exit_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) handler(sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sm->previous_state_id = sm->current_state_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sm->current_state_id = next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) handler = sm->state_table[sm->current_state_id].enter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) handler(sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 get_value = ihost->completion_queue_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static bool sci_controller_isr(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (sci_controller_completion_queue_has_entries(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* we have a spurious interrupt it could be that we have already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * emptied the completion queue from a previous interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * FIXME: really!?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* There is a race in the hardware that could cause us not to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * notified of an interrupt completion if we do not take this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * step. We will mask then unmask the interrupts so if there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * another interrupt pending the clearing of the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * source we get the next interrupt message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_lock(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(0, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_unlock(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) irqreturn_t isci_msix_isr(int vec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct isci_host *ihost = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (sci_controller_isr(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tasklet_schedule(&ihost->completion_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static bool sci_controller_error_isr(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) interrupt_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) readl(&ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (interrupt_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * There is an error interrupt pending so let it through and handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * in the callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * There is a race in the hardware that could cause us not to be notified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * of an interrupt completion if we do not take this step. We will mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * then unmask the error interrupts so if there was another interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * pending we will be notified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(0xff, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(0, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 index = SCU_GET_COMPLETION_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct isci_request *ireq = ihost->reqs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Make sure that we really want to process this IO request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Yep this is a valid io request pass it along to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * io request handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sci_io_request_tc_completion(ireq, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct isci_request *ireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct isci_remote_device *idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) index = SCU_GET_COMPLETION_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (scu_get_command_request_type(ent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ireq = ihost->reqs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __func__, ent, ireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* @todo For a post TC operation we need to fail the IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) idev = ihost->device_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __func__, ent, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* @todo For a port RNC operation we need to fail the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __func__, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 frame_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct scu_unsolicited_frame_header *frame_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct isci_phy *iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct isci_remote_device *idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum sci_status result = SCI_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) frame_index = SCU_GET_FRAME_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) frame_header = ihost->uf_control.buffers.array[frame_index].header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (SCU_GET_FRAME_ERROR(ent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * / this cause a problem? We expect the phy initialization will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * / fail if there is an error in the frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) sci_controller_release_frame(ihost, frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (frame_header->is_address_frame) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) iphy = &ihost->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) result = sci_phy_frame_handler(iphy, frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) index = SCU_GET_COMPLETION_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * This is a signature fis or a frame from a direct attached SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * device that has not yet been created. In either case forwared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * the frame to the PE and let it take care of the frame data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) iphy = &ihost->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) result = sci_phy_frame_handler(iphy, frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (index < ihost->remote_node_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) idev = ihost->device_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) idev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (idev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) result = sci_remote_device_frame_handler(idev, frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sci_controller_release_frame(ihost, frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (result != SCI_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * / @todo Is there any reason to report some additional error message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * / when we get this failure notifiction? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct isci_remote_device *idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct isci_request *ireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct isci_phy *iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) index = SCU_GET_COMPLETION_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) switch (scu_get_event_type(ent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* / @todo The driver did something wrong and we need to fix the condtion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "%s: SCIC Controller 0x%p received SMU command error "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case SCU_EVENT_TYPE_SMU_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * / @todo This is a hardware failure and its likely that we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * / reset the controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "%s: SCIC Controller 0x%p received fatal controller "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "event 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SCU_EVENT_TYPE_TRANSPORT_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ireq = ihost->reqs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sci_io_request_event_handler(ireq, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) switch (scu_get_event_specifier(ent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ireq = ihost->reqs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ireq != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sci_io_request_event_handler(ireq, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "%s: SCIC Controller 0x%p received "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "event 0x%x for io request object "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "that doesnt exist.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) idev = ihost->device_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (idev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sci_remote_device_event_handler(idev, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "%s: SCIC Controller 0x%p received "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "event 0x%x for remote device object "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "that doesnt exist.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SCU_EVENT_TYPE_BROADCAST_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * direct the broadcast change event to the phy first and then let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * the phy redirect the broadcast change to the port object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case SCU_EVENT_TYPE_ERR_CNT_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * direct error counter event to the phy object since that is where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * we get the event notification. This is a type 4 event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case SCU_EVENT_TYPE_OSSP_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) iphy = &ihost->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sci_phy_event_handler(iphy, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case SCU_EVENT_TYPE_RNC_OPS_MISC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (index < ihost->remote_node_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) idev = ihost->device_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (idev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sci_remote_device_event_handler(idev, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "%s: SCIC Controller 0x%p received event 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "for remote device object 0x%0x that doesnt "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "exist.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "%s: SCIC Controller received unknown event code %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static void sci_controller_process_completions(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 completion_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 get_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 get_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 event_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 event_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "%s: completion queue beginning get:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ihost->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Get the component parts of the completion queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) while (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) completion_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ent = ihost->completion_queue[get_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* increment the get pointer and check for rollover to toggle the cycle bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "%s: completion queue entry:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) switch (SCU_GET_COMPLETION_TYPE(ent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case SCU_COMPLETION_TYPE_TASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) sci_controller_task_completion(ihost, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case SCU_COMPLETION_TYPE_SDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sci_controller_sdma_completion(ihost, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case SCU_COMPLETION_TYPE_UFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sci_controller_unsolicited_frame(ihost, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case SCU_COMPLETION_TYPE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sci_controller_event_completion(ihost, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case SCU_COMPLETION_TYPE_NOTIFY: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sci_controller_event_completion(ihost, ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "%s: SCIC Controller received unknown "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "completion type %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Update the get register if we completed one or more entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (completion_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ihost->completion_queue_get =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SMU_CQGR_GEN_BIT(ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) event_cycle |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) get_cycle |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SMU_CQGR_GEN_VAL(POINTER, get_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(ihost->completion_queue_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &ihost->smu_registers->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "%s: completion queue ending get:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ihost->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void sci_controller_error_handler(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) interrupt_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) readl(&ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sci_controller_completion_queue_has_entries(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sci_controller_process_completions(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sci_change_state(&ihost->sm, SCIC_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* If we dont process any completions I am not sure that we want to do this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * We are in the middle of a hardware fault and should probably be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writel(0, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) irqreturn_t isci_intx_isr(int vec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct isci_host *ihost = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (sci_controller_isr(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tasklet_schedule(&ihost->completion_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else if (sci_controller_error_isr(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) spin_lock(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sci_controller_error_handler(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irqreturn_t isci_error_isr(int vec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct isci_host *ihost = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (sci_controller_error_isr(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sci_controller_error_handler(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * isci_host_start_complete() - This function is called by the core library,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * through the ISCI Module, to indicate controller start status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * @isci_host: This parameter specifies the ISCI host object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @completion_status: This parameter specifies the completion status from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * core library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (completion_status != SCI_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_info(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "controller start timed out, continuing...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clear_bit(IHOST_START_PENDING, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) wake_up(&ihost->eventq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct isci_host *ihost = ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (test_bit(IHOST_START_PENDING, &ihost->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) sas_drain_work(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * sci_controller_get_suggested_start_timeout() - This method returns the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * suggested sci_controller_start() timeout amount. The user is free to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * use any timeout value, but this method provides the suggested minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * start timeout value. The returned value is based upon empirical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * information determined as a result of interoperability testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @controller: the handle to the controller object for which to return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * suggested start timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * This method returns the number of milliseconds for the suggested start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * operation timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Validate the user supplied parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * The suggested minimum timeout value for a controller start operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Signature FIS Timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * + Phy Start Timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * + Number of Phy Spin Up Intervals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * ---------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Number of milliseconds for the controller start operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * NOTE: The number of phy spin up intervals will be equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * to the number of phys divided by the number phys allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * per interval - 1 (once OEM parameters are supported).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Currently we assume only 1 phy per interval. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void sci_controller_enable_interrupts(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) set_bit(IHOST_IRQ_ENABLED, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(0, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) void sci_controller_disable_interrupts(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) clear_bit(IHOST_IRQ_ENABLED, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) readl(&ihost->smu_registers->interrupt_mask); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 port_task_scheduler_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) port_task_scheduler_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) readl(&ihost->scu_registers->peg0.ptsg.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) port_task_scheduler_value |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel(port_task_scheduler_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &ihost->scu_registers->peg0.ptsg.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void sci_controller_assign_task_entries(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 task_assignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Assign all the TCs to function 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * TODO: Do we actually need to read this register to write it back?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) task_assignment =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) readl(&ihost->smu_registers->task_context_assignment[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) writel(task_assignment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) &ihost->smu_registers->task_context_assignment[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 completion_queue_control_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 completion_queue_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 completion_queue_put_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ihost->completion_queue_get = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) completion_queue_control_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writel(completion_queue_control_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) &ihost->smu_registers->completion_queue_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Set the completion queue get pointer and enable the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) completion_queue_get_value = (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) (SMU_CQGR_GEN_VAL(POINTER, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) | (SMU_CQGR_GEN_BIT(ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) writel(completion_queue_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) &ihost->smu_registers->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Set the completion queue put pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) completion_queue_put_value = (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) (SMU_CQPR_GEN_VAL(POINTER, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) writel(completion_queue_put_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &ihost->smu_registers->completion_queue_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Initialize the cycle bit of the completion queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * If get.cycle_bit != completion_queue.cycle_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * its not a valid completion queue entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * so at system start all entries are invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ihost->completion_queue[index] = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 frame_queue_control_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 frame_queue_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 frame_queue_put_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Write the queue size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) frame_queue_control_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) writel(frame_queue_control_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Setup the get pointer for the unsolicited frame queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) frame_queue_get_value = (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SCU_UFQGP_GEN_VAL(POINTER, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(frame_queue_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Setup the put pointer for the unsolicited frame queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) writel(frame_queue_put_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ihost->sm.current_state_id == SCIC_STARTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * We move into the ready state, because some of the phys/ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * may be up and operational.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) sci_change_state(&ihost->sm, SCIC_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) isci_host_start_complete(ihost, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static bool is_phy_starting(struct isci_phy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) enum sci_phy_states state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) state = iphy->sm.current_state_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case SCI_PHY_STARTING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case SCI_PHY_SUB_INITIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case SCI_PHY_SUB_AWAIT_IAF_UF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case SCI_PHY_SUB_AWAIT_SAS_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case SCI_PHY_SUB_AWAIT_SATA_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case SCI_PHY_SUB_AWAIT_OSSP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case SCI_PHY_SUB_FINAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) bool is_controller_start_complete(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct isci_phy *iphy = &ihost->phys[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 state = iphy->sm.current_state_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* in apc mode we need to check every phy, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * mpc mode we only need to check phys that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * been configured into a port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (is_port_config_apc(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* pass */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) else if (!phy_get_non_dummy_port(iphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* The controller start operation is complete iff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * - all links have been given an opportunity to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * - have no indication of a connected device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * - have an indication of a connected device and it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * finished the link training process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * sci_controller_start_next_phy - start phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * @scic: controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * If all the phys have been started, then attempt to transition the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * controller to the READY state and inform the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * (sci_cb_controller_start_complete()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct sci_oem_params *oem = &ihost->oem_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct isci_phy *iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) status = SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ihost->phy_startup_timer_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (is_controller_start_complete(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sci_del_timer(&ihost->phy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ihost->phy_startup_timer_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) iphy = &ihost->phys[ihost->next_phy_to_start];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (phy_get_non_dummy_port(iphy) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ihost->next_phy_to_start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Caution recursion ahead be forwarned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * The PHY was never added to a PORT in MPC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * so start the next phy in sequence This phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * will never go link up and will not draw power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * the OEM parameters either configured the phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * incorrectly for the PORT or it was never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * assigned to a PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return sci_controller_start_next_phy(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) status = sci_phy_start(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (status == SCI_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) sci_mod_timer(&ihost->phy_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ihost->phy_startup_timer_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "%s: Controller stop operation failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "to stop phy %d because of status "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ihost->phys[ihost->next_phy_to_start].phy_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ihost->next_phy_to_start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static void phy_startup_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct sci_timer *tmr = from_timer(tmr, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) spin_lock_irqsave(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (tmr->cancel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ihost->phy_startup_timer_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) status = sci_controller_start_next_phy(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) } while (status != SCI_SUCCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) spin_unlock_irqrestore(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static u16 isci_tci_active(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static enum sci_status sci_controller_start(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) enum sci_status result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Build the TCi free pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ihost->tci_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ihost->tci_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) for (index = 0; index < ihost->task_context_entries; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) isci_tci_free(ihost, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Build the RNi free pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) sci_remote_node_table_initialize(&ihost->available_remote_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ihost->remote_node_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * Before anything else lets make sure we will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * interrupted by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) sci_controller_disable_interrupts(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Enable the port task scheduler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) sci_controller_enable_port_task_scheduler(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Assign all the task entries to ihost physical function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) sci_controller_assign_task_entries(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Now initialize the completion queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) sci_controller_initialize_completion_queue(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Initialize the unsolicited frame queue for use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sci_controller_initialize_unsolicited_frame_queue(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Start all of the ports on this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) for (index = 0; index < ihost->logical_port_entries; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct isci_port *iport = &ihost->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) result = sci_port_start(iport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sci_controller_start_next_phy(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) sci_mod_timer(&ihost->timer, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) sci_change_state(&ihost->sm, SCIC_STARTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) void isci_host_start(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) set_bit(IHOST_START_PENDING, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) sci_controller_start(ihost, tmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) sci_controller_enable_interrupts(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static void isci_host_stop_complete(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) sci_controller_disable_interrupts(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) clear_bit(IHOST_STOP_PENDING, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) wake_up(&ihost->eventq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static void sci_controller_completion_handler(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Empty out the completion queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (sci_controller_completion_queue_has_entries(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) sci_controller_process_completions(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Clear the interrupt and enable all interrupts again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Could we write the value of SMU_ISR_COMPLETION? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) writel(0, &ihost->smu_registers->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void ireq_done(struct isci_host *ihost, struct isci_request *ireq, struct sas_task *task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!test_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) !(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (test_bit(IREQ_COMPLETE_IN_TARGET, &ireq->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* Normal notification (task_done) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "%s: Normal - ireq/task = %p/%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) __func__, ireq, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) task->lldd_task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) task->task_done(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "%s: Error - ireq/task = %p/%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) __func__, ireq, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (sas_protocol_ata(task->task_proto))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) task->lldd_task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) sas_task_abort(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) task->lldd_task = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) wake_up_all(&ihost->eventq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!test_bit(IREQ_NO_AUTO_FREE_TAG, &ireq->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) isci_free_tag(ihost, ireq->io_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * isci_host_completion_routine() - This function is the delayed service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * routine that calls the sci core library's completion handler. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * scheduled as a tasklet from the interrupt service routine when interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * in use, or set as the timeout function in polled mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * @data: This parameter specifies the ISCI host object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) void isci_host_completion_routine(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct isci_host *ihost = (struct isci_host *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u16 active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) sci_controller_completion_handler(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * we subtract SCI_MAX_PORTS to account for the number of dummy TCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * issued for hardware issue workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) active = isci_tci_active(ihost) - SCI_MAX_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * the coalesence timeout doubles at each encoding step, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * update it based on the ilog2 value of the outstanding requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) writel(SMU_ICC_GEN_VAL(NUMBER, active) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) &ihost->smu_registers->interrupt_coalesce_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * sci_controller_stop() - This method will stop an individual controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * object.This method will invoke the associated user callback upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * completion. The completion callback is called when the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * conditions are met: -# the method return status is SCI_SUCCESS. -# the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * controller has been quiesced. This method will ensure that all IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * requests are quiesced, phys are stopped, and all additional operation by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * the hardware is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * @controller: the handle to the controller object to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * @timeout: This parameter specifies the number of milliseconds in which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * stop operation should complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * The controller must be in the STARTED or STOPPED state. Indicate if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * controller is not either in the STARTED or STOPPED states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ihost->sm.current_state_id != SCIC_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) sci_mod_timer(&ihost->timer, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) sci_change_state(&ihost->sm, SCIC_STOPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * sci_controller_reset() - This method will reset the supplied core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * controller regardless of the state of said controller. This operation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * considered destructive. In other words, all current operations are wiped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * out. No IO completions for outstanding devices occur. Outstanding IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * requests are not aborted or completed at the actual remote device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * @controller: the handle to the controller object to reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Indicate if the controller reset method succeeded or failed in some way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * the controller reset operation is unable to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static enum sci_status sci_controller_reset(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) switch (ihost->sm.current_state_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case SCIC_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case SCIC_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case SCIC_STOPPING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) case SCIC_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * The reset operation is not a graceful cleanup, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * perform the state transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) sci_change_state(&ihost->sm, SCIC_RESETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) enum sci_status phy_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) status = SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) for (index = 0; index < SCI_MAX_PHYS; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) phy_status = sci_phy_stop(&ihost->phys[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (phy_status != SCI_SUCCESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) phy_status != SCI_FAILURE_INVALID_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) status = SCI_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "%s: Controller stop operation failed to stop "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) "phy %d because of status %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ihost->phys[index].phy_index, phy_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * isci_host_deinit - shutdown frame reception and dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * @ihost: host to take down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * This is called in either the driver shutdown or the suspend path. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * the shutdown case libsas went through port teardown and normal device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * removal (i.e. physical links stayed up to service scsi_device removal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * commands). In the suspend case we disable the hardware without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * notifying libsas of the link down events since we want libsas to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * remember the domain across the suspend/resume cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) void isci_host_deinit(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* disable output data selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 0; i < isci_gpio_count(ihost); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) set_bit(IHOST_STOP_PENDING, &ihost->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) wait_for_stop(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* phy stop is after controller stop to allow port and device to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * go idle before shutting down the phys, but the expectation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * that i/o has been shut off well before we reach this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) sci_controller_stop_phys(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* disable sgpio: where the above wait should give time for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * enclosure to sample the gpios going inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) sci_controller_reset(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Cancel any/all outstanding port timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) for (i = 0; i < ihost->logical_port_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct isci_port *iport = &ihost->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) del_timer_sync(&iport->timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Cancel any/all outstanding phy timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct isci_phy *iphy = &ihost->phys[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) del_timer_sync(&iphy->sata_timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) del_timer_sync(&ihost->port_agent.timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) del_timer_sync(&ihost->power_control.timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) del_timer_sync(&ihost->timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) del_timer_sync(&ihost->phy_timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static void __iomem *scu_base(struct isci_host *isci_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct pci_dev *pdev = isci_host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) int id = isci_host->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static void __iomem *smu_base(struct isci_host *isci_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct pci_dev *pdev = isci_host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int id = isci_host->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sci_change_state(&ihost->sm, SCIC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sci_del_timer(&ihost->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define INTERRUPT_COALESCE_NUMBER_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * sci_controller_set_interrupt_coalescence() - This method allows the user to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * configure the interrupt coalescence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * @controller: This parameter represents the handle to the controller object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * for which its interrupt coalesce register is overridden.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * @coalesce_number: Used to control the number of entries in the Completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Queue before an interrupt is generated. If the number of entries exceed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * this number, an interrupt will be generated. The valid range of the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * is [0, 256]. A setting of 0 results in coalescing being disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * @coalesce_timeout: Timeout value in microseconds. The valid range of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * input is [0, 2700000] . A setting of 0 is allowed and results in no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * interrupt coalescing timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * Indicate if the user successfully set the interrupt coalesce parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * SCI_SUCCESS The user successfully updated the interrutp coalescence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static enum sci_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 coalesce_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 coalesce_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u8 timeout_encode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u32 min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* Check if the input parameters fall in the range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return SCI_FAILURE_INVALID_PARAMETER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * Defined encoding for interrupt coalescing timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * Value Min Max Units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * ----- --- --- -----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * 0 - - Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * 1 13.3 20.0 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * 2 26.7 40.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * 3 53.3 80.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * 4 106.7 160.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * 5 213.3 320.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * 6 426.7 640.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * 7 853.3 1280.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * 8 1.7 2.6 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * 9 3.4 5.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * 10 6.8 10.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * 11 13.7 20.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * 12 27.3 41.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * 13 54.6 81.9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * 14 109.2 163.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * 15 218.5 327.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * 16 436.9 655.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * 17 873.8 1310.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * 18 1.7 2.6 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * 19 3.5 5.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * 20 7.0 10.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * 21 14.0 21.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * 22 28.0 41.9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * 23 55.9 83.9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * 24 111.8 167.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * 25 223.7 335.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * 26 447.4 671.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * 27 894.8 1342.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * 28 1.8 2.7 s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * Others Undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * Use the table above to decide the encode of interrupt coalescing timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * value for register writing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (coalesce_timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) timeout_encode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* make the timeout value in unit of (10 ns). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) coalesce_timeout = coalesce_timeout * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* get the encode of timeout for register writing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) timeout_encode++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (min <= coalesce_timeout && max > coalesce_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else if (coalesce_timeout >= max && coalesce_timeout < min * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) timeout_encode++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) max = max * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) min = min * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* the value is out of range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return SCI_FAILURE_INVALID_PARAMETER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) SMU_ICC_GEN_VAL(TIMER, timeout_encode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) &ihost->smu_registers->interrupt_coalesce_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ihost->interrupt_coalesce_number = (u16)coalesce_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* enable clock gating for power control of the scu unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) val = readl(&ihost->smu_registers->clock_gating_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) writel(val, &ihost->smu_registers->clock_gating_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* set the default interrupt coalescence number and timeout value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) sci_controller_set_interrupt_coalescence(ihost, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* disable interrupt coalescence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) sci_controller_set_interrupt_coalescence(ihost, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) enum sci_status port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) enum sci_status status = SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) for (index = 0; index < ihost->logical_port_entries; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct isci_port *iport = &ihost->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) port_status = sci_port_stop(iport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if ((port_status != SCI_SUCCESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) (port_status != SCI_FAILURE_INVALID_STATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) status = SCI_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) "%s: Controller stop operation failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) "stop port %d because of status %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) iport->logical_port_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) enum sci_status device_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) status = SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (index = 0; index < ihost->remote_node_entries; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (ihost->device_table[index] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* / @todo What timeout value do we want to provide to this request? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) device_status = sci_remote_device_stop(ihost->device_table[index], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if ((device_status != SCI_SUCCESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) (device_status != SCI_FAILURE_INVALID_STATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) "%s: Controller stop operation failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) "to stop device 0x%p because of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) "status %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ihost->device_table[index], device_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) sci_controller_stop_devices(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) sci_controller_stop_ports(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (!sci_controller_has_remote_devices_stopping(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) isci_host_stop_complete(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) sci_del_timer(&ihost->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void sci_controller_reset_hardware(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Disable interrupts so we dont take any spurious interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) sci_controller_disable_interrupts(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* Reset the SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Delay for 1ms to before clearing the CQP and UFQPR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* The write to the CQGR clears the CQP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) writel(0x00000000, &ihost->smu_registers->completion_queue_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* The write to the UFQGP clears the UFQPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) sci_controller_reset_hardware(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) sci_change_state(&ihost->sm, SCIC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const struct sci_base_state sci_controller_state_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) [SCIC_INITIAL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .enter_state = sci_controller_initial_state_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) [SCIC_RESET] = {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) [SCIC_INITIALIZING] = {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) [SCIC_INITIALIZED] = {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) [SCIC_STARTING] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .exit_state = sci_controller_starting_state_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) [SCIC_READY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .enter_state = sci_controller_ready_state_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .exit_state = sci_controller_ready_state_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) [SCIC_RESETTING] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .enter_state = sci_controller_resetting_state_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) [SCIC_STOPPING] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .enter_state = sci_controller_stopping_state_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .exit_state = sci_controller_stopping_state_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [SCIC_FAILED] = {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static void controller_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct sci_timer *tmr = from_timer(tmr, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct sci_base_state_machine *sm = &ihost->sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) spin_lock_irqsave(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (tmr->cancel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (sm->current_state_id == SCIC_STARTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) else if (sm->current_state_id == SCIC_STOPPING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) sci_change_state(sm, SCIC_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) isci_host_stop_complete(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) } else /* / @todo Now what do we want to do in this case? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_err(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) "%s: Controller timer fired when controller was not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) "in a state being timed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) spin_unlock_irqrestore(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static enum sci_status sci_controller_construct(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) void __iomem *scu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) void __iomem *smu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ihost->scu_registers = scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ihost->smu_registers = smu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) sci_port_configuration_agent_construct(&ihost->port_agent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* Construct the ports for this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) for (i = 0; i < SCI_MAX_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) sci_port_construct(&ihost->ports[i], i, ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Construct the phys for this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Add all the PHYs to the dummy port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) sci_phy_construct(&ihost->phys[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &ihost->ports[SCI_MAX_PORTS], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ihost->invalid_phy_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) sci_init_timer(&ihost->timer, controller_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return sci_controller_reset(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) for (i = 0; i < SCI_MAX_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) for (i = 0; i < SCI_MAX_PHYS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (oem->phys[i].sas_address.high == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) oem->phys[i].sas_address.low == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) for (i = 0; i < SCI_MAX_PHYS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (oem->ports[i].phy_mask != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u8 phy_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) for (i = 0; i < SCI_MAX_PHYS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) phy_mask |= oem->ports[i].phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (phy_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) oem->controller.max_concurr_spin_up < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (oem->controller.do_enable_ssc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (version >= ISCI_ROM_VER_1_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u8 test = oem->controller.ssc_sata_tx_spread_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) switch (test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) test = oem->controller.ssc_sas_tx_spread_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (oem->controller.ssc_sas_tx_type == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) switch (test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else if (oem->controller.ssc_sas_tx_type == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) switch (test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static u8 max_spin_up(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (ihost->user_parameters.max_concurr_spinup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return min_t(u8, ihost->user_parameters.max_concurr_spinup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static void power_control_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct sci_timer *tmr = from_timer(tmr, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct isci_phy *iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) spin_lock_irqsave(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (tmr->cancel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ihost->power_control.phys_granted_power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ihost->power_control.phys_waiting == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ihost->power_control.timer_started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (ihost->power_control.phys_waiting == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) iphy = ihost->power_control.requesters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (iphy == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) ihost->power_control.requesters[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ihost->power_control.phys_waiting--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ihost->power_control.phys_granted_power++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) sci_phy_consume_power_handler(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (iphy->protocol == SAS_PROTOCOL_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u8 j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) for (j = 0; j < SCI_MAX_PHYS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct isci_phy *requester = ihost->power_control.requesters[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * Search the power_control queue to see if there are other phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * attached to the same remote device. If found, take all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * them out of await_sas_power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (requester != NULL && requester != iphy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) iphy->frame_rcvd.iaf.sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) sizeof(requester->frame_rcvd.iaf.sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (other == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ihost->power_control.requesters[j] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ihost->power_control.phys_waiting--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) sci_phy_consume_power_handler(requester);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * It doesn't matter if the power list is empty, we need to start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * timer in case another phy becomes ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ihost->power_control.timer_started = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) spin_unlock_irqrestore(&ihost->scic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) void sci_controller_power_control_queue_insert(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct isci_phy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) BUG_ON(iphy == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ihost->power_control.phys_granted_power++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) sci_phy_consume_power_handler(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * stop and start the power_control timer. When the timer fires, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * no_of_phys_granted_power will be set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (ihost->power_control.timer_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) sci_del_timer(&ihost->power_control.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) sci_mod_timer(&ihost->power_control.timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ihost->power_control.timer_started = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * There are phys, attached to the same sas address as this phy, are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * already in READY state, this phy don't need wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct isci_phy *current_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) u8 other;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) current_phy = &ihost->phys[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) iphy->frame_rcvd.iaf.sas_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) sizeof(current_phy->frame_rcvd.iaf.sas_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (current_phy->sm.current_state_id == SCI_PHY_READY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) current_phy->protocol == SAS_PROTOCOL_SSP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) other == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) sci_phy_consume_power_handler(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (i == SCI_MAX_PHYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* Add the phy in the waiting list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ihost->power_control.requesters[iphy->phy_index] = iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ihost->power_control.phys_waiting++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) void sci_controller_power_control_queue_remove(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct isci_phy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) BUG_ON(iphy == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (ihost->power_control.requesters[iphy->phy_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ihost->power_control.phys_waiting--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ihost->power_control.requesters[iphy->phy_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static int is_long_cable(int phy, unsigned char selection_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return !!(selection_byte & (1 << phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static int is_medium_cable(int phy, unsigned char selection_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return !!(selection_byte & (1 << (phy + 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static enum cable_selections decode_selection_byte(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) unsigned char selection_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return ((selection_byte & (1 << phy)) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static unsigned char *to_cable_select(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (is_cable_select_overridden())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return ((unsigned char *)&cable_selection_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) + ihost->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return &ihost->oem_parameters.controller.cable_selection_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return decode_selection_byte(phy, *to_cable_select(ihost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) char *lookup_cable_names(enum cable_selections selection)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static char *cable_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) [short_cable] = "short",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) [long_cable] = "long",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) [medium_cable] = "medium",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return (selection <= undefined_cable) ? cable_names[selection]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) : cable_names[undefined_cable];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define AFE_REGISTER_WRITE_DELAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static void sci_controller_afe_initialization(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) const struct sci_oem_params *oem = &ihost->oem_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct pci_dev *pdev = ihost->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) u32 afe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned char cable_selection_mask = *to_cable_select(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* Clear DFX Status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) writel(0x0081000f, &afe->afe_dfx_master_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * Timer, PM Stagger Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* Configure bias currents to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (is_a2(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) writel(0x00005A00, &afe->afe_bias_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) else if (is_b0(pdev) || is_c0(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) writel(0x00005F00, &afe->afe_bias_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) else if (is_c1(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) writel(0x00005500, &afe->afe_bias_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* Enable PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (is_a2(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) writel(0x80040908, &afe->afe_pll_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) else if (is_b0(pdev) || is_c0(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) writel(0x80040A08, &afe->afe_pll_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) else if (is_c1(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) writel(0x80000B08, &afe->afe_pll_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) writel(0x00000B08, &afe->afe_pll_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) writel(0x80000B08, &afe->afe_pll_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* Wait for the PLL to lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) afe_status = readl(&afe->afe_common_block_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) } while ((afe_status & 0x00001000) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (is_a2(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* Shorten SAS SNW lock time (RxLock timer value from 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * us to 50 us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) int cable_length_long =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) is_long_cable(phy_id, cable_selection_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) int cable_length_medium =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) is_medium_cable(phy_id, cable_selection_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (is_a2(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* All defaults, except the Receive Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * Alignament/Comma Detect Enable....(0xe800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) writel(0x00004512, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) writel(0x0050100F, &xcvr->afe_xcvr_control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) } else if (is_b0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* Configure transmitter SSC parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) writel(0x00030000, &xcvr->afe_tx_ssc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) } else if (is_c0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* Configure transmitter SSC parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) writel(0x00010202, &xcvr->afe_tx_ssc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* All defaults, except the Receive Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * Alignament/Comma Detect Enable....(0xe800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) writel(0x00014500, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) } else if (is_c1(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* Configure transmitter SSC parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) writel(0x00010202, &xcvr->afe_tx_ssc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* All defaults, except the Receive Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * Alignament/Comma Detect Enable....(0xe800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) writel(0x0001C500, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* Power up TX and RX out from power down (PWRDNTX and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (is_a2(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) writel(0x000003F0, &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) else if (is_b0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) writel(0x000003D7, &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) writel(0x000003D4, &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) } else if (is_c0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) writel(0x000001E7, &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) writel(0x000001E4, &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) } else if (is_c1(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) writel(cable_length_long ? 0x000002F7 : 0x000001F7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) writel(cable_length_long ? 0x000002F4 : 0x000001F4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) &xcvr->afe_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (is_a2(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* Enable TX equalization (0xe824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) writel(0x00040000, &xcvr->afe_tx_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (is_a2(pdev) || is_b0(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) * TPD=0x0(TX Power On), RDD=0x0(RX Detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) * Enabled) ....(0xe800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) writel(0x00004100, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) else if (is_c0(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) writel(0x00014100, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) else if (is_c1(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) writel(0x0001C100, &xcvr->afe_xcvr_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* Leave DFE/FFE on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (is_a2(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) else if (is_b0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* Enable TX equalization (0xe824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) writel(0x00040000, &xcvr->afe_tx_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) } else if (is_c0(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* Enable TX equalization (0xe824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) writel(0x00040000, &xcvr->afe_tx_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) } else if (is_c1(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) writel(cable_length_long ? 0x01500C0C :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) cable_length_medium ? 0x01400C0D : 0x02400C0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) &xcvr->afe_xcvr_control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) writel(cable_length_long ? 0x33091C1F :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) cable_length_medium ? 0x3315181F : 0x2B17161F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) &xcvr->afe_rx_ssc_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* Enable TX equalization (0xe824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) writel(0x00040000, &xcvr->afe_tx_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /* Transfer control to the PEs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) writel(0x00010f00, &afe->afe_dfx_master_control0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) udelay(AFE_REGISTER_WRITE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static void sci_controller_initialize_power_control(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) sci_init_timer(&ihost->power_control.timer, power_control_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) memset(ihost->power_control.requesters, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) sizeof(ihost->power_control.requesters));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ihost->power_control.phys_waiting = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ihost->power_control.phys_granted_power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static enum sci_status sci_controller_initialize(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct sci_base_state_machine *sm = &ihost->sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) enum sci_status result = SCI_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) unsigned long i, state, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (ihost->sm.current_state_id != SCIC_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) sci_change_state(sm, SCIC_INITIALIZING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ihost->next_phy_to_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ihost->phy_startup_timer_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) sci_controller_initialize_power_control(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) * There is nothing to do here for B0 since we do not have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * program the AFE registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * / @todo The AFE settings are supposed to be correct for the B0 but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * / presently they seem to be wrong. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) sci_controller_afe_initialization(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Take the hardware out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) writel(0, &ihost->smu_registers->soft_reset_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * / @todo Provide meaningfull error code for hardware failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) for (i = 100; i >= 1; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* Loop until the hardware reports success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) status = readl(&ihost->smu_registers->control_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * Determine what are the actaul device capacities that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) * hardware will support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) val = readl(&ihost->smu_registers->device_context_capacity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* Record the smaller of the two capacity values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * Make all PEs that are unassigned match up with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * logical ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) for (i = 0; i < ihost->logical_port_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct scu_port_task_scheduler_group_registers __iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) *ptsg = &ihost->scu_registers->peg0.ptsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) writel(i, &ptsg->protocol_engine[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* Initialize hardware PCI Relaxed ordering in DMA engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) val = readl(&ihost->scu_registers->sdma.pdma_configuration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) writel(val, &ihost->scu_registers->sdma.pdma_configuration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) val = readl(&ihost->scu_registers->sdma.cdma_configuration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) writel(val, &ihost->scu_registers->sdma.cdma_configuration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * Initialize the PHYs before the PORTs because the PHY registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * are accessed during the port initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) for (i = 0; i < SCI_MAX_PHYS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) result = sci_phy_initialize(&ihost->phys[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) &ihost->scu_registers->peg0.pe[i].tl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) &ihost->scu_registers->peg0.pe[i].ll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (result != SCI_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) for (i = 0; i < ihost->logical_port_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) struct isci_port *iport = &ihost->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) /* Advance the controller state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (result == SCI_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) state = SCIC_INITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) state = SCIC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) sci_change_state(sm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static int sci_controller_dma_alloc(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct device *dev = &ihost->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* detect re-initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (ihost->completion_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (!ihost->completion_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (!ihost->remote_node_context_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) size = ihost->task_context_entries * sizeof(struct scu_task_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (!ihost->task_context_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) size = SCI_UFI_TOTAL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (!ihost->ufi_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) struct isci_request *ireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (!ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ireq->tc = &ihost->task_context_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ireq->owning_controller = ihost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ireq->request_daddr = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) ireq->isci_host = ihost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ihost->reqs[i] = ireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static int sci_controller_mem_init(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) int err = sci_controller_dma_alloc(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) sci_unsolicited_frame_control_construct(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) * Inform the silicon as to the location of the UF headers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) * address table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) writel(lower_32_bits(ihost->uf_control.headers.physical_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) &ihost->scu_registers->sdma.uf_header_base_address_lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) writel(upper_32_bits(ihost->uf_control.headers.physical_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) &ihost->scu_registers->sdma.uf_header_base_address_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) &ihost->scu_registers->sdma.uf_address_table_lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) &ihost->scu_registers->sdma.uf_address_table_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * isci_host_init - (re-)initialize hardware and internal (private) state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * @ihost: host to init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * one-time initialization objects like locks and waitqueues, are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) * not touched (they are initialized in isci_host_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) int isci_host_init(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (status != SCI_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) dev_err(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) "%s: sci_controller_construct failed - status = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) spin_lock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) status = sci_controller_initialize(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) spin_unlock_irq(&ihost->scic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if (status != SCI_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) "%s: sci_controller_initialize failed -"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) " status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) err = sci_controller_mem_init(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* enable sgpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) for (i = 0; i < isci_gpio_count(ihost); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct isci_phy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) switch (ihost->sm.current_state_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) case SCIC_STARTING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) sci_del_timer(&ihost->phy_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ihost->phy_startup_timer_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) iport, iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) sci_controller_start_next_phy(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) case SCIC_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) iport, iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) "%s: SCIC Controller linkup event from phy %d in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) "unexpected state %d\n", __func__, iphy->phy_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) struct isci_phy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) switch (ihost->sm.current_state_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) case SCIC_STARTING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) case SCIC_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) iport, iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) "%s: SCIC Controller linkdown event from phy %d in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "unexpected state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) iphy->phy_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) for (index = 0; index < ihost->remote_node_entries; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if ((ihost->device_table[index] != NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) void sci_controller_remote_device_stopped(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct isci_remote_device *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (ihost->sm.current_state_id != SCIC_STOPPING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) dev_dbg(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) "SCIC Controller 0x%p remote device stopped event "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) "from device 0x%p in unexpected state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ihost, idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if (!sci_controller_has_remote_devices_stopping(ihost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) isci_host_stop_complete(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) void sci_controller_post_request(struct isci_host *ihost, u32 request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) __func__, ihost->id, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) writel(request, &ihost->smu_registers->post_context_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) u16 task_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) u16 task_sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) task_index = ISCI_TAG_TCI(io_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (task_index < ihost->task_context_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) struct isci_request *ireq = ihost->reqs[task_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) task_sequence = ISCI_TAG_SEQ(io_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (task_sequence == ihost->io_request_sequence[task_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return ireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * This method allocates remote node index and the reserves the remote node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * context space for use. This method can fail if there are no more remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * node index available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * @scic: This is the controller object which contains the set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) * free remote node ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) * @sci_dev: This is the device object which is requesting the a remote node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) * id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) * @node_id: This is the remote node id that is assinged to the device if one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) * is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) * node index available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) u16 *node_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) u16 node_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) u32 remote_node_count = sci_remote_device_node_count(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) node_index = sci_remote_node_table_allocate_remote_node(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) &ihost->available_remote_nodes, remote_node_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ihost->device_table[node_index] = idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) *node_id = node_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) return SCI_FAILURE_INSUFFICIENT_RESOURCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) void sci_controller_free_remote_node_context(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) u16 node_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) u32 remote_node_count = sci_remote_device_node_count(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) if (ihost->device_table[node_id] == idev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ihost->device_table[node_id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) sci_remote_node_table_release_remote_node_index(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) &ihost->available_remote_nodes, remote_node_count, node_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) void sci_controller_copy_sata_response(void *response_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) void *frame_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) void *frame_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* XXX type safety? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) memcpy(response_buffer, frame_header, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) memcpy(response_buffer + sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) frame_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) sizeof(struct dev_to_host_fis) - sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) writel(ihost->uf_control.get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) void isci_tci_free(struct isci_host *ihost, u16 tci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) ihost->tci_pool[tail] = tci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) ihost->tci_tail = tail + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) static u16 isci_tci_alloc(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) u16 tci = ihost->tci_pool[head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ihost->tci_head = head + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) return tci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static u16 isci_tci_space(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) u16 isci_alloc_tag(struct isci_host *ihost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (isci_tci_space(ihost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) u16 tci = isci_tci_alloc(ihost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) u8 seq = ihost->io_request_sequence[tci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) return ISCI_TAG(seq, tci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) return SCI_CONTROLLER_INVALID_IO_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) u16 tci = ISCI_TAG_TCI(io_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) u16 seq = ISCI_TAG_SEQ(io_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /* prevent tail from passing head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (isci_tci_active(ihost) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) return SCI_FAILURE_INVALID_IO_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) if (seq == ihost->io_request_sequence[tci]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) isci_tci_free(ihost, tci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) return SCI_FAILURE_INVALID_IO_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) enum sci_status sci_controller_start_io(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct isci_request *ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (ihost->sm.current_state_id != SCIC_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) status = sci_remote_device_start_io(ihost, idev, ireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (status != SCI_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) set_bit(IREQ_ACTIVE, &ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) sci_controller_post_request(ihost, ireq->post_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) struct isci_request *ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* terminate an ongoing (i.e. started) core IO request. This does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) * abort the IO request at the target, but rather removes the IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) * request from the host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) if (ihost->sm.current_state_id != SCIC_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) status = sci_io_request_terminate(ireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) dev_dbg(&ihost->pdev->dev, "%s: status=%d; ireq=%p; flags=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) __func__, status, ireq, ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if ((status == SCI_SUCCESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) !test_bit(IREQ_PENDING_ABORT, &ireq->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) !test_and_set_bit(IREQ_TC_ABORT_POSTED, &ireq->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) /* Utilize the original post context command and or in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * POST_TC_ABORT request sub-type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) sci_controller_post_request(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) ihost, ireq->post_context |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) * sci_controller_complete_io() - This method will perform core specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) * completion operations for an IO request. After this method is invoked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) * the user should consider the IO request as invalid until it is properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) * reused (i.e. re-constructed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) * @ihost: The handle to the controller object for which to complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) * IO request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * @idev: The handle to the remote device object for which to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) * the IO request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) * @ireq: the handle to the io request object to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) enum sci_status sci_controller_complete_io(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) struct isci_request *ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) switch (ihost->sm.current_state_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) case SCIC_STOPPING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /* XXX: Implement this function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return SCI_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) case SCIC_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) status = sci_remote_device_complete_io(ihost, idev, ireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (status != SCI_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) clear_bit(IREQ_ACTIVE, &ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) enum sci_status sci_controller_continue_io(struct isci_request *ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) struct isci_host *ihost = ireq->owning_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (ihost->sm.current_state_id != SCIC_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) __func__, ihost->sm.current_state_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) set_bit(IREQ_ACTIVE, &ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) sci_controller_post_request(ihost, ireq->post_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) * sci_controller_start_task() - This method is called by the SCIC user to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) * send/start a framework task management request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) * @controller: the handle to the controller object for which to start the task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) * management request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) * @remote_device: the handle to the remote device object for which to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) * the task management request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) * @task_request: the handle to the task request object to start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) enum sci_status sci_controller_start_task(struct isci_host *ihost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) struct isci_remote_device *idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) struct isci_request *ireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) enum sci_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) if (ihost->sm.current_state_id != SCIC_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) dev_warn(&ihost->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) "%s: SCIC Controller starting task from invalid "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) "state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) return SCI_FAILURE_INVALID_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) status = sci_remote_device_start_task(ihost, idev, ireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) set_bit(IREQ_ACTIVE, &ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * We will let framework know this task request started successfully,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * although core is still woring on starting the request (to post tc when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * RNC is resumed.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) return SCI_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) case SCI_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) set_bit(IREQ_ACTIVE, &ireq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) sci_controller_post_request(ihost, ireq->post_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) int d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /* no support for TX_GP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) if (reg_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) for (d = 0; d < isci_gpio_count(ihost); d++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) u32 val = 0x444; /* all ODx.n clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) write_data, reg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) if (bit < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* if od is set, clear the 'invert' bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) val &= ~(bit << ((i << 2) + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (i < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* unless reg_index is > 1, we should always be able to write at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) * least one register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) return d > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) u8 reg_count, u8 *write_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) struct isci_host *ihost = sas_ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) int written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) switch (reg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) case SAS_GPIO_REG_TX_GP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) written = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) return written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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