^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Written By: Keith Mitchell, IBM Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* Jack Hammer, Adaptec, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* David Jeffery, Adaptec, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Copyright (C) 1999 IBM Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Copyright (C) 2003 Adaptec, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* This program is free software; you can redistribute it and/or modify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* it under the terms of the GNU General Public License as published by */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* the Free Software Foundation; either version 2 of the License, or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* (at your option) any later version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* This program is distributed in the hope that it will be useful, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* GNU General Public License for more details. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* NO WARRANTY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* solely responsible for determining the appropriateness of using and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* distributing the Program and assumes all risks associated with its */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* exercise of rights under this Agreement, including but not limited to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* the risks and costs of program errors, damage to or loss of data, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* programs or equipment, and unavailability or interruption of operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* DISCLAIMER OF LIABILITY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* You should have received a copy of the GNU General Public License */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* along with this program; if not, write to the Free Software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Bugs/Comments/Suggestions should be mailed to: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ipslinux@adaptec.com */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifndef _IPS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define _IPS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/nmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Some handy macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (IPS_IS_TROMBONE(ha) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (ips_force_i2o))) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (ips_force_memio))) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IPS_PRINTK(level, pcidev, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_printk(level , &((pcidev)->dev) , format , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MDELAY(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mdelay(n); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) touch_nmi_watchdog(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifndef min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define min(x,y) ((x) < (y) ? x : y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define __iomem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Adapter address map equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IPS_REG_SQER 0x28 /* Status Q End Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IPS_REG_CBSP 0x07 /* CBSP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IPS_REG_FLAP 0x18 /* Flash address port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IPS_REG_FLDP 0x1C /* Flash data port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Adapter register bit equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Adapter Command ID Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IPS_CMD_GET_LD_INFO 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IPS_CMD_GET_SUBSYS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IPS_CMD_READ_CONF 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IPS_CMD_RW_NVRAM_PAGE 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IPS_CMD_READ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IPS_CMD_WRITE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IPS_CMD_FFDC 0xD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IPS_CMD_ENQUIRY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IPS_CMD_FLUSH 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IPS_CMD_READ_SG 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IPS_CMD_WRITE_SG 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IPS_CMD_DCDB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IPS_CMD_DCDB_SG 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IPS_CMD_EXTENDED_DCDB 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IPS_CMD_EXTENDED_DCDB_SG 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IPS_CMD_CONFIG_SYNC 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IPS_CMD_ERROR_TABLE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IPS_CMD_DOWNLOAD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IPS_CMD_RW_BIOSFW 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IPS_CMD_GET_VERSION_INFO 0xC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IPS_CMD_RESET_CHANNEL 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Adapter Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IPS_CSL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IPS_POCL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IPS_NORM_STATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IPS_MAX_ADAPTER_TYPES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IPS_MAX_ADAPTERS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IPS_MAX_IOCTL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IPS_MAX_IOCTL_QUEUE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IPS_MAX_QUEUE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IPS_BLKSIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IPS_MAX_SG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IPS_MAX_LD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IPS_MAX_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IPS_MAX_TARGETS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IPS_MAX_CHUNKS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IPS_MAX_CMDS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IPS_MAX_XFER 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IPS_NVRAM_P5_SIG 0xFFDDBB99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IPS_MAX_POST_BYTES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IPS_MAX_CONFIG_BYTES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IPS_GOOD_POST_STATUS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IPS_SEM_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IPS_IOCTL_COMMAND 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IPS_INTR_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IPS_INTR_IORL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IPS_FFDC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IPS_ADAPTER_ID 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IPS_VENDORID_IBM 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IPS_VENDORID_ADAPTEC 0x9005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IPS_DEVICEID_COPPERHEAD 0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IPS_DEVICEID_MORPHEUS 0x01BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IPS_DEVICEID_MARCO 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IPS_SUBDEVICEID_4M 0x01BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IPS_SUBDEVICEID_4L 0x01BF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IPS_SUBDEVICEID_4MX 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IPS_SUBDEVICEID_4LX 0x020E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IPS_SUBDEVICEID_5I2 0x0259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IPS_SUBDEVICEID_5I1 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IPS_SUBDEVICEID_6M 0x0279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IPS_SUBDEVICEID_6I 0x028C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IPS_SUBDEVICEID_7k 0x028E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IPS_SUBDEVICEID_7M 0x028F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IPS_IOCTL_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IPS_STATUS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IPS_IMAGE_SIZE 500 * 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IPS_MEMMAP_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IPS_ONE_MSEC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IPS_ONE_SEC 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Geometry Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IPS_COMP_HEADS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IPS_COMP_SECTORS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IPS_NORM_HEADS 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IPS_NORM_SECTORS 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Adapter Basic Status Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IPS_BASIC_STATUS_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IPS_GSC_STATUS_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IPS_CMD_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IPS_CMD_RECOVERED_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IPS_INVAL_OPCO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IPS_INVAL_CMD_BLK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IPS_INVAL_PARM_BLK 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IPS_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IPS_CMD_CMPLT_WERROR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IPS_LD_ERROR 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IPS_CMD_TIMEOUT 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IPS_PHYS_DRV_ERROR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Adapter Extended Status Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IPS_ERR_SEL_TO 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IPS_ERR_OU_RUN 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IPS_ERR_HOST_RESET 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IPS_ERR_DEV_RESET 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IPS_ERR_RECOVERY 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IPS_ERR_CKCOND 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Operating System Defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IPS_OS_WINDOWS_NT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IPS_OS_NETWARE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IPS_OS_OPENSERVER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IPS_OS_UNIXWARE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IPS_OS_SOLARIS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IPS_OS_OS2 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IPS_OS_LINUX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IPS_OS_FREEBSD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Adapter Revision ID's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IPS_REVID_SERVERAID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IPS_REVID_NAVAJO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IPS_REVID_SERVERAID2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IPS_REVID_CLARINETP1 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IPS_REVID_CLARINETP2 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IPS_REVID_CLARINETP3 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IPS_REVID_TROMBONE32 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IPS_REVID_TROMBONE64 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * NVRAM Page 5 Adapter Defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IPS_ADTYPE_SERVERAID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IPS_ADTYPE_SERVERAID2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IPS_ADTYPE_NAVAJO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IPS_ADTYPE_KIOWA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IPS_ADTYPE_SERVERAID3 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IPS_ADTYPE_SERVERAID3L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IPS_ADTYPE_SERVERAID4H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IPS_ADTYPE_SERVERAID4M 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IPS_ADTYPE_SERVERAID4L 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IPS_ADTYPE_SERVERAID4MX 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IPS_ADTYPE_SERVERAID4LX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IPS_ADTYPE_SERVERAID5I2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IPS_ADTYPE_SERVERAID5I1 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IPS_ADTYPE_SERVERAID6M 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IPS_ADTYPE_SERVERAID6I 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IPS_ADTYPE_SERVERAID7t 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IPS_ADTYPE_SERVERAID7k 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IPS_ADTYPE_SERVERAID7M 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Adapter Command/Status Packet Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IPS_SUCCESS 0x01 /* Successfully completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IPS_FAILURE 0x04 /* Completed with Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Logical Drive Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IPS_LD_OFFLINE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IPS_LD_OKAY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IPS_LD_FREE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IPS_LD_SYS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IPS_LD_CRS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * DCDB Table Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IPS_NO_DISCONNECT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IPS_DISCONNECT_ALLOWED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IPS_NO_AUTO_REQSEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IPS_DATA_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IPS_DATA_UNK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IPS_DATA_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IPS_DATA_OUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IPS_TRANSFER64K 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IPS_NOTIMEOUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IPS_TIMEOUT10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IPS_TIMEOUT60 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IPS_TIMEOUT20M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * SCSI Inquiry Data Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IPS_SCSI_INQ_TYPE_DASD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IPS_SCSI_INQ_LU_CONNECTED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IPS_SCSI_INQ_RD_REV2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IPS_SCSI_INQ_REV2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IPS_SCSI_INQ_REV3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IPS_SCSI_INQ_Address16 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IPS_SCSI_INQ_Address32 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IPS_SCSI_INQ_MedChanger 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IPS_SCSI_INQ_MultiPort 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IPS_SCSI_INQ_EncServ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IPS_SCSI_INQ_SoftReset 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IPS_SCSI_INQ_CmdQue 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IPS_SCSI_INQ_Linked 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IPS_SCSI_INQ_Sync 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IPS_SCSI_INQ_WBus16 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IPS_SCSI_INQ_WBus32 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IPS_SCSI_INQ_RelAdr 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * SCSI Request Sense Data Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IPS_SCSI_REQSEN_VALID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IPS_SCSI_REQSEN_NO_SENSE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * SCSI Mode Page Equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IPS_SCSI_MP3_SoftSector 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IPS_SCSI_MP3_HardSector 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IPS_SCSI_MP3_Removeable 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IPS_SCSI_MP3_AllocateSurface 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * HA Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IPS_HA_ENH_SG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * SCB Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IPS_SCB_MAP_SG 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IPS_SCB_MAP_SINGLE 0X00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Passthru stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IPS_COPPUSRCMD (('C'<<8) | 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IPS_COPPIOCCMD (('C'<<8) | 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IPS_NUMCTRLS (('C'<<8) | 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IPS_CTRLINFO (('C'<<8) | 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* flashing defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IPS_FW_IMAGE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IPS_BIOS_IMAGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IPS_WRITE_FW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IPS_WRITE_BIOS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IPS_ERASE_BIOS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IPS_BIOS_HEADER 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* time oriented stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IPS_SECS_8HOURS 28800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Scsi_Host Template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sector_t capacity, int geom[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int ips_slave_configure(struct scsi_device *SDptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Raid Command Formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uint8_t log_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) uint8_t sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint32_t lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) uint32_t sg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) uint16_t sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uint8_t segment_4G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uint8_t enhanced_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } IPS_IO_CMD, *PIPS_IO_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } IPS_LD_CMD, *PIPS_LD_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint32_t reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uint8_t channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint8_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uint8_t reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint8_t reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint8_t reserved6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint8_t reserved7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint8_t reserved8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) uint8_t reserved9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint8_t reserved10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t reserved11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uint8_t reserved12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint8_t reserved13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint8_t reserved14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint8_t adapter_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } IPS_RESET_CMD, *PIPS_RESET_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint32_t dcdb_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint16_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t segment_4G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint8_t enhanced_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint8_t channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint8_t source_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } IPS_CS_CMD, *PIPS_CS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uint8_t log_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint8_t control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } IPS_US_CMD, *PIPS_US_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) uint8_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uint32_t reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } IPS_FC_CMD, *PIPS_FC_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uint8_t desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uint8_t page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint8_t write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uint32_t ccsar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint32_t cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) typedef struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) uint32_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uint8_t reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) uint8_t reset_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint8_t second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint8_t minute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) uint8_t hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) uint8_t day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) uint8_t reserved1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) uint8_t month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint8_t yearH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint8_t yearL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint8_t direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) uint8_t total_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint8_t packet_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) uint8_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uint8_t direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) uint32_t buffer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) IPS_IO_CMD basic_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) IPS_LD_CMD logical_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) IPS_IOCTL_CMD ioctl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) IPS_DCDB_CMD dcdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) IPS_CS_CMD config_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) IPS_US_CMD unlock_stripe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) IPS_FC_CMD flush_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) IPS_STATUS_CMD status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) IPS_NVRAM_CMD nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) IPS_FFDC_CMD ffdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) IPS_FLASHFW_CMD flashfw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) IPS_FLASHBIOS_CMD flashbios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) IPS_VERSION_INFO version_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) IPS_RESET_CMD reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uint8_t logical_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uint8_t raid_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) uint8_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uint32_t sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) uint8_t no_of_log_drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } IPS_LD_INFO, *PIPS_LD_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uint8_t device_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) uint8_t cmd_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uint16_t transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) uint32_t buffer_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint8_t cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) uint8_t sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint8_t sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) uint8_t scsi_cdb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) uint8_t sense_info[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) uint8_t reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) uint8_t device_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) uint8_t cmd_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uint8_t cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uint8_t reserved_for_LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) uint32_t transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint32_t buffer_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) uint16_t sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint8_t sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) uint8_t scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) uint8_t scsi_cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uint8_t sense_info[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) volatile uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) volatile uint8_t command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) volatile uint8_t basic_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) volatile uint8_t extended_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) volatile uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } IPS_STATUS, *PIPS_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) IPS_STATUS status[IPS_MAX_CMDS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) volatile PIPS_STATUS p_status_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) volatile PIPS_STATUS p_status_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) volatile PIPS_STATUS p_status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) volatile uint32_t hw_status_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) volatile uint32_t hw_status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } IPS_ADAPTER, *PIPS_ADAPTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) uint8_t ucLogDriveCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uint8_t ucMiscFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint8_t ucSLTFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint8_t ucBSTFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint8_t ucPwrChgCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint8_t ucWrongAdrCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint8_t ucUnidentCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uint8_t ucNVramDevChgCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint8_t CodeBlkVersion[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint8_t BootBlkVersion[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint32_t ulDriveSize[IPS_MAX_LD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint8_t ucConcurrentCmdCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) uint8_t ucMaxPhysicalDevices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) uint16_t usFlashRepgmCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) uint8_t ucDefunctDiskCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) uint8_t ucRebuildFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) uint8_t ucOfflineLogDrvCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uint8_t ucCriticalDrvCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uint16_t usConfigUpdateCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uint8_t ucBlkFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } IPS_ENQ, *PIPS_ENQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uint8_t ucInitiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uint8_t ucParameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) uint8_t ucMiscFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uint8_t ucState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint32_t ulBlockCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint8_t ucDeviceId[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } IPS_DEVSTATE, *PIPS_DEVSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint8_t ucChn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint8_t ucTgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint16_t ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint32_t ulStartSect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) uint32_t ulNoOfSects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } IPS_CHUNK, *PIPS_CHUNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) uint16_t ucUserField;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) uint8_t ucState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) uint8_t ucRaidCacheParam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) uint8_t ucNoOfChunkUnits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint8_t ucStripeSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uint8_t ucParams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint8_t ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uint32_t ulLogDrvSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) IPS_CHUNK chunk[IPS_MAX_CHUNKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } IPS_LD, *PIPS_LD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) uint8_t board_disc[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) uint8_t processor[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) uint8_t ucNoChanType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint8_t ucNoHostIntType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uint8_t ucCompression;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) uint8_t ucNvramType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) uint32_t ulNvramSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } IPS_HARDWARE, *PIPS_HARDWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) uint8_t ucLogDriveCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint8_t ucDateD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) uint8_t ucDateM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint8_t ucDateY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint8_t init_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint8_t host_id[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) uint8_t time_sign[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uint32_t UserOpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uint16_t user_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uint8_t ucRebuildRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint8_t ucReserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) IPS_HARDWARE hardware_disc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) IPS_LD logical_drive[IPS_MAX_LD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uint8_t reserved[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } IPS_CONF, *PIPS_CONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint8_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint8_t adapter_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uint16_t adapter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uint8_t ctrl_bios[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint8_t versioning; /* 1 = Versioning Supported, else 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint8_t operating_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) uint8_t driver_high[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) uint8_t driver_low[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) uint8_t BiosCompatibilityID[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint8_t ReservedForOS2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) uint8_t bios_low[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) uint8_t Filler[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Data returned from a GetVersion Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* SubSystem Parameter[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) typedef struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint32_t revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint8_t bootBlkVersion[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint8_t bootBlkAttributes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) uint8_t codeBlkVersion[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint8_t biosVersion[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint8_t biosAttributes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint8_t compatibilityId[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint8_t reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } IPS_VERSION_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) typedef struct _IPS_SUBSYS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint32_t param[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } IPS_SUBSYS, *PIPS_SUBSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ** SCSI Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Inquiry Data Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint8_t DeviceType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) uint8_t DeviceTypeQualifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) uint8_t Version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) uint8_t ResponseDataFormat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint8_t AdditionalLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) uint8_t Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) uint8_t Flags[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) uint8_t VendorId[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) uint8_t ProductId[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uint8_t ProductRevisionLevel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) uint8_t Reserved2; /* Provides NULL terminator to name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Read Capacity Data Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) uint32_t lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } IPS_SCSI_CAPACITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Request Sense Data Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uint8_t ResponseCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uint8_t SegmentNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) uint8_t Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) uint8_t Information[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) uint8_t AdditionalLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uint8_t CommandSpecific[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uint8_t AdditionalSenseCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) uint8_t AdditionalSenseCodeQual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uint8_t FRUCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint8_t SenseKeySpecific[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } IPS_SCSI_REQSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Sense Data Format - Page 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint8_t PageCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) uint8_t PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint16_t TracksPerZone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) uint16_t AltSectorsPerZone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint16_t AltTracksPerZone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint16_t AltTracksPerVolume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uint16_t SectorsPerTrack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) uint16_t BytesPerSector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) uint16_t Interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) uint16_t TrackSkew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint16_t CylinderSkew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) } IPS_SCSI_MODE_PAGE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Sense Data Format - Page 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) uint8_t PageCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) uint8_t PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint16_t CylindersHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint8_t CylindersLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) uint8_t Heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uint16_t WritePrecompHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) uint8_t WritePrecompLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) uint16_t ReducedWriteCurrentHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) uint8_t ReducedWriteCurrentLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) uint16_t StepRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) uint16_t LandingZoneHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uint8_t LandingZoneLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uint8_t RotationalOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) uint8_t Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint16_t MediumRotationRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uint8_t Reserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } IPS_SCSI_MODE_PAGE4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Sense Data Format - Page 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint8_t PageCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint8_t PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint8_t RetentPrio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint16_t DisPrefetchLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint16_t MinPrefetchLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint16_t MaxPrefetchLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint16_t MaxPrefetchCeiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } IPS_SCSI_MODE_PAGE8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * Sense Data Format - Block Descriptor (DASD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) uint32_t NumberOfBlocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uint8_t DensityCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uint16_t BlockLengthHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uint8_t BlockLengthLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } IPS_SCSI_MODE_PAGE_BLKDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * Sense Data Format - Mode Page Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint8_t DataLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) uint8_t MediumType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) uint8_t Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) uint8_t BlockDescLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } IPS_SCSI_MODE_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) IPS_SCSI_MODE_PAGE_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) IPS_SCSI_MODE_PAGE3 pg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) IPS_SCSI_MODE_PAGE4 pg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) IPS_SCSI_MODE_PAGE8 pg8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) } IPS_SCSI_MODE_PAGE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Scatter Gather list format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) typedef struct ips_sglist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uint32_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } IPS_STD_SG_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) typedef struct ips_enh_sglist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) uint32_t address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) uint32_t address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } IPS_ENH_SG_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) void *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) IPS_STD_SG_LIST *std_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) IPS_ENH_SG_LIST *enh_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) } IPS_SG_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) char *option_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int *option_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int option_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } IPS_OPTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Status Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) typedef struct ips_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) uint32_t residue_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) void *scb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) uint8_t padding[12 - sizeof(void *)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } ips_stat_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * SCB Queue Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) typedef struct ips_scb_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct ips_scb *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct ips_scb *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) } ips_scb_queue_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * Wait queue_format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) typedef struct ips_wait_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct scsi_cmnd *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct scsi_cmnd *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } ips_wait_queue_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) typedef struct ips_copp_wait_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct ips_copp_wait_item *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) } ips_copp_wait_item_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) typedef struct ips_copp_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct ips_copp_wait_item *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct ips_copp_wait_item *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) } ips_copp_queue_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* forward decl for host structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct ips_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int (*reset)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int (*issue)(struct ips_ha *, struct ips_scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int (*isinit)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int (*isintr)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int (*init)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int (*erasebios)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) void (*statinit)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int (*intr)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) void (*enableint)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) uint32_t (*statupd)(struct ips_ha *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) } ips_hw_func_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) typedef struct ips_ha {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint8_t ha_id[IPS_MAX_CHANNELS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint32_t dcdb_active[IPS_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint32_t io_addr; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) uint8_t ntargets; /* Number of targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) uint8_t nbus; /* Number of buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) uint8_t nlun; /* Number of Luns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uint16_t ad_type; /* Adapter type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint16_t host_num; /* Adapter number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint32_t max_xfer; /* Maximum Xfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uint32_t max_cmds; /* Max concurrent commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint32_t num_ioctl; /* Number of Ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ips_stat_t sp; /* Status packer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct ips_scb *scbs; /* Array of all CCBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct ips_scb *scb_freelist; /* SCB free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ips_wait_queue_entry_t scb_waitlist; /* Pending SCB list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ips_copp_queue_t copp_waitlist; /* Pending PT list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ips_scb_queue_t scb_activelist; /* Active SCB list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) IPS_IO_CMD *dummy; /* dummy command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) IPS_ADAPTER *adapt; /* Adapter status area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) IPS_ENQ *enq; /* Adapter Enquiry data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) IPS_CONF *conf; /* Adapter config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) IPS_SUBSYS *subsys; /* Subsystem parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) char *ioctl_data; /* IOCTL data area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) uint32_t ioctl_datasize; /* IOCTL data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) uint32_t cmd_in_progress; /* Current command in progress*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int flags; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) uint8_t waitflag; /* are we waiting for cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) uint8_t active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int ioctl_reset; /* IOCTL Requested Reset Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) uint16_t reset_count; /* number of resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) time64_t last_ffdc; /* last time we sent ffdc info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) uint8_t slot_num; /* PCI Slot Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int ioctl_len; /* size of ioctl buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) uint8_t bios_version[8]; /* BIOS Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) uint32_t mem_addr; /* Memory mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) uint32_t io_len; /* Size of IO Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) uint32_t mem_len; /* Size of memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) char __iomem *mem_ptr; /* Memory mapped Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) char __iomem *ioremap_ptr;/* ioremapped memory pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ips_hw_func_t func; /* hw function pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct pci_dev *pcidev; /* PCI device handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) char *flash_data; /* Save Area for flash data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int flash_len; /* length of flash buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u32 flash_datasize; /* Save Area for flash data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dma_addr_t flash_busaddr; /* dma address of flash buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dma_addr_t enq_busaddr; /* dma address of enq struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) uint8_t requires_esl; /* Requires an EraseStripeLock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } ips_ha_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * SCB Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) typedef struct ips_scb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) IPS_HOST_COMMAND cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) IPS_DCDB_TABLE dcdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) uint8_t cdb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uint32_t scb_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) uint32_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) uint8_t basic_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) uint8_t extended_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) uint8_t breakup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) uint8_t sg_break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) uint32_t data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) uint32_t sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) uint32_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) IPS_SG_LIST sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct ips_scb *q_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ips_scb_callback callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) uint32_t sg_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dma_addr_t data_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) } ips_scb_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) typedef struct ips_scb_pt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) IPS_HOST_COMMAND cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) IPS_DCDB_TABLE dcdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) uint8_t cdb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) uint32_t scb_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) uint32_t data_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) uint32_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) uint8_t basic_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) uint8_t extended_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) uint16_t breakup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) uint32_t data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) uint32_t sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) uint32_t op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) IPS_SG_LIST *sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct ips_scb *q_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ips_scb_callback callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } ips_scb_pt_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Passthru Command Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) uint8_t CoppID[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) uint32_t CoppCmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) uint32_t PtBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) uint8_t *CmdBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) uint32_t CmdBSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ips_scb_pt_t CoppCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) uint32_t TimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) uint8_t BasicStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) uint8_t ExtendedStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) uint8_t AdapterType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) } ips_passthru_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* The Version Information below gets created by SED during the build process. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Do not modify the next line; it's what SED is looking for to do the insert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Version Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * VERSION.H -- version numbers and copyright notices in various formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define IPS_VER_MAJOR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define IPS_VER_MINOR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define IPS_VER_BUILD 05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define IPS_RELEASE_ID 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define IPS_BUILD_IDENT 761
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Version numbers for various adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define IPS_VER_SERVERAID1 "2.25.01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define IPS_VER_SERVERAID2 "2.88.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define IPS_VER_NAVAJO "2.88.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define IPS_VER_SERVERAID3 "6.10.24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define IPS_VER_SERVERAID4H "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define IPS_VER_SERVERAID4MLx "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define IPS_VER_SARASOTA "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define IPS_VER_MARCO "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define IPS_VER_SEBRING "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define IPS_VER_KEYWEST "7.12.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Compatibility IDs for various adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define IPS_COMPAT_UNKNOWN ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define IPS_COMPAT_CURRENT "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define IPS_COMPAT_SERVERAID1 "2.25.01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define IPS_COMPAT_SERVERAID2 "2.88.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define IPS_COMPAT_NAVAJO "2.88.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define IPS_COMPAT_KIOWA "2.88.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define IPS_COMPAT_SERVERAID3H "SB610"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define IPS_COMPAT_SERVERAID3L "SB610"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define IPS_COMPAT_SERVERAID4H "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define IPS_COMPAT_SERVERAID4M "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define IPS_COMPAT_SERVERAID4L "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define IPS_COMPAT_SERVERAID4Mx "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define IPS_COMPAT_SERVERAID4Lx "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define IPS_COMPAT_SARASOTA "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define IPS_COMPAT_MARCO "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define IPS_COMPAT_SEBRING "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define IPS_COMPAT_TAMPA "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define IPS_COMPAT_KEYWEST "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define IPS_COMPAT_BIOS "KW710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define IPS_COMPAT_ID_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define IPS_DEFINE_COMPAT_TABLE(tablename) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) IPS_COMPAT_UNKNOWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) IPS_COMPAT_SERVERAID1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) IPS_COMPAT_SERVERAID2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) IPS_COMPAT_NAVAJO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) IPS_COMPAT_KIOWA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) IPS_COMPAT_SERVERAID3H, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) IPS_COMPAT_SERVERAID3L, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) IPS_COMPAT_SERVERAID4H, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) IPS_COMPAT_SERVERAID4M, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) IPS_COMPAT_SERVERAID4L, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) IPS_COMPAT_SERVERAID4Mx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) IPS_COMPAT_SERVERAID4Lx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) IPS_COMPAT_MARCO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) IPS_COMPAT_SEBRING, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) IPS_COMPAT_TAMPA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) IPS_COMPAT_KEYWEST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Overrides for Emacs so that we almost follow Linus's tabbing style.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * Emacs will notice this stuff at the end of the file and automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * adjust the settings for this buffer only. This must remain at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * of the file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * Local variables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * c-indent-level: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * c-brace-imaginary-offset: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * c-brace-offset: -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * c-argdecl-indent: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * c-label-offset: -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * c-continued-statement-offset: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * c-continued-brace-offset: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * indent-tabs-mode: nil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * tab-width: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * End:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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