^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ipr.h -- driver for IBM Power Linux RAID adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003, 2004 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * that broke 64bit platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _IPR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _IPR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kref.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irq_poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPR_DRIVER_VERSION "2.6.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPR_DRIVER_DATE "(March 14, 2017)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ops per device for devices not running tagged command queuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * This can be adjusted at runtime through sysfs device attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPR_MAX_CMD_PER_LUN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPR_MAX_CMD_PER_ATA_LUN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ops the mid-layer can send to the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_IBM_RATTLESNAKE 0x04DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IPR_SUBS_DEV_ID_2780 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IPR_SUBS_DEV_ID_5702 0x0266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IPR_SUBS_DEV_ID_5703 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IPR_SUBS_DEV_ID_572E 0x028D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IPR_SUBS_DEV_ID_573E 0x02D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IPR_SUBS_DEV_ID_573D 0x02D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IPR_SUBS_DEV_ID_571A 0x02C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IPR_SUBS_DEV_ID_571B 0x02BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IPR_SUBS_DEV_ID_571E 0x02BF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IPR_SUBS_DEV_ID_571F 0x02D5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IPR_SUBS_DEV_ID_572A 0x02C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IPR_SUBS_DEV_ID_572B 0x02C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IPR_SUBS_DEV_ID_572F 0x02C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IPR_SUBS_DEV_ID_574E 0x030A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IPR_SUBS_DEV_ID_575B 0x030D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IPR_SUBS_DEV_ID_575C 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPR_SUBS_DEV_ID_57B3 0x033A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IPR_SUBS_DEV_ID_57B7 0x0360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IPR_SUBS_DEV_ID_57B8 0x02C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IPR_SUBS_DEV_ID_57B4 0x033B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IPR_SUBS_DEV_ID_57B2 0x035F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IPR_SUBS_DEV_ID_57C0 0x0352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IPR_SUBS_DEV_ID_57C3 0x0353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IPR_SUBS_DEV_ID_57C4 0x0354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPR_SUBS_DEV_ID_57C6 0x0357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IPR_SUBS_DEV_ID_57CC 0x035C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IPR_SUBS_DEV_ID_57B5 0x033C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IPR_SUBS_DEV_ID_57CE 0x035E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IPR_SUBS_DEV_ID_57B1 0x0355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IPR_SUBS_DEV_ID_574D 0x0356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IPR_SUBS_DEV_ID_57C8 0x035D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IPR_SUBS_DEV_ID_57D5 0x03FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IPR_SUBS_DEV_ID_57D6 0x03FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IPR_SUBS_DEV_ID_57D7 0x03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IPR_SUBS_DEV_ID_57D8 0x03FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IPR_SUBS_DEV_ID_57D9 0x046D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IPR_SUBS_DEV_ID_57DA 0x04CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IPR_SUBS_DEV_ID_57EB 0x0474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IPR_SUBS_DEV_ID_57EC 0x0475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IPR_SUBS_DEV_ID_57ED 0x0499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IPR_SUBS_DEV_ID_57EE 0x049A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IPR_SUBS_DEV_ID_57EF 0x049B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IPR_SUBS_DEV_ID_57F0 0x049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IPR_SUBS_DEV_ID_2CCA 0x04C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IPR_SUBS_DEV_ID_2CD2 0x04C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IPR_SUBS_DEV_ID_2CCD 0x04C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IPR_SUBS_DEV_ID_580A 0x04FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IPR_SUBS_DEV_ID_580B 0x04FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPR_NAME "ipr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IPR_RC_JOB_CONTINUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IPR_RC_JOB_RETURN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * IOASCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IPR_IOASC_HW_CMD_FAILED 0x046E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IPR_IOASC_BUS_WAS_RESET 0x06290000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IPR_FIRST_DRIVER_IOASC 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPR_IOASC_IOA_WAS_RESET 0x10000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Driver data flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IPR_USE_PCI_WARM_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IPR_DEFAULT_MAX_ERROR_DUMP 984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IPR_NUM_LOG_HCAMS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IPR_NUM_CFG_CHG_HCAMS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IPR_NUM_HCAM_QUEUE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IPR_MAX_HCAMS (IPR_NUM_HCAMS + IPR_NUM_HCAM_QUEUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IPR_MAX_NUM_TARGETS_PER_BUS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IPR_MAX_NUM_LUNS_PER_TARGET 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IPR_VSET_BUS 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IPR_IOA_BUS 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IPR_IOA_TARGET 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IPR_IOA_LUN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IPR_MAX_NUM_BUSES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IPR_NUM_RESET_RELOAD_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IPR_MAX_COMMANDS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IPR_NUM_INTERNAL_CMD_BLKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IPR_MAX_PHYSICAL_DEVS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IPR_DEFAULT_SIS64_DEVS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IPR_MAX_SIS64_DEVS 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IPR_MAX_SGLIST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IPR_IOA_MAX_SECTORS 32767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IPR_VSET_MAX_SECTORS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IPR_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IPR_MAX_HRRQ_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IPR_DEFAULT_BUS_WIDTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IPR_IOA_RES_HANDLE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IPR_INVALID_RES_HANDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IPR_IOA_RES_ADDR 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Adapter Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IPR_CANCEL_REQUEST 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IPR_CANCEL_64BIT_IOARCB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IPR_QUERY_RSRC_STATE 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IPR_RESET_DEVICE 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IPR_RESET_TYPE_SELECT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IPR_LUN_RESET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IPR_TARGET_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IPR_BUS_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IPR_ATA_PHY_RESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IPR_ID_HOST_RR_Q 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IPR_QUERY_IOA_CONFIG 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IPR_CANCEL_ALL_REQUESTS 0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IPR_HOST_CONTROLLED_ASYNC 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IPR_SET_SUPPORTED_DEVICES 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IPR_IOA_SHUTDOWN 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IPR_IOA_SERVICE_ACTION 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* IOA Service Actions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IPR_DUMP_DELAY_SECONDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * SCSI Literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IPR_VENDOR_ID_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IPR_PROD_ID_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IPR_SERIAL_NUM_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Hardware literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IPR_GET_FMT2_BAR_SEL(mbx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IPR_SDT_FMT2_BAR0_SEL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IPR_SDT_FMT2_BAR1_SEL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IPR_SDT_FMT2_BAR2_SEL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IPR_SDT_FMT2_BAR3_SEL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IPR_SDT_FMT2_BAR4_SEL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IPR_SDT_FMT2_BAR5_SEL 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IPR_DOORBELL 0x82800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IPR_RUNTIME_RESET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IPR_IPL_INIT_MIN_STAGE_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IPR_IPL_INIT_STAGE_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IPR_WAIT_FOR_MAILBOX (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IPR_PCII_ERROR_INTERRUPTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IPR_PCII_OPER_INTERRUPTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Dump literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IPR_FMT2_NUM_SDT_ENTRIES 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Misc literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IPR_MAX_MSIX_VECTORS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IPR_MAX_HRRQ_NUM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IPR_INIT_HRRQ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Adapter interface types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct ipr_res_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IPR_GET_PHYS_LOC(res_addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct ipr_std_inq_vpids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 vendor_id[IPR_VENDOR_ID_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 product_id[IPR_PROD_ID_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct ipr_vpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct ipr_std_inq_vpids vpids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 sn[IPR_SERIAL_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct ipr_ext_vpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct ipr_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) __be32 wwid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct ipr_ext_vpd64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct ipr_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __be32 wwid[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct ipr_std_inq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 peri_qual_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 removeable_medium_rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IPR_IS_DASD_DEVICE(std_inq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IPR_IS_SES_DEVICE(std_inq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 aen_naca_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 additional_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 sccs_rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 bq_enc_multi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 sync_cmdq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ipr_std_inq_vpids vpids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 ros_rsvd_ram_rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 serial_num[IPR_SERIAL_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }__attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IPR_RES_TYPE_AF_DASD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IPR_RES_TYPE_GENERIC_SCSI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IPR_RES_TYPE_VOLUME_SET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IPR_RES_TYPE_GENERIC_ATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IPR_RES_TYPE_ARRAY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IPR_RES_TYPE_IOAFP 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct ipr_config_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IPR_PROTO_SATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IPR_PROTO_SATA_ATAPI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IPR_PROTO_SAS_STP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IPR_PROTO_SAS_STP_ATAPI 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IPR_IS_IOA_RESOURCE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 rsvd_subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IPR_QUEUE_FROZEN_MODEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IPR_QUEUE_NACA_MODEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct ipr_res_addr res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) __be32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __be32 lun_wwn[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ipr_std_inq_data std_inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }__attribute__ ((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct ipr_config_table_entry64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 res_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 vset_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __be16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __be16 res_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __be32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 dev_id_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __be64 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __be64 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __be64 lun_wwn[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IPR_MAX_RES_PATH_LENGTH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __be64 res_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct ipr_std_inq_data std_inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 reserved2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) __be64 reserved3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 reserved4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }__attribute__ ((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ipr_config_table_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IPR_UCODE_DOWNLOAD_REQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ipr_config_table_hdr64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __be16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 reserved2[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct ipr_config_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct ipr_config_table_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct ipr_config_table_entry dev[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct ipr_config_table64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct ipr_config_table_hdr64 hdr64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ipr_config_table_entry64 dev[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ipr_config_table_entry_wrapper {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct ipr_config_table_entry *cfgte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct ipr_config_table_entry64 *cfgte64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct ipr_hostrcb_cfg_ch_not {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct ipr_config_table_entry cfgte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ipr_config_table_entry64 cfgte64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 reserved[936];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct ipr_supported_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __be16 data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 num_records;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct ipr_std_inq_vpids vpids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 reserved2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct ipr_hrr_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __be32 *host_rrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dma_addr_t host_rrq_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define IPR_HRRQ_RESP_BIT_SET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define IPR_HRRQ_TOGGLE_BIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IPR_ID_HRRQ_SELE_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) volatile __be32 *hrrq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) volatile __be32 *hrrq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) volatile __be32 *hrrq_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct list_head hrrq_free_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct list_head hrrq_pending_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spinlock_t _lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) volatile u32 toggle_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 min_cmd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 max_cmd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 allow_interrupts:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 ioa_is_dead:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 allow_cmds:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 removing_ioa:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct irq_poll iopoll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Command packet structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct ipr_cmd_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 reserved; /* Reserved by IOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 hrrq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 request_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IPR_RQTYPE_SCSICDB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IPR_RQTYPE_IOACMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IPR_RQTYPE_HCAM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IPR_RQTYPE_ATA_PASSTHRU 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IPR_RQTYPE_PIPE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 flags_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 flags_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define IPR_FLAGS_LO_ORDERED_TASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IPR_FLAGS_LO_ACA_TASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __be16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }__attribute__ ((packed, aligned(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct ipr_ioarcb_ata_regs { /* 22 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define IPR_ATA_FLAG_PACKET_CMD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __be16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 hob_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 hob_nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 hob_lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 hob_lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 hob_lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }__attribute__ ((packed, aligned(2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct ipr_ioadl_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __be32 flags_and_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IPR_IOADL_FLAGS_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IPR_IOADL_FLAGS_READ 0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define IPR_IOADL_FLAGS_WRITE 0x68000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IPR_IOADL_FLAGS_LAST 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __be32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct ipr_ioadl64_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __be32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __be64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }__attribute__((packed, aligned (16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct ipr_ata64_ioadl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct ipr_ioarcb_ata_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u16 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }__attribute__((packed, aligned (16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct ipr_ioarcb_add_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct ipr_ioarcb_ata_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct ipr_ioadl_desc ioadl[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __be32 add_cmd_parms[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }__attribute__ ((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct ipr_ioarcb_sis64_add_addr_ecb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) __be64 ioasa_host_pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __be64 data_ioadl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __be64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) __be32 ext_control_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* IOA Request Control Block 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct ipr_ioarcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) __be32 ioarcb_host_pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __be64 ioarcb_host_pci_addr64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __be32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __be32 host_response_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __be32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __be32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) __be32 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __be32 data_transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __be32 read_data_transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __be32 write_ioadl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __be32 ioadl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __be32 read_ioadl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __be32 read_ioadl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __be32 ioasa_host_pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __be16 ioasa_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) __be16 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct ipr_cmd_pkt cmd_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) __be16 add_cmd_parms_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __be16 add_cmd_parms_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct ipr_ioarcb_add_data add_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct ipr_ioasa_vset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __be32 failing_lba_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __be32 failing_lba_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __be32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct ipr_ioasa_af_dasd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) __be32 failing_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __be32 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct ipr_ioasa_gpdd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 end_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 bus_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __be32 ioa_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct ipr_ioasa_gata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 nsect; /* Interrupt reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u8 lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u8 lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 alt_status; /* ATA CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 hob_nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 hob_lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 hob_lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 hob_lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct ipr_auto_sense {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __be16 auto_sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __be16 ioa_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct ipr_ioasa_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __be32 ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) __be16 ret_stat_len; /* Length of the returned IOASA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) __be16 avail_stat_len; /* Total Length of status available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __be32 residual_data_len; /* number of bytes in the host data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* buffers that were not used by the IOARCB command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __be32 ilid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define IPR_NO_ILID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define IPR_DRIVER_ILID 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __be32 fd_ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __be32 fd_phys_locator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __be32 fd_res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __be32 ioasc_specific; /* status code specific field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define IPR_AUTOSENSE_VALID 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define IPR_FIELD_POINTER_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct ipr_ioasa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct ipr_ioasa_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct ipr_ioasa_vset vset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct ipr_ioasa_af_dasd dasd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct ipr_ioasa_gpdd gpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct ipr_ioasa_gata gata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct ipr_auto_sense auto_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct ipr_ioasa64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct ipr_ioasa_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 fd_res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct ipr_ioasa_vset vset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct ipr_ioasa_af_dasd dasd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct ipr_ioasa_gpdd gpdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct ipr_ioasa_gata gata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct ipr_auto_sense auto_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ipr_mode_parm_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 medium_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 device_spec_parms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 block_desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct ipr_mode_pages {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct ipr_mode_parm_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct ipr_mode_page_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u8 ps_page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define IPR_MODE_PAGE_PS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 page_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }__attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct ipr_dev_bus_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct ipr_res_addr res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define IPR_SCSI_ATTR_QAS_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define IPR_SCSI_ATTR_ENABLE_TM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u8 extended_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define IPR_EXTENDED_RESET_DELAY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __be32 max_xfer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 spinup_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u8 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) __be16 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct ipr_mode_page28 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct ipr_mode_page_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u8 entry_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct ipr_dev_bus_entry bus[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct ipr_mode_page24 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct ipr_mode_page_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define IPR_ENABLE_DUAL_IOA_AF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct ipr_ioa_vpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct ipr_std_inq_data std_inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u8 ascii_part_num[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u8 reserved[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 ascii_plant_code[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct ipr_inquiry_page3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 peri_qual_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u8 page_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u8 ascii_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 load_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u8 major_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u8 card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u8 minor_release[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u8 ptf_number[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 patch_number[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct ipr_inquiry_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u8 peri_qual_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u8 page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u8 page_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u8 ascii_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 sis_version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define IPR_CAP_DUAL_IOA_RAID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u8 reserved3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define IPR_INQUIRY_PAGE0_ENTRIES 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct ipr_inquiry_page0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 peri_qual_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }__attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct ipr_inquiry_pageC4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 peri_qual_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u8 page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 cache_cap[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define IPR_CAP_SYNC_CACHE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u8 reserved2[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct ipr_hostrcb_device_data_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct ipr_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct ipr_res_addr dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct ipr_vpd new_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct ipr_vpd ioa_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct ipr_vpd cfc_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __be32 ioa_data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct ipr_hostrcb_device_data_entry_enhanced {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct ipr_ext_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct ipr_res_addr dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct ipr_ext_vpd new_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 new_ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct ipr_ext_vpd ioa_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct ipr_ext_vpd cfc_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct ipr_hostrcb64_device_data_entry_enhanced {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct ipr_ext_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u8 ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct ipr_ext_vpd new_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u8 new_ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct ipr_ext_vpd ioa_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct ipr_ext_vpd cfc_last_with_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct ipr_hostrcb_array_data_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct ipr_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct ipr_res_addr expected_dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct ipr_res_addr dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct ipr_hostrcb64_array_data_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct ipr_ext_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u8 ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u8 expected_res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct ipr_hostrcb_array_data_entry_enhanced {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct ipr_ext_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u8 ccin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct ipr_res_addr expected_dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct ipr_res_addr dev_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct ipr_hostrcb_type_ff_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __be32 ioa_data[758];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct ipr_hostrcb_type_01_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __be32 seek_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __be32 read_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u8 sense_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) __be32 ioa_data[236];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct ipr_hostrcb_type_21_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) __be32 wwn[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u8 primary_problem_desc[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 second_problem_desc[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __be32 sense_data[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) __be32 cdb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __be32 residual_trans_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) __be32 length_of_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) __be32 ioa_data[236];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct ipr_hostrcb_type_02_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct ipr_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct ipr_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct ipr_vpd ioa_last_attached_to_cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct ipr_vpd cfc_last_attached_to_ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) __be32 ioa_data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct ipr_hostrcb_type_12_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct ipr_ext_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ipr_ext_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) __be32 ioa_data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct ipr_hostrcb_type_03_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct ipr_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct ipr_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) __be32 errors_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __be32 errors_logged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u8 ioa_data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct ipr_hostrcb_device_data_entry dev[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct ipr_hostrcb_type_13_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct ipr_ext_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct ipr_ext_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) __be32 errors_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) __be32 errors_logged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct ipr_hostrcb_device_data_entry_enhanced dev[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct ipr_hostrcb_type_23_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct ipr_ext_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct ipr_ext_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) __be32 errors_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) __be32 errors_logged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct ipr_hostrcb_type_04_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct ipr_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct ipr_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u8 ioa_data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct ipr_hostrcb_array_data_entry array_member[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) __be32 exposed_mode_adn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) __be32 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct ipr_vpd incomp_dev_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) __be32 ioa_data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct ipr_hostrcb_array_data_entry array_member2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct ipr_res_addr last_func_vset_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u8 protection_level[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct ipr_hostrcb_type_14_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct ipr_ext_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct ipr_ext_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) __be32 exposed_mode_adn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) __be32 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct ipr_res_addr last_func_vset_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u8 protection_level[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) __be32 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct ipr_hostrcb_type_24_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct ipr_ext_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct ipr_ext_vpd cfc_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u8 exposed_mode_adn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define IPR_INVALID_ARRAY_DEV_NUM 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u8 array_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u8 last_res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) u8 protection_level[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct ipr_ext_vpd64 array_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u8 description[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u8 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct ipr_hostrcb64_array_data_entry array_member[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct ipr_hostrcb_type_07_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u8 failure_reason[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct ipr_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) __be32 data[222];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct ipr_hostrcb_type_17_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u8 failure_reason[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct ipr_ext_vpd vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) __be32 data[476];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct ipr_hostrcb_config_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u8 type_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define IPR_PATH_CFG_TYPE_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define IPR_PATH_CFG_NOT_EXIST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define IPR_PATH_CFG_IOA_PORT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define IPR_PATH_CFG_EXP_PORT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define IPR_PATH_CFG_DEVICE_PORT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define IPR_PATH_CFG_DEVICE_LUN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define IPR_PATH_CFG_STATUS_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define IPR_PATH_CFG_NO_PROB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define IPR_PATH_CFG_DEGRADED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define IPR_PATH_CFG_FAILED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define IPR_PATH_CFG_SUSPECT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define IPR_PATH_NOT_DETECTED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define IPR_PATH_INCORRECT_CONN 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u8 cascaded_expander;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) u8 phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u8 link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define IPR_PHY_LINK_RATE_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) __be32 wwid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct ipr_hostrcb64_config_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) __be16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u8 descriptor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define IPR_DESCRIPTOR_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define IPR_DESCRIPTOR_SIS64 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u8 type_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u8 reserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u8 link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) __be32 wwid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct ipr_hostrcb_fabric_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) __be16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u8 ioa_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u8 cascaded_expander;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u8 path_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define IPR_PATH_ACTIVE_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define IPR_PATH_NO_INFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define IPR_PATH_ACTIVE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define IPR_PATH_NOT_ACTIVE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define IPR_PATH_STATE_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define IPR_PATH_STATE_NO_INFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define IPR_PATH_HEALTHY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define IPR_PATH_DEGRADED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define IPR_PATH_FAILED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) __be16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct ipr_hostrcb_config_element elem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct ipr_hostrcb64_fabric_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) __be16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u8 descriptor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u8 path_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u8 reserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u8 reserved3[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) __be16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct ipr_hostrcb64_config_element elem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define for_each_hrrq(hrrq, ioa_cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) for (hrrq = (ioa_cfg)->hrrq; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define for_each_fabric_cfg(fabric, cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) for (cfg = (fabric)->elem; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct ipr_hostrcb_type_20_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u8 failure_reason[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct ipr_hostrcb_fabric_desc desc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct ipr_hostrcb_type_30_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u8 failure_reason[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct ipr_hostrcb64_fabric_desc desc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct ipr_hostrcb_type_41_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u8 failure_reason[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) __be32 data[200];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct ipr_hostrcb_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) __be32 fd_ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct ipr_res_addr fd_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) __be32 fd_res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) __be32 prc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct ipr_hostrcb_type_ff_error type_ff_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct ipr_hostrcb_type_01_error type_01_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct ipr_hostrcb_type_02_error type_02_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct ipr_hostrcb_type_03_error type_03_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct ipr_hostrcb_type_04_error type_04_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct ipr_hostrcb_type_07_error type_07_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct ipr_hostrcb_type_12_error type_12_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct ipr_hostrcb_type_13_error type_13_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct ipr_hostrcb_type_14_error type_14_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct ipr_hostrcb_type_17_error type_17_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct ipr_hostrcb_type_20_error type_20_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct ipr_hostrcb64_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) __be32 fd_ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) __be32 ioa_fw_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) __be32 fd_res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) __be32 prc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) __be64 fd_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) __be64 fd_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u8 fd_res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) __be64 time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u8 reserved[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct ipr_hostrcb_type_ff_error type_ff_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct ipr_hostrcb_type_12_error type_12_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct ipr_hostrcb_type_17_error type_17_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct ipr_hostrcb_type_21_error type_21_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct ipr_hostrcb_type_23_error type_23_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct ipr_hostrcb_type_24_error type_24_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct ipr_hostrcb_type_30_error type_30_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct ipr_hostrcb_type_41_error type_41_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }__attribute__((packed, aligned (8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct ipr_hostrcb_raw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct ipr_hcam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u8 op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u8 notify_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u8 notifications_lost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define IPR_HOSTRCB_INTERNAL_OPER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u8 overlay_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define IPR_HOST_RCB_OVERLAY_ID_21 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define IPR_HOST_RCB_OVERLAY_ID_41 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) __be32 ilid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) __be32 time_since_last_ioa_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) __be32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) __be32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct ipr_hostrcb_error error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct ipr_hostrcb64_error error64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct ipr_hostrcb_cfg_ch_not ccn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct ipr_hostrcb_raw raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct ipr_hostrcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct ipr_hcam hcam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dma_addr_t hostrcb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* IPR smart dump table structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct ipr_sdt_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) __be32 start_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) __be32 end_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define IPR_SDT_ENDIAN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define IPR_SDT_VALID_ENTRY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u8 resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) __be16 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct ipr_sdt_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __be32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) __be32 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) __be32 num_entries_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) __be32 dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct ipr_sdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct ipr_sdt_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct ipr_uc_sdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ipr_sdt_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct ipr_sdt_entry entry[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Driver types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct ipr_bus_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u8 qas_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u8 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) u32 max_xfer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct ipr_sata_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct ipr_resource_entry *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct ipr_ioasa_gata ioasa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct ipr_resource_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u8 needs_sync_complete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u8 in_erp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u8 add_to_ml:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u8 del_from_ml:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u8 resetting_device:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u8 reset_occurred:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) u8 raw_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u32 bus; /* AKA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u32 target; /* AKA id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u32 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define IPR_ARRAY_VIRTUAL_BUS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define IPR_VSET_VIRTUAL_BUS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define IPR_IOAFP_VIRTUAL_BUS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define IPR_MAX_SIS64_BUSES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define IPR_GET_RES_PHYS_LOC(res) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u8 ata_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u16 res_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u8 qmodel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct ipr_std_inq_data std_inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __be32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) __be64 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) u64 lun_wwn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct scsi_lun dev_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u8 res_path[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct ipr_sata_port *sata_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }; /* struct ipr_resource_entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct ipr_resource_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) u16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct ipr_misc_cbs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct ipr_ioa_vpd ioa_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct ipr_inquiry_page0 page0_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct ipr_inquiry_page3 page3_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct ipr_inquiry_cap cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct ipr_inquiry_pageC4 pageC4_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct ipr_mode_pages mode_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct ipr_supported_device supp_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct ipr_interrupt_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) unsigned long set_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) unsigned long clr_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) unsigned long clr_interrupt_mask_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) unsigned long sense_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) unsigned long sense_interrupt_mask_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) unsigned long clr_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) unsigned long clr_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unsigned long sense_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) unsigned long sense_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) unsigned long ioarrin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) unsigned long sense_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) unsigned long sense_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) unsigned long set_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) unsigned long set_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) unsigned long clr_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) unsigned long clr_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) unsigned long init_feedback_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) unsigned long dump_addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) unsigned long dump_data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define IPR_ENDIAN_SWAP_KEY 0x00080800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) unsigned long endian_swap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct ipr_interrupts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) void __iomem *set_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) void __iomem *clr_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) void __iomem *clr_interrupt_mask_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) void __iomem *sense_interrupt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) void __iomem *sense_interrupt_mask_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) void __iomem *clr_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) void __iomem *clr_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) void __iomem *sense_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) void __iomem *sense_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) void __iomem *ioarrin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) void __iomem *sense_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) void __iomem *sense_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) void __iomem *set_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) void __iomem *set_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) void __iomem *clr_uproc_interrupt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) void __iomem *clr_uproc_interrupt_reg32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) void __iomem *init_feedback_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) void __iomem *dump_addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) void __iomem *dump_data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) void __iomem *endian_swap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct ipr_chip_cfg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) u32 mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) u16 max_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) u8 cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) u8 clear_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) u32 iopoll_weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct ipr_interrupt_offsets regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct ipr_chip_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) bool has_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u16 sis_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define IPR_SIS32 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define IPR_SIS64 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u16 bist_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define IPR_PCI_CFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define IPR_MMIO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) const struct ipr_chip_cfg_t *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) enum ipr_shutdown_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) IPR_SHUTDOWN_NORMAL = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) IPR_SHUTDOWN_ABBREV = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) IPR_SHUTDOWN_NONE = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) IPR_SHUTDOWN_QUIESCE = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct ipr_trace_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u32 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u8 op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u8 ata_op_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define IPR_TRACE_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define IPR_TRACE_FINISH 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u8 cmd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) __be32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 add_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) u32 res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct ipr_sglist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u32 num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u32 num_dma_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u32 buffer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct scatterlist *scatterlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) enum ipr_sdt_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) WAIT_FOR_DUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) GET_DUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) READ_DUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ABORT_DUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) DUMP_OBTAINED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Per-controller data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct ipr_ioa_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) char eye_catcher[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define IPR_EYECATCHER "iprcfg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u8 in_reset_reload:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u8 in_ioa_bringdown:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u8 ioa_unit_checked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u8 dump_taken:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) u8 scan_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u8 scan_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u8 needs_hard_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u8 dual_raid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u8 needs_warm_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) u8 msi_received:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u8 sis64:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u8 dump_timeout:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) u8 cfg_locked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u8 clear_isr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) u8 probe_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) u8 scsi_unblock:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) u8 scsi_blocked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) u8 revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * Bitmaps for SIS64 generated target values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) u16 type; /* CCIN of the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u8 log_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define IPR_MAX_LOG_LEVEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define IPR_DEFAULT_LOG_LEVEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define IPR_DEBUG_LOG_LEVEL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define IPR_NUM_TRACE_INDEX_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) char trace_start[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define IPR_TRACE_START_LABEL "trace"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct ipr_trace_entry *trace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) atomic_t trace_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) char cfg_table_start[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define IPR_CFG_TBL_START "cfg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct ipr_config_table *cfg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct ipr_config_table64 *cfg_table64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dma_addr_t cfg_table_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) u32 cfg_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) u32 max_devs_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) char resource_table_label[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define IPR_RES_TABLE_LABEL "res_tbl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct ipr_resource_entry *res_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct list_head free_res_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct list_head used_res_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) char ipr_hcam_label[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define IPR_HCAM_LABEL "hcams"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct ipr_hostrcb *hostrcb[IPR_MAX_HCAMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) dma_addr_t hostrcb_dma[IPR_MAX_HCAMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct list_head hostrcb_free_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct list_head hostrcb_pending_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct list_head hostrcb_report_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) u32 hrrq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) atomic_t hrrq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) u16 identify_hrrq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) unsigned int transop_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) const struct ipr_chip_cfg_t *chip_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) const struct ipr_chip_t *ipr_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) void __iomem *ioa_mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct ipr_interrupts regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u16 saved_pcix_cmd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) u16 reset_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) u32 errors_logged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) struct ipr_sglist *ucode_sglist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) u8 saved_mode_page_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct work_struct work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct work_struct scsi_add_work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct workqueue_struct *reset_work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) wait_queue_head_t reset_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) wait_queue_head_t msi_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) wait_queue_head_t eeh_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct ipr_dump *dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) enum ipr_sdt_state sdt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct ipr_misc_cbs *vpd_cbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dma_addr_t vpd_cbs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct dma_pool *ipr_cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct ipr_cmnd *reset_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) int (*reset) (struct ipr_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct ata_host ata_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) char ipr_cmd_label[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define IPR_CMD_LABEL "ipr_cmd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) u32 max_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct ipr_cmnd **ipr_cmnd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dma_addr_t *ipr_cmnd_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) unsigned int nvectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) char desc[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) } vectors_info[IPR_MAX_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) u32 iopoll_weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }; /* struct ipr_ioa_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct ipr_cmnd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct ipr_ioarcb ioarcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct ipr_ata64_ioadl ata_ioadl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) } i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct ipr_ioasa ioasa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct ipr_ioasa64 ioasa64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) void (*fast_done) (struct ipr_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) void (*done) (struct ipr_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) int (*job_step) (struct ipr_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int (*job_step_failed) (struct ipr_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) u16 cmd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dma_addr_t sense_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) unsigned short dma_use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct ipr_cmnd *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) enum ipr_shutdown_type shutdown_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct ipr_hostrcb *hostrcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) unsigned long scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct ipr_resource_entry *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct completion *eh_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct ipr_hrr_queue *hrrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct ipr_ses_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) char product_id[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) char compare_product_id_byte[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct ipr_dump_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u32 eye_catcher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u32 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u32 first_entry_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define IPR_DUMP_STATUS_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define IPR_DUMP_STATUS_FAILED 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define IPR_DUMP_OS_LINUX 0x4C4E5558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) u32 driver_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define IPR_DUMP_DRIVER_NAME 0x49505232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct ipr_dump_entry_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u32 eye_catcher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 num_elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) u32 data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define IPR_DUMP_LOCATION_ID 0x4C4F4341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define IPR_DUMP_TRACE_ID 0x54524143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define IPR_DUMP_PEND_OPS 0x414F5053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct ipr_dump_location_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct ipr_dump_entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) u8 location[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct ipr_dump_trace_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct ipr_dump_entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct ipr_dump_version_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct ipr_dump_entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) u8 version[sizeof(IPR_DRIVER_VERSION)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct ipr_dump_ioa_type_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct ipr_dump_entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct ipr_driver_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct ipr_dump_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct ipr_dump_version_entry version_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct ipr_dump_location_entry location_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct ipr_dump_ioa_type_entry ioa_type_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct ipr_dump_trace_entry trace_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct ipr_ioa_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct ipr_dump_entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct ipr_sdt sdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) __be32 **ioa_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) u32 next_page_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u32 page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct ipr_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct ipr_ioa_cfg *ioa_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct ipr_driver_dump driver_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct ipr_ioa_dump ioa_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct ipr_error_table_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) u32 ioasc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int log_ioasa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) int log_hcam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) char *error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct ipr_software_inq_lid_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) __be32 load_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) __be32 timestamp[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct ipr_ucode_image_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) __be32 header_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) __be32 lid_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u8 major_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) u8 card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) u8 minor_release[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u8 reserved[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) char eyecatcher[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) __be32 num_lids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) struct ipr_software_inq_lid_info lid[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }__attribute__((packed, aligned (4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * Macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #ifdef CONFIG_SCSI_IPR_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define ipr_create_trace_file(kobj, attr) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define ipr_remove_trace_file(kobj, attr) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #ifdef CONFIG_SCSI_IPR_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define ipr_create_dump_file(kobj, attr) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define ipr_remove_dump_file(kobj, attr) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * Error logging macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) bus, target, lun, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define ipr_res_err(ioa_cfg, res, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if ((res).bus >= IPR_MAX_NUM_BUSES) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ipr_err(fmt": %d:%d:%d:%d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) (res).bus, (res).target, (res).lun); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define ipr_hcam_err(hostrcb, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (ipr_is_device(hostrcb)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if ((hostrcb)->ioa_cfg->sis64) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) printk(KERN_ERR IPR_NAME ": %s: " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ipr_format_res_path(hostrcb->ioa_cfg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) hostrcb->hcam.u.error64.fd_res_path, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) hostrcb->rp_buffer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) sizeof(hostrcb->rp_buffer)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ipr_ra_err((hostrcb)->ioa_cfg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) (hostrcb)->hcam.u.error.fd_res_addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) fmt, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) __FILE__, __func__, __LINE__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define ipr_err_separator \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ipr_err("----------------------------------------------------------\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * Inlines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * ipr_is_ioa_resource - Determine if a resource is the IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * 1 if IOA / 0 if not IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return res->type == IPR_RES_TYPE_IOAFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * 1 if AF DASD / 0 if not AF DASD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return res->type == IPR_RES_TYPE_AF_DASD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * ipr_is_vset_device - Determine if a resource is a VSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * 1 if VSET / 0 if not VSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return res->type == IPR_RES_TYPE_VOLUME_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * ipr_is_gscsi - Determine if a resource is a generic scsi resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * 1 if GSCSI / 0 if not GSCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return res->type == IPR_RES_TYPE_GENERIC_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * 1 if SCSI disk / 0 if not SCSI disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (ipr_is_af_dasd_device(res) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * ipr_is_gata - Determine if a resource is a generic ATA resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * 1 if GATA / 0 if not GATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static inline int ipr_is_gata(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return res->type == IPR_RES_TYPE_GENERIC_ATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) * ipr_is_naca_model - Determine if a resource is using NACA queueing model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) * @res: resource entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * 1 if NACA queueing model / 0 if not NACA queueing model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * ipr_is_device - Determine if the hostrcb structure is related to a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * @hostrcb: host resource control blocks struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) * 1 if AF / 0 if not AF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct ipr_res_addr *res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) u8 *res_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (hostrcb->ioa_cfg->sis64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) res_path[0] == 0x81) && res_path[2] != 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) res_addr = &hostrcb->hcam.u.error.fd_res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) * @sdt_word: SDT address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * 1 if format 2 / 0 if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static inline int ipr_sdt_is_fmt2(u32 sdt_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) switch (bar_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) case IPR_SDT_FMT2_BAR0_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) case IPR_SDT_FMT2_BAR1_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) case IPR_SDT_FMT2_BAR2_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case IPR_SDT_FMT2_BAR3_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) case IPR_SDT_FMT2_BAR4_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) case IPR_SDT_FMT2_BAR5_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) case IPR_SDT_FMT2_EXP_ROM_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #ifndef writeq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static inline void writeq(u64 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) writel(((u32) (val >> 32)), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) writel(((u32) (val)), (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #endif /* _IPR_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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