^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Initio 9100 device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994-1998 Initio Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Cleanups (c) Copyright 2007 Red Hat <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the Free Software Foundation; either version 2, or (at your option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this program; see the file COPYING. If not, write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TOTAL_SG_ENTRY 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX_SUPPORTED_ADAPTERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_TARGETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned short base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned short vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } i91u_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Tulip Configuration Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TUL_PVID 0x00 /* Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TUL_PDID 0x02 /* Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TUL_PCMD 0x04 /* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TUL_PSTUS 0x06 /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TUL_PRID 0x08 /* Revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TUL_PPI 0x09 /* Programming interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TUL_PSC 0x0A /* Sub Class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TUL_PBC 0x0B /* Base Class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TUL_PCLS 0x0C /* Cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TUL_PLTR 0x0D /* Latency timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TUL_PHDT 0x0E /* Header type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TUL_PBIST 0x0F /* BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TUL_PBAD 0x10 /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TUL_PBAD1 0x14 /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TUL_PBAD2 0x18 /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TUL_PBAD3 0x1C /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TUL_PBAD4 0x20 /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TUL_PBAD5 0x24 /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TUL_PRSVD 0x28 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TUL_PRSVD1 0x2C /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TUL_PRAD 0x30 /* Expansion ROM base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TUL_PRSVD2 0x34 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TUL_PRSVD3 0x38 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TUL_PINTL 0x3C /* Interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TUL_PINTP 0x3D /* Interrupt pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TUL_PIGNT 0x3E /* MIN_GNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TUL_PMGNT 0x3F /* MAX_GNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Jasmin Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TUL_GINTS 0x50 /* Global Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TUL_GCTRL 0x54 /* Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TUL_GCTRL_EEPROM_BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TUL_GCTRL1 0x55 /* Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TUL_DMACFG 0x5B /* DMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TUL_NVRAM 0x5D /* Non-volatile RAM port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TUL_SInt 0x84 /* 04 R Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TUL_SCtrl0 0x85 /* 05 W Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TUL_SStatus0 0x85 /* 05 R Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TUL_SCtrl1 0x86 /* 06 W Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TUL_SStatus1 0x86 /* 06 R Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TUL_SConfig 0x87 /* 07 W Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TUL_SStatus2 0x87 /* 07 R Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TUL_SOffset 0x88 /* 08 R Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TUL_SScsiId 0x89 /* 09 W SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TUL_SIdent 0x8A /* 0A R Identify Message Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TUL_SAvail 0x8A /* 0A R Available Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TUL_SData 0x8B /* 0B R/W SCSI data in/out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TUL_SFifo 0x8C /* 0C R/W FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TUL_SCmd 0x91 /* 11 R/W Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TUL_STest0 0x92 /* 12 R/W Test0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TUL_STest1 0x93 /* 13 R/W Test1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TUL_SCFG1 0x94 /* 14 R/W Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TUL_XCntH 0xD0 /*DMA Transfer Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TUL_XCmd 0xD8 /*DMA Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TUL_Int 0xDC /*Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TUL_XStatus 0xDD /*DMA status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TUL_Mask 0xE0 /*Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TUL_XCtrl 0xE4 /*DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TUL_XFifo 0xE8 /*DMA FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TUL_WCtrl 0xF7 /*Bus master wait state control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TUL_DCtrl 0xFB /*DMA delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* bit definition for Command register of Configuration Space Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BUSMS 0x04 /* BUS MASTER Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IOSPA 0x01 /* IO Space Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Command Codes of Tulip SCSI Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TSC_EN_RESEL 0x80 /* Enable Reselection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TSC_CMD_COMP 0x84 /* Command Complete Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TSC_SEL 0x01 /* Select Without ATN Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Information out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Information in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Information out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Information in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Information in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TSC_MSG_ACCEPT 0x0F /* Message Accept */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* bit definition for Tulip SCSI Control 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TSC_RST_SEQ 0x20 /* Reset sequence counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TSC_ABT_CMD 0x04 /* Abort command (sequence) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TSC_RST_BUS 0x01 /* Reset SCSI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* bit definition for Tulip SCSI Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TSC_EN_SCAM 0x80 /* Enable SCAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TSC_TIMER 0x40 /* Select timeout unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TSC_PWDN 0x10 /* Power down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TSC_WIDE_CPU 0x08 /* Wide CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TSC_HW_RESELECT 0x04 /* Enable HW reselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* bit definition for Tulip SCSI Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TSC_EN_LATCH 0x80 /* Enable phase latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TSC_INITIATOR 0x40 /* Initiator mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* bit definition for Tulip SCSI signal Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TSC_RST_ACK 0x00 /* Release ACK signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TSC_RST_ATN 0x00 /* Release ATN signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TSC_RST_BSY 0x00 /* Release BSY signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TSC_SET_ACK 0x40 /* ACK signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TSC_SET_ATN 0x08 /* ATN signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TSC_REQI 0x80 /* REQ signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TSC_ACKI 0x40 /* ACK signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TSC_BSYI 0x20 /* BSY signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TSC_SELI 0x10 /* SEL signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TSC_ATNI 0x08 /* ATN signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TSC_MSGI 0x04 /* MSG signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TSC_CDI 0x02 /* C/D signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TSC_IOI 0x01 /* I/O signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* bit definition for Tulip SCSI Status 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TSS_INT_PENDING 0x80 /* Interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TSS_XFER_CNT 0x20 /* Transfer counter zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TSS_FIFO_EMPTY 0x10 /* FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TSS_PAR_ERROR 0x08 /* SCSI parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TSS_PH_MASK 0x07 /* SCSI phase mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* bit definition for Tulip SCSI Status 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TSS_STATUS_RCV 0x08 /* Status received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TSS_MSG_SEND 0x40 /* Message sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TSS_CMD_PH_CMP 0x20 /* command phase done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TSS_DATA_PH_CMP 0x10 /* Data phase done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TSS_STATUS_SEND 0x08 /* Status sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TSS_XFER_CMP 0x04 /* Transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TSS_SEL_CMP 0x02 /* Selection completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TSS_ARB_CMP 0x01 /* Arbitration completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* bit definition for Tulip SCSI Status 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TSS_CMD_ABTED 0x80 /* Command aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TSS_OFFSET_0 0x40 /* Offset counter zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TSS_FIFO_FULL 0x20 /* FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TSS_BUSY_RLS 0x08 /* Busy release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TSS_PH_MISMATCH 0x04 /* Phase mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* bit definition for Tulip SCSI Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TSS_RESEL_INT 0x80 /* Reselected interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TSS_BUS_SERV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TSS_DISC_INT 0x08 /* Disconnected interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TSS_SEL_INT 0x04 /* Select interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TSS_SCAM_SEL 0x02 /* SCAM selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TSS_FUNC_COMP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* SCSI Phase Codes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DATA_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DATA_IN 1 /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CMD_OUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define STATUS_IN 3 /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MSG_OUT 6 /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MSG_IN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Command Codes of Tulip xfer Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TAX_X_FORC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TAX_X_ABT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TAX_X_CLR_FIFO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TAX_X_IN 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TAX_X_OUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TAX_SG_IN 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TAX_SG_OUT 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Tulip Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define XCMP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define FCMP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define XABT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define XERR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SCMP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IPEND 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Tulip DMA Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define XPEND 0x01 /* Transfer pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define FEMPTY 0x02 /* FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* bit definition for TUL_GCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define EXTSG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define EXTAD 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SEG4K 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define EEPRG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MRMUL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* bit definition for TUL_NVRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SE2CS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SE2CLK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SE2DO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SE2DI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Scatter-Gather Element Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 data; /* Data Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 len; /* Data Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SCSI Control Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct scsi_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct scsi_ctrl_blk *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 status; /*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 next_state; /*5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 mode; /*6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 msgin; /*7 SCB_Res0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u16 sgidx; /*8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 sgmax; /*A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #ifdef ALPHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 reserved[2]; /*C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 reserved[3]; /*C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 xferlen; /*18 Current xfer len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 totxlen; /*1C Total xfer len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 paddr; /*20 SCB phy. Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 opcode; /*24 SCB command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 flags; /*25 SCB Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 target; /*26 Target Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 lun; /*27 Lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 bufptr; /*28 Data Buffer Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 buflen; /*2C Data Allocation Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 sglen; /*30 SG list # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 senselen; /*31 Sense Allocation Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 hastat; /*32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 tastat; /*33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 cdblen; /*34 CDB Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 ident; /*35 Identify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 tagmsg; /*36 Tag Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 tagid; /*37 Queue Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 cdb[12]; /*38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 sgpaddr; /*44 SG List/Sense Buf phy. Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 senseptr; /*48 Sense data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void (*post) (u8 *, u8 *); /*4C POST routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct scsi_cmnd *srb; /*50 SRB Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct sg_entry sglist[TOTAL_SG_ENTRY]; /*54 Start of SG list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Bit Definition for status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SCB_RENT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SCB_PEND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SCB_CONTIG 0x04 /* Contingent Allegiance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SCB_SELECT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SCB_BUSY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SCB_DONE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Opcodes for opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ExecSCSI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define BusDevRst 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AbortCmd 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Bit Definition for mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SCM_RSENS 0x01 /* request sense mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Bit Definition for flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SCF_DONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SCF_POST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SCF_SENSE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SCF_DIR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SCF_NO_DCHK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SCF_DIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SCF_DOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SCF_NO_XF 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SCF_WR_VF 0x20 /* Write verify turn on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SCF_POLL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SCF_SG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Error Codes for SCB_HaStat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define HOST_SEL_TOUT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HOST_DO_DU 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HOST_BUS_FREE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HOST_BAD_PHAS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HOST_INV_CMD 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define HOST_ABORTED 0x1A /* 07/21/98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HOST_SCSI_RST 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HOST_DEV_RST 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Error Codes for SCB_TaStat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TARGET_CHKCOND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define TARGET_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define INI_QUEUE_FULL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* SCSI MESSAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MSG_COMP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MSG_EXTEND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MSG_SDP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MSG_RESTORE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MSG_DISC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MSG_IDE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MSG_ABORT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MSG_REJ 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MSG_NOP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MSG_PARITY 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MSG_LINK_COMP 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MSG_LINK_FLAG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MSG_DEVRST 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MSG_ABORT_TAG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MSG_STAG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MSG_HTAG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MSG_OTAG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MSG_IGNOREWIDE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MSG_IDENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) Target Device Control Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) **********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct target_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 js_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 sconfig0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u16 drv_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) Target Device Control Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) **********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Bit Definition for TCF_Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define TCF_SCSI_RATE 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define TCF_EN_DISC 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define TCF_NO_SYNC_NEGO 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define TCF_NO_WDTR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define TCF_EN_255 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TCF_EN_START 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TCF_WDTR_DONE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TCF_SYNC_DONE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TCF_BUSY 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Bit Definition for TCF_DrvFlags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define TCF_DRV_EN_TAG 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define TCF_DRV_255_63 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) Host Adapter Control Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct initio_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 addr; /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 bios_addr; /* 02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 irq; /* 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 scsi_id; /* 05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 max_tar; /* 06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 num_scbs; /* 07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 flags; /* 08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 index; /* 09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 ha_id; /* 0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 config; /* 0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u16 idmask; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 semaph; /* 0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 phase; /* 0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 jsstatus0; /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 jsint; /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 jsstatus1; /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 sconf1; /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 msg[8]; /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct scsi_ctrl_blk *next_avail; /* 1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct scsi_ctrl_blk *scb; /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct scsi_ctrl_blk *scb_end; /* 24 */ /*UNUSED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct scsi_ctrl_blk *next_pending; /* 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct scsi_ctrl_blk *next_contig; /* 2C */ /*UNUSED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct scsi_ctrl_blk *active; /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct target_control *active_tc; /* 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct scsi_ctrl_blk *first_avail; /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct scsi_ctrl_blk *last_avail; /* 3C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct scsi_ctrl_blk *first_pending; /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct scsi_ctrl_blk *last_pending; /* 44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct scsi_ctrl_blk *first_busy; /* 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct scsi_ctrl_blk *last_busy; /* 4C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct scsi_ctrl_blk *first_done; /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct scsi_ctrl_blk *last_done; /* 54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 max_tags[16]; /* 58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 act_tags[16]; /* 68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct target_control targets[MAX_TARGETS]; /* 78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spinlock_t avail_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spinlock_t semaph_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Bit Definition for HCB_Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define HCC_SCSI_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define HCC_EN_PAR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define HCC_ACT_TERM1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define HCC_ACT_TERM2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define HCC_AUTO_TERM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define HCC_EN_PWR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Bit Definition for HCB_Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define HCF_EXPECT_DISC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define HCF_EXPECT_SELECT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HCF_EXPECT_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HCF_EXPECT_DONE_DISC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) Serial EEProm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) typedef struct _NVRAM_SCSI { /* SCSI channel configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 NVM_ChConfig1; /* 0Dh -> Channel config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 NVM_ChConfig2; /* 0Eh -> Channel config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* SCSI target configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 NVM_Targ0Config; /* 10h -> Target 0 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 NVM_Targ1Config; /* 11h -> Target 1 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 NVM_Targ2Config; /* 12h -> Target 2 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 NVM_Targ3Config; /* 13h -> Target 3 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 NVM_Targ4Config; /* 14h -> Target 4 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 NVM_Targ5Config; /* 15h -> Target 5 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 NVM_Targ6Config; /* 16h -> Target 6 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u8 NVM_Targ7Config; /* 17h -> Target 7 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u8 NVM_Targ8Config; /* 18h -> Target 8 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 NVM_Targ9Config; /* 19h -> Target 9 configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 NVM_TargAConfig; /* 1Ah -> Target A configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 NVM_TargBConfig; /* 1Bh -> Target B configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 NVM_TargCConfig; /* 1Ch -> Target C configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 NVM_TargDConfig; /* 1Dh -> Target D configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 NVM_TargEConfig; /* 1Eh -> Target E configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 NVM_TargFConfig; /* 1Fh -> Target F configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } NVRAM_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) typedef struct _NVRAM {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*----------header ---------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 NVM_Signature; /* 0,1: Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 NVM_Size; /* 2: Size of data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 NVM_Revision; /* 3: Revision of data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* ----Host Adapter Structure ---- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 NVM_ModelByte0; /* 4: Model number (byte 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u8 NVM_ModelByte1; /* 5: Model number (byte 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 NVM_ModelInfo; /* 6: Model information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 NVM_NumOfCh; /* 7: Number of SCSI channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u8 NVM_BIOSConfig1; /* 8: BIOS configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u8 NVM_BIOSConfig2; /* 9: BIOS configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 NVM_HAConfig1; /* A: Hoat adapter configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 NVM_HAConfig2; /* B: Hoat adapter configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) NVRAM_SCSI NVM_SCSIInfo[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 NVM_reserved[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* ---------- CheckSum ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u16 NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } NVRAM, *PNVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Bios Configuration for nvram->BIOSConfig1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define NBC1_ENABLE 0x01 /* BIOS enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define NBC1_8DRIVE 0x02 /* Support more than 2 drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define NBC1_REMOVABLE 0x04 /* Support removable drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define NBC1_INT19 0x08 /* Intercept int 19h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define NBC1_LUNSUPPORT 0x40 /* Support LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* HA Configuration Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define NHC1_BOOTIDMASK 0x0F /* Boot ID number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define NHC1_LUNMASK 0x70 /* Boot LUN number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define NHC1_CHANMASK 0x80 /* Boot Channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Bit definition for nvram->SCSIconfig1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define NCC1_PARITYCHK 0x02 /* SCSI parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define NCC1_AUTOTERM 0x10 /* Enable auto terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define NCC1_PWRMGR 0x80 /* Enable power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Bit definition for SCSI Target configuration byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define NTC_SYNC 0x10 /* SYNC_NEGO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define NTC_NO_WDTR 0x20 /* SYNC_NEGO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define NTC_SPINUP 0x80 /* Start disk drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Default NVRam values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define INI_SIGNATURE 0xC925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define NBC1_DEFAULT (NBC1_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* SCSI related definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SCSICMD_RequestSense 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SCSI_ABORT_SNOOZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SCSI_ABORT_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define SCSI_ABORT_PENDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define SCSI_ABORT_BUSY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define SCSI_ABORT_NOT_RUNNING 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define SCSI_ABORT_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define SCSI_RESET_SNOOZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define SCSI_RESET_PUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define SCSI_RESET_SUCCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SCSI_RESET_PENDING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SCSI_RESET_WAKEUP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SCSI_RESET_NOT_RUNNING 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SCSI_RESET_ERROR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SCSI_RESET_SYNCHRONOUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SCSI_RESET_ASYNCHRONOUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SCSI_RESET_SUGGEST_BUS_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SCSI_RESET_SUGGEST_HOST_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SCSI_RESET_BUS_RESET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SCSI_RESET_HOST_RESET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SCSI_RESET_ACTION 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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