^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Disk Array driver for HP Smart Array SAS controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2016 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014-2015 PMC-Sierra, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * NON INFRINGEMENT. See the GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef HPSA_CMD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HPSA_CMD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* general boundary defintions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SENSEINFOBYTES 32 /* may vary between hbas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HPSA_SG_CHAIN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HPSA_SG_LAST 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAXREPLYQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Command Status value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMD_SUCCESS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMD_TARGET_STATUS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMD_DATA_UNDERRUN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMD_DATA_OVERRUN 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMD_INVALID 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMD_PROTOCOL_ERR 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMD_HARDWARE_ERR 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMD_CONNECTION_LOST 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMD_ABORTED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMD_ABORT_FAILED 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_UNSOLICITED_ABORT 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMD_TIMEOUT 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_UNABORTABLE 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMD_TMF_STATUS 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMD_IOACCEL_DISABLED 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD_CTLR_LOCKUP 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * it is a value defined by the driver that commands can be marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * with when a controller lockup has been detected by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* TMF function status values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CISS_TMF_COMPLETE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CISS_TMF_INVALID_FRAME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CISS_TMF_NOT_SUPPORTED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CISS_TMF_FAILED 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CISS_TMF_SUCCESS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CISS_TMF_WRONG_LUN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CISS_TMF_OVERLAPPED_TAG 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Unit Attentions ASC's as defined for the MSA2012sa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define POWER_OR_RESET 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STATE_CHANGED 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UNIT_ATTENTION_CLEARED 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LUN_FAILED 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REPORT_LUNS_CHANGED 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Unit Attentions ASCQ's as defined for the MSA2012sa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* These ASCQ's defined for ASC = POWER_OR_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define POWER_ON_RESET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define POWER_ON_REBOOT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCSI_BUS_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSA_TARGET_RESET 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CONTROLLER_FAILOVER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TRANSCEIVER_SE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TRANSCEIVER_LVD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* These ASCQ's defined for ASC = STATE_CHANGED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RESERVATION_PREEMPTED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ASYM_ACCESS_CHANGED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LUN_CAPACITY_CHANGED 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XFER_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XFER_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XFER_READ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XFER_RSVD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* task attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ATTR_UNTAGGED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ATTR_SIMPLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ATTR_HEADOFQUEUE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ATTR_ORDERED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ATTR_ACA 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* cdb type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TYPE_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TYPE_MSG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Message Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HPSA_TASK_MANAGEMENT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HPSA_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HPSA_SCAN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HPSA_NOOP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HPSA_CTLR_RESET_TYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HPSA_BUS_RESET_TYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HPSA_TARGET_RESET_TYPE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HPSA_LUN_RESET_TYPE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HPSA_NEXUS_RESET_TYPE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Task Management Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HPSA_TMF_ABORT_TASK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HPSA_TMF_ABORT_TASK_SET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HPSA_TMF_CLEAR_ACA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HPSA_TMF_CLEAR_TASK_SET 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HPSA_TMF_QUERY_TASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HPSA_TMF_QUERY_TASK_SET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* config space register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CFG_VENDORID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CFG_DEVICEID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CFG_I2OBAR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CFG_MEM1BAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* i2o space register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I2O_IBDB_SET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I2O_IBDB_CLEAR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I2O_INT_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define I2O_INT_MASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define I2O_IBPOST_Q 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define I2O_OBPOST_Q 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I2O_DMA1_CFG 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Configuration Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CFGTBL_ChangeReq 0x00000001l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CFGTBL_AccCmds 0x00000001l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DOORBELL_CTLR_RESET 0x00000004l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DOORBELL_CTLR_RESET2 0x00000020l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DOORBELL_CLEAR_EVENTS 0x00000040l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DOORBELL_GENERATE_CHKPT 0x00000080l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CFGTBL_Trans_Simple 0x00000002l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CFGTBL_Trans_Performant 0x00000004l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CFGTBL_Trans_io_accel1 0x00000080l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CFGTBL_Trans_io_accel2 0x00000100l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CFGTBL_Trans_use_short_tags 0x20000000l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CFGTBL_Trans_enable_directed_msix (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CFGTBL_BusType_Ultra2 0x00000001l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CFGTBL_BusType_Ultra3 0x00000002l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CFGTBL_BusType_Fibre1G 0x00000100l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CFGTBL_BusType_Fibre2G 0x00000200l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* VPD Inquiry types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HPSA_INQUIRY_FAILED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HPSA_VPD_SUPPORTED_PAGES 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HPSA_VPD_LV_DEVICE_ID 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HPSA_VPD_LV_STATUS 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HPSA_VPD_HEADER_SZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Logical volume states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HPSA_LV_OK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HPSA_LV_FAILED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HPSA_LV_NOT_AVAILABLE 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HPSA_LV_UNDERGOING_ERASE 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HPSA_LV_UNDERGOING_RPI 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HPSA_LV_PENDING_RPI 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HPSA_LV_ENCRYPTED_NO_KEY 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HPSA_LV_PENDING_ENCRYPTION 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct vals32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) union u64bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct vals32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* FIXME this is a per controller value (barf!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HPSA_MAX_LUN 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HPSA_MAX_PHYS_LUN 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MAX_EXT_TARGETS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SCSI-3 Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HPSA_INQUIRY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct InquiryData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 data_byte[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HPSA_REPORT_PHYS_EXTENDED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HPSA_CISS_READ 0xc0 /* CISS Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RAID_MAP_MAX_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct raid_map_disk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 ioaccel_handle; /**< Handle to access this disk via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * I/O accelerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 xor_mult[2]; /**< XOR multipliers for this position,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * valid for data disks only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct raid_map_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __le32 structure_size; /* Size of entire structure in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __le32 volume_blk_size; /* bytes / block in the volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le64 volume_blk_cnt; /* logical blocks on the volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 phys_blk_shift; /* Shift factor to convert between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * units of logical blocks and physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * disk blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 parity_rotation_shift; /* Shift factor to convert between units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * of logical stripes and physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * stripes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __le16 strip_size; /* blocks used on each disk / stripe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __le64 disk_starting_blk; /* First disk block used in volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __le16 data_disks_per_row; /* data disk entries / row in the map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le16 metadata_disks_per_row;/* mirror/parity disk entries / row
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * in the map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __le16 row_cnt; /* rows in each layout map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __le16 layout_map_count; /* layout maps (1 map per mirror/parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * group) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __le16 flags; /* Bit 0 set if encryption enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RAID_MAP_FLAG_ENCRYPT_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __le16 dekindex; /* Data encryption key index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 reserved[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct ReportLUNdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 LUNListLength[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 extended_response_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 LUN[HPSA_MAX_LUN][8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ext_report_lun_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 lunid[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MASKED_DEVICE(x) ((x)[3] & 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GET_BMIC_LEVEL_TWO_TARGET((lunid)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 wwid[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 lun_count; /* multi-lun device, how many luns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 redundant_paths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ReportExtendedLUNdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 LUNListLength[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 extended_response_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct SenseSubsystem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 reserved[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 portname[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 reserved1[1108];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* BMIC commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define BMIC_READ 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define BMIC_WRITE 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BMIC_CACHE_FLUSH 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BMIC_FLASH_FIRMWARE 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define BMIC_IDENTIFY_CONTROLLER 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define BMIC_SET_DIAG_OPTIONS 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BMIC_SENSE_DIAG_OPTIONS 0xF5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Command List Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) union SCSI3Addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 Dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 Bus:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 Mode:2; /* b00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } PeripDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 DevLSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 DevMSB:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 Mode:2; /* b01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } LogDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 Dev:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 Bus:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 Targ:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 Mode:2; /* b10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } LogUnit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct PhysDevAddr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 TargetId:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 Bus:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 Mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 2 level target device addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) union SCSI3Addr Target[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct LogDevAddr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 VolId:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 Mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) union LUNAddr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 LunAddrBytes[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) union SCSI3Addr SCSI3Lun[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct PhysDevAddr PhysDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct LogDevAddr LogDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct CommandListHeader {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 ReplyQueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 SGList;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __le16 SGTotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __le64 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) union LUNAddr LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct RequestBlock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 CDBLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * type_attr_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * type: low 3 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * attr: middle 3 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * dir: high 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 type_attr_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) (((a) & 0x07) << 3) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ((t) & 0x07))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define GET_TYPE(tad) ((tad) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define GET_DIR(tad) (((tad) >> 6) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u16 Timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 CDB[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct ErrDescriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __le64 Addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __le32 Len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct SGDescriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __le64 Addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __le32 Len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __le32 Ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) union MoreErrInfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 Reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 ErrorInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } Common_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 Reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 offense_size; /* size of offending entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 offense_num; /* byte # of offense 0-base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 offense_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } Invalid_Cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct ErrorInfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 ScsiStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 SenseLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u16 CommandStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 ResidualCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) union MoreErrInfo MoreErrInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 SenseInfo[SENSEINFOBYTES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Command types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CMD_IOCTL_PEND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CMD_SCSI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CMD_IOACCEL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CMD_IOACCEL2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IOACCEL2_TMF 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DIRECT_LOOKUP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define HPSA_ERROR_BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ctlr_info; /* defined in hpsa.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* The size of this structure needs to be divisible by 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * on all architectures. The low 4 bits of the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * are used as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * bit 0: to device, used to indicate "performant mode" command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * from device, indidcates error status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * bit 1-3: to device, indicates block fetch table entry for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * reducing DMA in fetching commands from host memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define COMMANDLIST_ALIGNMENT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct CommandList {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct CommandListHeader Header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct RequestBlock Request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct ErrDescriptor ErrDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* information associated with the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 busaddr; /* physical addr of this record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct ErrorInfo *err_info; /* pointer to the allocated mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct ctlr_info *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) long cmdindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct completion *waiting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct scsi_cmnd *scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * For commands using either of the two "ioaccel" paths to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * bypass the RAID stack and go directly to the physical disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * i/o is destined. We need to store that here because the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * may potentially encounter TASK SET FULL and need to be resubmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct hpsa_scsi_dev_t *phys_disk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int abort_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct hpsa_scsi_dev_t *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } __aligned(COMMANDLIST_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Max S/G elements in I/O accelerator command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IOACCEL1_MAXSGENTRIES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IOACCEL2_MAXSGENTRIES 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Structure for I/O accelerator (mode 1) commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Note that this structure must be 128-byte aligned in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct io_accel1_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) __le16 dev_handle; /* 0x00 - 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 reserved1; /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 function; /* 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 reserved2[8]; /* 0x04 - 0x0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 err_info; /* 0x0C - 0x0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 reserved3[2]; /* 0x10 - 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u8 err_info_len; /* 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 reserved4; /* 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 sgl_offset; /* 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 reserved5[7]; /* 0x15 - 0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __le32 transfer_len; /* 0x1C - 0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 reserved6[4]; /* 0x20 - 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __le16 io_flags; /* 0x24 - 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 reserved7[14]; /* 0x26 - 0x33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 LUN[8]; /* 0x34 - 0x3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __le32 control; /* 0x3C - 0x3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 CDB[16]; /* 0x40 - 0x4F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 reserved8[16]; /* 0x50 - 0x5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __le16 host_context_flags; /* 0x60 - 0x61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __le16 timeout_sec; /* 0x62 - 0x63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 ReplyQueue; /* 0x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 reserved9[3]; /* 0x65 - 0x67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le64 tag; /* 0x68 - 0x6F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __le64 host_addr; /* 0x70 - 0x77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 CISS_LUN[8]; /* 0x78 - 0x7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define IOACCEL1_FUNCTION_SCSIIO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define IOACCEL1_SGLOFFSET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define IOACCEL1_IOFLAGS_IO_REQ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define IOACCEL1_CONTROL_NODATAXFER 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define IOACCEL1_CONTROL_DATA_OUT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define IOACCEL1_CONTROL_DATA_IN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define IOACCEL1_CONTROL_ACA 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct ioaccel2_sg_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __le64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 chain_indicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IOACCEL2_CHAIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IOACCEL2_LAST_SG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * SCSI Response Format structure for IO Accelerator Mode 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct io_accel2_scsi_response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 IU_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IOACCEL2_IU_TYPE_SRF 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 req_id[4]; /* request identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 reserved2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 serv_response; /* service response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 status; /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define IOACCEL2_STATUS_SR_IO_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IOACCEL2_STATUS_SR_UNDERRUN 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IOACCEL2_STATUS_SR_OVERRUN 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u8 data_present; /* low 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IOACCEL2_NO_DATAPRESENT 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IOACCEL2_RESPONSE_DATAPRESENT 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IOACCEL2_SENSE_DATA_PRESENT 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IOACCEL2_RESERVED 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 sense_data_len; /* sense/response data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 resid_cnt[4]; /* residual count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 sense_data_buff[32]; /* sense/response data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Structure for I/O accelerator (mode 2 or m2) commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Note that this structure must be 128-byte aligned in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct io_accel2_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 IU_type; /* IU Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 direction; /* direction, memtype, and encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* 0b=PCIe, 1b=DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* 0=off, 1=on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 reply_queue; /* Reply Queue ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 reserved1; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __le32 scsi_nexus; /* Device Handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __le32 Tag; /* cciss tag, lower 4 bytes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 cdb[16]; /* SCSI Command Descriptor Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 cciss_lun[8]; /* 8 byte SCSI address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __le32 data_len; /* Total bytes to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 cmd_priority_task_attr; /* priority and task attrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define IOACCEL2_PRIORITY_MASK 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define IOACCEL2_ATTR_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 sg_count; /* Number of sg elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __le16 dekindex; /* Data encryption key index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __le64 err_ptr; /* Error Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) __le32 err_len; /* Error Length*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct io_accel2_scsi_response error_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * defines for Mode 2 command struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * FIXME: this can't be all I need mfm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define IOACCEL2_IU_TYPE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define IOACCEL2_IU_TMF_TYPE 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define IOACCEL2_DIR_NO_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define IOACCEL2_DIR_DATA_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define IOACCEL2_DIR_DATA_OUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define IOACCEL2_TMF_ABORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * SCSI Task Management Request format for Accelerator Mode 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct hpsa_tmf_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 iu_type; /* Information Unit Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 reply_queue; /* Reply Queue ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 tmf; /* Task Management Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 reserved1; /* byte 3 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) __le32 it_nexus; /* SCSI I-T Nexus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 lun_id[8]; /* LUN ID for TMF request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) __le64 tag; /* cciss tag associated w/ request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __le64 error_ptr; /* Error Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __le32 error_len; /* Error Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Configuration Table Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct HostWrite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __le32 TransportRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __le32 command_pool_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __le32 CoalIntDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __le32 CoalIntCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SIMPLE_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define PERFORMANT_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define MEMQ_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define IOACCEL_MODE_1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DRIVER_SUPPORT_UA_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct CfgTable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 Signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __le32 SpecValence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) __le32 TransportSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) __le32 TransportActive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct HostWrite HostWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) __le32 CmdsOutMax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __le32 BusTypes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le32 TransMethodOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 ServerName[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __le32 HeartBeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __le32 driver_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ENABLE_SCSI_PREFETCH 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define ENABLE_UNIT_ATTN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __le32 MaxScatterGatherElements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __le32 MaxLogicalUnits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __le32 MaxPhysicalDevices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __le32 MaxPhysicalDrivesPerLogicalUnit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) __le32 MaxPerformantModeCommands;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __le32 MaxBlockFetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) __le32 PowerConservationSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) __le32 PowerConservationEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) __le32 TMFSupportFlags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 TMFTagMask[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 reserved[0x78 - 0x70];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __le32 misc_fw_support; /* offset 0x78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MISC_FW_DOORBELL_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MISC_FW_DOORBELL_RESET2 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define MISC_FW_RAID_OFFLOAD_BASIC 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define MISC_FW_EVENT_NOTIFY 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 driver_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __le32 max_cached_write_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 driver_scratchpad[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __le32 max_error_info_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) __le32 io_accel_max_embedded_sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __le32 io_accel_request_size_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __le32 event_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __le32 clear_event_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define NUM_BLOCKFETCH_ENTRIES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct TransTable_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __le32 RepQSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __le32 RepQCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __le32 RepQCtrAddrLow32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __le32 RepQCtrAddrHigh32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MAX_REPLY_QUEUES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct vals32 RepQAddr[MAX_REPLY_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct hpsa_pci_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned char bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned char dev_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned short domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 board_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct bmic_identify_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u8 configured_logical_drive_count; /* offset 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u8 pad1[153];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __le16 extended_logical_unit_count; /* offset 154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 pad2[136];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 controller_mode; /* offset 292 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 pad3[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct bmic_identify_physical_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 scsi_bus; /* SCSI Bus number on controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u8 scsi_id; /* SCSI ID on this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __le16 block_size; /* sector size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __le32 total_blocks; /* number for sectors on drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __le32 reserved_blocks; /* controller reserved (RIS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u8 model[40]; /* Physical Drive Model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u8 serial_number[40]; /* Drive Serial Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 firmware_revision[8]; /* drive firmware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u8 compaq_drive_stamp; /* 0 means drive not stamped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 last_failure_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define BMIC_LAST_FAILURE_TIMEOUT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define BMIC_LAST_FAILURE_NOT_READY 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u8 more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u8 scsi_lun; /* SCSI LUN for phys drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 yet_more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 even_more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 phys_connector[2]; /* connector number on controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u8 phys_box_on_bus; /* phys enclosure this drive resides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u8 phys_bay_in_box; /* phys drv bay this drive resides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __le32 rpm; /* Drive rotational speed in rpm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u8 device_type; /* type of drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define BMIC_DEVICE_TYPE_CONTROLLER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u8 sata_version; /* only valid when drive_type is SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) __le64 big_total_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __le64 ris_starting_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) __le32 ris_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u8 wwid[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u8 controller_phy_map[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __le16 phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u8 phy_connected_dev_type[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u8 phy_to_drive_bay_num[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __le16 phy_to_attached_dev_index[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u8 box_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __le16 extra_physical_drive_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) (idphydrv->extra_physical_drive_flags & (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u8 negotiated_link_rate[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u8 phy_to_phy_map[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u8 redundant_path_present_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 redundant_path_failure_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u8 active_path_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) __le16 alternate_paths_phys_connector[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 alternate_paths_phys_box_on_port[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 multi_lun_device_lun_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u8 minimum_good_fw_revision[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u8 unique_inquiry_bytes[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 current_temperature_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 temperature_threshold_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 max_temperature_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) __le16 current_queue_depth_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 reserved_switch_stuff[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __le16 power_on_hours; /* valid only if gas gauge supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __le16 percent_endurance_used; /* valid only if gas gauge supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ((idphydrv->percent_endurance_used & 0x80) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (idphydrv->percent_endurance_used > 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 drive_authentication;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (idphydrv->drive_authentication == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 smart_carrier_authentication;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) (idphydrv->smart_carrier_authentication != 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (idphydrv->smart_carrier_authentication == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u8 smart_carrier_app_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 smart_carrier_bootloader_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 sanitize_support_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 drive_key_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 encryption_key_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __le32 misc_drive_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __le16 dek_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) __le16 hba_drive_encryption_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __le16 max_overwrite_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __le16 max_block_erase_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __le16 max_crypto_erase_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 device_connector_info[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 connector_name[8][8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 page_83_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 max_link_rate[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 neg_phys_link_rate[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 box_conn_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) } __attribute((aligned(512)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct bmic_sense_subsystem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 primary_slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 chasis_serial_number[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 primary_world_wide_id[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u8 primary_array_serial_number[32]; /* NULL terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 primary_cache_serial_number[32]; /* NULL terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u8 reserved_2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u8 secondary_array_serial_number[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u8 secondary_cache_serial_number[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u8 pad[332];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct bmic_sense_storage_box_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u8 reserved[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u8 inquiry_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 reserved_1[68];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 phys_box_on_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u8 reserved_2[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u16 connection_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u8 reserver_3[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u8 phys_connector[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 reserved_4[296];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #endif /* HPSA_CMD_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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