Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef GVP11_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /* $Id: gvp11.h,v 1.4 1997/01/19 23:07:12 davem Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Header file for the GVP Series II SCSI controller for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Written and (C) 1993, Ralf Baechle, see gvp11.c for more info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * based on a2091.h (C) 1993 by Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef CMD_PER_LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CMD_PER_LUN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef CAN_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CAN_QUEUE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * if the transfer address ANDed with this results in a non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * result, then we can't use DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GVP11_XFER_MASK		(0xff000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct gvp11_scsiregs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		 unsigned char	pad1[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	volatile unsigned short	CNTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		 unsigned char	pad2[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	volatile unsigned char	SASR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		 unsigned char	pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	volatile unsigned char	SCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		 unsigned char	pad4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	volatile unsigned short	BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		 unsigned char	pad5[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	volatile unsigned long	ACR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	volatile unsigned short	secret1; /* store 0 here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	volatile unsigned short	ST_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	volatile unsigned short	SP_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	volatile unsigned short	secret2; /* store 1 here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	volatile unsigned short	secret3; /* store 15 here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* bits in CNTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GVP11_DMAC_BUSY		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GVP11_DMAC_INT_PENDING	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GVP11_DMAC_INT_ENABLE	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GVP11_DMAC_DIR_WRITE	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif /* GVP11_H */