^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _GDTH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _GDTH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * See gdth.c for further informations and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * below for supported controller types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * <achim_leubner@adaptec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifndef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* defines, macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* driver version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GDTH_VERSION_STR "3.05"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GDTH_VERSION 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GDTH_SUBVERSION 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* protocol version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PROTOCOL_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* OEM IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OEM_ID_ICP 0x941c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OEM_ID_INTEL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* controller classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GDT_PCI 0x03 /* PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GDT_PCINEW 0x04 /* new PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GDT_PCIMPR 0x05 /* PCI MPR controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* GDT_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* GDT_PCINEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* GDT_PCINEW, wide/ultra SCSI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* GDT_PCINEW, wide SCSI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* GDT_MPR, RP series, wide/ultra SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* GDT_MPR, RP series, narrow/ultra SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* GDT_MPR, RD series, wide/ultra SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* GDT_MPR, RD series, narrow/ultra SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* GDT_MPR, RD series, wide/ultra2 SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GDT6618RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GDT6628RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GDT7618RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GDT7628RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* GDT_MPR, RD series, Fibre Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* GDT_MPR, last device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* new GDT Rx Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* new(2) GDT Rx Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifndef PCI_DEVICE_ID_INTEL_SRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Intel Storage RAID Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCI_DEVICE_ID_INTEL_SRC 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Intel Storage RAID Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GDTH_MAXCMDS 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GDTH_MAX_RAW 2 /* max. cmds per raw device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MAXOFFSETS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MAXHA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MAXID 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MAXLUN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAXBUS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MAX_EVENTS 100 /* event buffer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MAX_RES_ARGS 40 /* device reservation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) must be a multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MAXCYLS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HEADS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SECS 32 /* mapping 64*32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MEDHEADS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MEDSECS 63 /* mapping 127*63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BIGHEADS 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BIGSECS 63 /* mapping 255*63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* special command ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define UNUSED_CMND ((struct scsi_cmnd *)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define INTERNAL_CMND ((struct scsi_cmnd *)-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SCREEN_CMND ((struct scsi_cmnd *)-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* controller services */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SCSIRAWSERVICE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CACHESERVICE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SCREENSERVICE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* screenservice defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MSG_INV_HANDLE -1 /* special message handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MSGLEN 16 /* size of message text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MSG_SIZE 34 /* size of message structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MSG_REQUEST 0 /* async. event: message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* DPMEM constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DPMEM_MAGIC 0xC0FFEE11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IC_HEADER_BYTES 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IC_QUEUE_BYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* cluster_type constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLUSTER_DRIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLUSTER_MOUNTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLUSTER_RESERVED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* commands for all services, cache service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GDT_INIT 0 /* service initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GDT_READ 1 /* read command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GDT_WRITE 2 /* write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GDT_INFO 3 /* information about devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GDT_FLUSH 4 /* flush dirty cache buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GDT_IOCTL 5 /* ioctl command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GDT_DEVTYPE 9 /* additional information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GDT_MOUNT 10 /* mount cache device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GDT_UNMOUNT 11 /* unmount cache device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GDT_GET_FEAT 13 /* get features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GDT_WRITE_THR 16 /* write through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GDT_READ_THR 17 /* read through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GDT_EXT_INFO 18 /* extended info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GDT_RESET 19 /* controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GDT_RESERVE_DRV 20 /* reserve host drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GDT_RELEASE_DRV 21 /* release host drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GDT_CLUST_INFO 22 /* cluster info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GDT_CLUST_RESET 24 /* releases the cluster drives*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GDT_FREEZE_IO 25 /* freezes all IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GDT_X_INFO 30 /* ext. info for drives>2TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* raw service commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GDT_RESERVE 14 /* reserve dev. to raw serv. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GDT_RELEASE 15 /* release device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GDT_RESERVE_ALL 16 /* reserve all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GDT_RELEASE_ALL 17 /* release all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GDT_RESET_BUS 18 /* reset bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GDT_SCAN_START 19 /* start device scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GDT_SCAN_END 20 /* stop device scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* screen service commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GDT_REALTIME 3 /* realtime clock to screens. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* IOCTL command defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SCSI_DR_INFO 0x00 /* SCSI drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SCSI_DR_LIST 0x06 /* SCSI drive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IOCHAN_DESC 0x5d /* description of IO channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ARRAY_INFO 0x12 /* array drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ARRAY_DRV_LIST 0x0f /* array drive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CACHE_DRV_CNT 0x01 /* cache drive count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CACHE_DRV_LIST 0x02 /* cache drive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CACHE_INFO 0x04 /* cache info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CACHE_CONFIG 0x05 /* cache configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CACHE_DRV_INFO 0x07 /* cache drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BOARD_FEATURES 0x15 /* controller features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BOARD_INFO 0x28 /* controller info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GET_PERF_MODES 0x83 /* get mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HOST_GET 0x10001L /* get host drive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IO_CHANNEL 0x00020000L /* default IO channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* service errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define S_OK 1 /* no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define S_GENERR 6 /* general error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define S_BSY 7 /* controller busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define S_RAW_SCSI 12 /* raw serv.: target error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define S_RAW_ILL 0xff /* raw serv.: illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define S_NOFUNC -2 /* unknown function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define S_CACHE_RESERV -24 /* cache: reserv. conflict */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DEFAULT_PRI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IOCTL_PRI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HIGH_PRI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* data directions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GDTH_DATA_IN 0x01000000L /* data from target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GDTH_DATA_OUT 0x00000000L /* data to target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* other defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LINUX_OS 8 /* used for cache optim. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SECS32 0x1f /* round capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define LOCALBOARD 0 /* board node always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ASYNCINDEX 0 /* cmd index async. event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SPEZINDEX 1 /* cmd index unknown service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define COALINDEX (GDTH_MAXCMDS + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SCATTER_GATHER 1 /* s/g feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define GDT_64BIT 0x200 /* 64bit / drv>2TB support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #include "gdth_ioctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* screenservice message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 msg_handle; /* message handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 msg_len; /* size of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 msg_alen; /* answer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 msg_answer; /* answer flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 msg_ext; /* more messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 msg_reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) char msg_text[MSGLEN+2]; /* the message text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } __attribute__((packed)) gdth_msg_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* IOCTL data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Status coalescing buffer for returning multiple requests per interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 ext_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 info0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } __attribute__((packed)) gdth_coal_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* performance mode data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 version; /* The version of this IOCTL structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 st_buff_addr1; /* physical address of status buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 st_buff_u_addr1; /* reserved for 64 bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 st_buff_indx1; /* reserved command idx. for this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 st_buff_addr2; /* physical address of status buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 st_buff_u_addr2; /* reserved for 64 bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 st_buff_indx2; /* reserved command idx. for this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 st_buff_size; /* size of each buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 cmd_buff_size; /* size of each cmd buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } __attribute__((packed)) gdth_perf_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* SCSI drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 vendor[8]; /* vendor string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 product[16]; /* product string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 revision[4]; /* revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 sy_rate; /* current rate for sync. tr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 sy_max_rate; /* max. rate for sync. tr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 no_ldrive; /* belongs to this log. drv.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 blkcnt; /* number of blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 blksize; /* size of block in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 available; /* flag: access is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 init; /* medium is initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 devtype; /* SCSI devicetype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 rm_medium; /* medium is removable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 wp_medium; /* medium is write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 ansi; /* SCSI I/II or III? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 protocol; /* same as ansi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 sync; /* flag: sync. transfer enab. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 disc; /* flag: disconnect enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 queueing; /* flag: command queing enab. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 cached; /* flag: caching enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 target_id; /* target ID of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 lun; /* LUN id of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 orphan; /* flag: drive fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 last_error; /* sense key or drive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 last_result; /* result of last command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 check_errors; /* err. in last surface check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 percent; /* progress for surface check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 last_check; /* IOCTRL operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 res[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 flags; /* from 1.19/2.19: raw reserv.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 multi_bus; /* multi bus dev? (fibre ch.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 mb_status; /* status: available? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 res2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 mb_alt_status; /* status on second bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 mb_alt_bid; /* number of second bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 mb_alt_tid; /* target id on second bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 fc_flag; /* from 1.22/2.22: info valid?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 res4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 fc_frame_size; /* frame size (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) char wwn[8]; /* world wide name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } __attribute__((packed)) gdth_diskinfo_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* get SCSI channel count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 channel_no; /* number of channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 drive_cnt; /* drive count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 siop_id; /* SCSI processor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 siop_state; /* SCSI processor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } __attribute__((packed)) gdth_getch_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* get SCSI drive numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 sc_no; /* SCSI channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 sc_cnt; /* sc_list[] elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 sc_list[MAXID]; /* minor device numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } __attribute__((packed)) gdth_drlist_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* get grown/primary defect count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 sddc_type; /* 0x08: grown, 0x10: prim. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 sddc_format; /* list entry format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 sddc_len; /* list entry length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 sddc_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 sddc_cnt; /* entry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } __attribute__((packed)) gdth_defcnt_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* disk statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 bid; /* SCSI channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 first; /* first SCSI disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 entries; /* number of elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 count; /* (R) number of init. el. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 mon_time; /* time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 tid; /* target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 lun; /* LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 res[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 blk_size; /* block size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 rd_count; /* bytes read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 wr_count; /* bytes written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 rd_blk_count; /* blocks read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 wr_blk_count; /* blocks written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 retries; /* retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 reassigns; /* reassigns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } __attribute__((packed)) list[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } __attribute__((packed)) gdth_dskstat_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* IO channel header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 version; /* version (-1UL: newest) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u8 list_entries; /* list entry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 first_chan; /* first channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 last_chan; /* last channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 chan_count; /* (R) channel count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 list_offset; /* offset of list[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } __attribute__((packed)) gdth_iochan_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* get IO channel description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) gdth_iochan_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 address; /* channel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 type; /* type (SCSI, FCAL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 local_no; /* local number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u16 features; /* channel features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } __attribute__((packed)) list[MAXBUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } __attribute__((packed)) gdth_iochan_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* get raw IO channel description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gdth_iochan_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 proc_id; /* processor id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 proc_defect; /* defect ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } __attribute__((packed)) list[MAXBUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } __attribute__((packed)) gdth_raw_iochan_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* array drive component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 al_controller; /* controller ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 al_cache_drive; /* cache drive number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 al_status; /* cache drive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 al_res[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } __attribute__((packed)) gdth_arraycomp_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* array drive information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 ai_type; /* array type (RAID0,4,5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 ai_cache_drive_cnt; /* active cachedrives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 ai_state; /* array drive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 ai_master_cd; /* master cachedrive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 ai_master_controller; /* ID of master controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 ai_size; /* user capacity [sectors] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 ai_striping_size; /* striping size [sectors] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 ai_secsize; /* sector size [bytes] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 ai_err_info; /* failed cache drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 ai_name[8]; /* name of the array drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 ai_controller_cnt; /* number of controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 ai_removable; /* flag: removable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 ai_write_protected; /* flag: write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 ai_devtype; /* type: always direct access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) gdth_arraycomp_str ai_drives[35]; /* drive components: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 ai_drive_entries; /* number of drive components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 ai_protected; /* protection flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u8 ai_verify_state; /* state of a parity verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 ai_ext_state; /* extended array drive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 ai_expand_state; /* array expand state (>=2.18)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 ai_reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } __attribute__((packed)) gdth_arrayinf_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* get array drive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 controller_no; /* controller no. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 cd_handle; /* master cachedrive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u8 is_arrayd; /* Flag: is array drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 is_master; /* Flag: is array master? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 is_parity; /* Flag: is parity drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 is_hotfix; /* Flag: is hotfix drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 res[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } __attribute__((packed)) gdth_alist_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 entries_avail; /* allocated entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 entries_init; /* returned entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 first_entry; /* first entry number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 list_offset; /* offset of following list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) gdth_alist_str list[1]; /* list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } __attribute__((packed)) gdth_arcdl_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* cache info/config IOCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 version; /* firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u16 state; /* cache state (on/off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 strategy; /* cache strategy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u16 write_back; /* write back state (on/off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u16 block_size; /* cache block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } __attribute__((packed)) gdth_cpar_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 csize; /* cache size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 read_cnt; /* read/write counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 write_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 tr_hits; /* hits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 sec_hits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 sec_miss; /* misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } __attribute__((packed)) gdth_cstat_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gdth_cpar_str cpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) gdth_cstat_str cstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } __attribute__((packed)) gdth_cinfo_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* cache drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 cd_name[8]; /* cache drive name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 cd_devtype; /* SCSI devicetype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 cd_ldcnt; /* number of log. drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 cd_last_error; /* last error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 cd_initialized; /* drive is initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 cd_removable; /* media is removable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 cd_write_protected; /* write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u8 cd_flags; /* Pool Hot Fix? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 ld_blkcnt; /* number of blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 ld_blksize; /* blocksize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 ld_dcnt; /* number of disks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 ld_slave; /* log. drive index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 ld_dtype; /* type of logical drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 ld_last_error; /* last error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 ld_name[8]; /* log. drive name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 ld_error; /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } __attribute__((packed)) gdth_cdrinfo_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* OEM string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 ctl_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 file_major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 file_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 cpy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 ext_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 oem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 board_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } __attribute__((packed)) gdth_oem_str_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 product_0_1_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 product_4_5_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 product_cluster_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 product_reserved[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 scsi_cluster_target_vendor_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 cluster_raid_fw_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 oem_brand_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 oem_raid_type[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 bios_type[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u8 bios_title[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u8 oem_company_name[37];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 pci_id_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 pci_id_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 validation_status[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 reserved_1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 scsi_host_drive_inquiry_vendor_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 library_file_template[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 reserved_2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 tool_name_1[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u8 tool_name_2[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 tool_name_3[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 oem_contact_1[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 oem_contact_2[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 oem_contact_3[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } __attribute__((packed)) gdth_oem_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gdth_oem_str_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) gdth_oem_str text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } __attribute__((packed)) gdth_oem_str_ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* board features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 chaining; /* Chaining supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 striping; /* Striping (RAID-0) supp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 mirroring; /* Mirroring (RAID-1) supp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 raid; /* RAID-4/5/10 supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } __attribute__((packed)) gdth_bfeat_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* board info IOCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 ser_no; /* serial no. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 oem_id[2]; /* OEM ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u16 ep_flags; /* eprom flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 proc_id; /* processor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 memsize; /* memory size (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 mem_banks; /* memory banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 chan_type; /* channel type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 chan_count; /* channel count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 rdongle_pres; /* dongle present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 epr_fw_ver; /* (eprom) firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 upd_fw_ver; /* (update) firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 upd_revision; /* update revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) char type_string[16]; /* controller name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) char raid_string[16]; /* RAID firmware name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u8 update_pres; /* update present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 xor_pres; /* XOR engine present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 prom_type; /* ROM type (eprom/flash) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 prom_count; /* number of ROM devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 dup_pres; /* duplexing module present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 chan_pres; /* number of expansion chn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 mem_pres; /* memory expansion inst. ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 ft_bus_system; /* fault bus supported? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 subtype_valid; /* board_subtype valid? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u8 board_subtype; /* subtype/hardware level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 ramparity_pres; /* RAM parity check hardware? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } __attribute__((packed)) gdth_binfo_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* get host drive info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) char name[8]; /* host drive name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 size; /* size (sectors) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 host_drive; /* host drive number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 log_drive; /* log. drive (master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 rw_attribs; /* r/w attribs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 start_sec; /* start sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) } __attribute__((packed)) gdth_hentry_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 entries; /* entry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 offset; /* offset of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 secs_p_head; /* sectors/head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 heads_p_cyl; /* heads/cylinder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 clust_drvtype; /* cluster drive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 location; /* controller number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } __attribute__((packed)) gdth_hget_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* DPRAM structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* interface area ISA/PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 S_Cmd_Indx; /* special command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 volatile S_Status; /* status special command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 S_Info[4]; /* add. info special command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 volatile Sema0; /* command semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u8 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 Cmd_Index; /* command number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 reserved3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u16 volatile Status; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u16 Service; /* service(for async.events) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 Info[2]; /* additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u16 offset; /* command offs. in the DPRAM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u16 serv_id; /* service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 bios_reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 gdt_dpr_cmd[1]; /* commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } __attribute__((packed)) gdt_dpr_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* SRAM structure PCI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 magic; /* controller ID from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u16 need_deinit; /* switch betw. BIOS/driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u8 switch_support; /* see need_deinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 padding[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u8 os_used[16]; /* OS code per service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 unused[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 fw_magic; /* contr. ID from firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } __attribute__((packed)) gdt_pci_sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* DPRAM ISA controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u16 need_deinit; /* switch betw. BIOS/driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 switch_support; /* see need_deinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 padding[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 os_used[16]; /* OS code per service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } __attribute__((packed)) dp_sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u8 bios_area[0x4000]; /* 16KB reserved for BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } bu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) gdt_dpr_if ic; /* interface area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 if_area[0x3000]; /* 12KB for interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 memlock; /* write protection DPRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u8 event; /* release event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 irqen; /* board interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u8 irqdel; /* acknowledge board int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 volatile Sema1; /* status semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 rq; /* IRQ/DRQ configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } __attribute__((packed)) io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } __attribute__((packed)) gdt2_dpram_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* DPRAM PCI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) gdt_dpr_if ic; /* interface area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u8 if_area[0xff0-sizeof(gdt_pci_sram)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) gdt_pci_sram gdt6sr; /* SRAM structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 unused0[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 volatile Sema1; /* command semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u8 unused1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 irqen; /* board interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 unused2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 event; /* release event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u8 unused3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 irqdel; /* acknowledge board int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u8 unused4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } __attribute__((packed)) io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } __attribute__((packed)) gdt6_dpram_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* PLX register structure (new PCI controllers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u8 unused1[0x3f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u8 volatile sema0_reg; /* command semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u8 volatile sema1_reg; /* status semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 unused2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u16 volatile status; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u16 service; /* service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 info[2]; /* additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 unused3[0x10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u8 ldoor_reg; /* PCI to local doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 unused4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u8 volatile edoor_reg; /* local to PCI doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 unused5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 control0; /* control0 register(unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 control1; /* board interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 unused6[0x16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } __attribute__((packed)) gdt6c_plx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* DPRAM new PCI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) gdt_dpr_if ic; /* interface area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 if_area[0x4000-sizeof(gdt_pci_sram)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gdt_pci_sram gdt6sr; /* SRAM structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } __attribute__((packed)) gdt6c_dpram_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* i960 register structure (PCI MPR controllers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u8 unused1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 volatile sema0_reg; /* command semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u8 unused2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 volatile sema1_reg; /* status semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u8 unused3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u16 volatile status; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u16 service; /* service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 info[2]; /* additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u8 ldoor_reg; /* PCI to local doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u8 unused4[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 volatile edoor_reg; /* local to PCI doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 unused5[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 edoor_en_reg; /* board interrupts enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 unused6[27];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 unused7[939];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) char evt_str[256]; /* event string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) } __attribute__((packed)) gdt6m_i960_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* DPRAM PCI MPR controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gdt6m_i960_regs i960r; /* 4KB i960 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) gdt_dpr_if ic; /* interface area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u8 if_area[0x3000-sizeof(gdt_pci_sram)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) gdt_pci_sram gdt6sr; /* SRAM structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } __attribute__((packed)) gdt6m_dpram_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned long dpmem; /* DPRAM address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned long io; /* IO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } gdth_pci_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* controller information structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u16 hanum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u16 oem_id; /* OEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u16 type; /* controller class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 stype; /* subtype (PCI: device ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u16 fw_vers; /* firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u16 cache_feat; /* feat. cache serv. (s/g,..)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u16 raw_feat; /* feat. raw service (s/g,..)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u16 screen_feat; /* feat. raw service (s/g,..)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) void __iomem *brd; /* DPRAM address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 brd_phys; /* slot number/BIOS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) gdth_cmd_str cmdext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) gdth_cmd_str *pccb; /* address command structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 ccb_phys; /* phys. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #ifdef INT_COAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) gdth_coal_status *coal_stat; /* buffer for coalescing int.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u64 coal_stat_phys; /* phys. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) char *pscratch; /* scratch (DMA) buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u64 scratch_phys; /* phys. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 scratch_busy; /* in use? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u8 dma64_support; /* 64-bit DMA supported? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) gdth_msg_str *pmsg; /* message buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u64 msg_phys; /* phys. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 scan_mode; /* current scan mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 irq; /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 drq; /* DRQ (ISA controllers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u16 status; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u16 service; /* service/firmware ver./.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 info2; /* additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct scsi_cmnd *req_first; /* top of request queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 present; /* Flag: host drive present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 is_logdrv; /* Flag: log. drive (master)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 is_arraydrv; /* Flag: array drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 is_master; /* Flag: array drive master? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 is_parity; /* Flag: parity drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 is_hotfix; /* Flag: hotfix drive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 master_no; /* number of master drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 lock; /* drive locked? (hot plug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u8 heads; /* mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u16 devtype; /* further information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u64 size; /* capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 ldr_no; /* log. drive no. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u8 rw_attribs; /* r/w attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 cluster_type; /* cluster properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 start_sec; /* start sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) } hdr[MAX_LDRIVES]; /* host drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u8 lock; /* channel locked? (hot plug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u8 pdev_cnt; /* physical device count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u8 local_no; /* local channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u8 io_cnt[MAXID]; /* current IO count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 address; /* channel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 id_list[MAXID]; /* IDs of the phys. devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } raw[MAXBUS]; /* SCSI channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct scsi_cmnd *cmnd; /* pending request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u16 service; /* service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct gdth_cmndinfo { /* per-command private info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int internal_command; /* don't call scsi_done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dma_addr_t sense_paddr; /* sense dma-addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u8 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int timeout_count; /* # of timeout calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) volatile int wait_for_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) enum dma_data_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int phase; /* ???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int OpCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u8 bus_cnt; /* SCSI bus count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u8 tid_cnt; /* Target ID count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u8 bus_id[MAXBUS]; /* IOP IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 virt_bus; /* number of virtual bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u8 more_proc; /* more /proc info supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u16 cmd_cnt; /* command count in DPRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u16 cmd_len; /* length of actual command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u16 cmd_offs_dpmem; /* actual offset in DPRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u16 ic_all_size; /* sizeof DPRAM interf. area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) gdth_cpar_str cpar; /* controller cache par. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) gdth_bfeat_str bfeat; /* controller features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) gdth_binfo_str binfo; /* controller info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) gdth_evt_data dvr; /* event structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) spinlock_t smp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) char oem_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #ifdef GDTH_DMA_STATISTICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) } gdth_ha_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return (struct gdth_cmndinfo *)cmd->host_scribble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* INQUIRY data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u8 type_qual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u8 modif_rmb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u8 resp_aenc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u8 add_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u8 vendor[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u8 product[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u8 revision[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) } __attribute__((packed)) gdth_inq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* READ_CAPACITY data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 last_block_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 block_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } __attribute__((packed)) gdth_rdcap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* READ_CAPACITY (16) data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u64 last_block_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 block_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } __attribute__((packed)) gdth_rdcap16_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* REQUEST_SENSE data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u8 errorcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 segno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u32 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u8 add_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 cmd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u8 adsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u8 adsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u8 fruc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u8 key_spec[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } __attribute__((packed)) gdth_sense_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* MODE_SENSE data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u8 data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u8 med_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u8 dev_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u8 bd_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } __attribute__((packed)) hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u8 dens_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u8 block_count[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u8 block_length[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) } __attribute__((packed)) bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } __attribute__((packed)) gdth_modep_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* stack frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned long b[10]; /* 32/64 bit compiler ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) } __attribute__((packed)) gdth_stackframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* function prototyping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int gdth_show_info(struct seq_file *, struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int gdth_set_info(struct Scsi_Host *, char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags