^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Cisco Systems, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2007 Nuova Systems, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef _VNIC_CQ_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define _VNIC_CQ_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cq_desc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "vnic_dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Driver) when both are built with CONFIG options =y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define vnic_cq_service fnic_cq_service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define vnic_cq_free fnic_cq_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define vnic_cq_alloc fnic_cq_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define vnic_cq_init fnic_cq_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define vnic_cq_clean fnic_cq_clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Completion queue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct vnic_cq_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 ring_base; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 ring_size; /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 flow_control_enable; /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 color_enable; /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 cq_head; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 cq_tail; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 cq_tail_color; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 interrupt_enable; /* 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 pad6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 cq_entry_enable; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 pad7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 cq_message_enable; /* 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 pad8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 interrupt_offset; /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 pad9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u64 cq_message_addr; /* 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 pad10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct vnic_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct vnic_dev *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct vnic_cq_ctrl __iomem *ctrl; /* memory-mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct vnic_dev_ring ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int to_clean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int last_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline unsigned int vnic_cq_service(struct vnic_cq *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int work_to_do,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int (*q_service)(struct vnic_dev *vdev, struct cq_desc *cq_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 type, u16 q_number, u16 completed_index, void *opaque),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct cq_desc *cq_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 q_number, completed_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 type, color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cq->ring.desc_size * cq->to_clean);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cq_desc_dec(cq_desc, &type, &color,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &q_number, &completed_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) while (color != cq->last_color) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if ((*q_service)(cq->vdev, cq_desc, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) q_number, completed_index, opaque))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cq->to_clean++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (cq->to_clean == cq->ring.desc_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cq->to_clean = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) cq->last_color = cq->last_color ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cq->ring.desc_size * cq->to_clean);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cq_desc_dec(cq_desc, &type, &color,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &q_number, &completed_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) work_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (work_done >= work_to_do)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void vnic_cq_free(struct vnic_cq *cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int desc_count, unsigned int desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int cq_tail_color, unsigned int interrupt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int cq_entry_enable, unsigned int message_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int interrupt_offset, u64 message_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void vnic_cq_clean(struct vnic_cq *cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif /* _VNIC_CQ_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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