^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* esp_scsi.h: Defines and structures for the ESP driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _ESP_SCSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _ESP_SCSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Access Description Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SBUS_ESP_REG_SIZE 0x40UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Bitfield meanings for the above registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ESP config reg 1, read-write, found on all ESP chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* ESP config register 4 read-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ESP_CONFIG_GE_12NS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* ESP command register read-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Group 1 commands: These may be sent at any point in time to the ESP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * chip. None of them can generate interrupts 'cept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the "SCSI bus reset" command if you have not disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * SCSI reset interrupts in the config1 ESP register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ESP_CMD_RC 0x02 /* Chip reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ESP_CMD_RS 0x03 /* SCSI bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Group 2 commands: ESP must be an initiator and connected to a target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * for these commands to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ESP_CMD_TI 0x10 /* Transfer Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ESP_CMD_SATN 0x1a /* Set ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ESP_CMD_RATN 0x1b /* De-assert ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * to a target as the initiator for these commands to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ESP_CMD_SMSG 0x20 /* Send message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ESP_CMD_SSTAT 0x21 /* Send status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ESP_CMD_SDATA 0x22 /* Send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ESP_CMD_DCNCT 0x27 /* Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ESP_CMD_RMSG 0x28 /* Receive Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ESP_CMD_RCMD 0x29 /* Receive Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ESP_CMD_RDATA 0x2a /* Receive Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Group 4 commands: The ESP must be in the disconnected state and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * not be connected to any targets as initiator for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * these commands to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ESP_CMD_RSEL 0x40 /* Reselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ESP_CMD_SELA 0x42 /* Select w/ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ESP_CMD_ESEL 0x44 /* Enable selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ESP_CMD_DSEL 0x45 /* Disable selections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* This bit enables the ESP's DMA on the SBus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ESP_CMD_DMA 0x80 /* Do DMA? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* ESP status register read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ESP_STAT_PIO 0x01 /* IO phase bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ESP_STAT_PCD 0x02 /* CD phase bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ESP_STAT_PERR 0x20 /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ESP_STAT_SPAM 0x40 /* Real bad error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * bit on other revs of the ESP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ESP_STAT_INTR 0x80 /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* The status register can be masked with ESP_STAT_PMASK and compared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * with the following values to determine the current phase the ESP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * (at least thinks it) is in. For our purposes we also add our own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * software 'done' bit for our phase management engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ESP_DOP (0) /* Data Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ESP_DIP (ESP_STAT_PIO) /* Data In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ESP_CMDP (ESP_STAT_PCD) /* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* HME only: status 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* ESP interrupt register read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ESP_INTR_S 0x01 /* Select w/o ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ESP_INTR_SATN 0x02 /* Select w/ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ESP_INTR_RSEL 0x04 /* Reselected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ESP_INTR_FDONE 0x08 /* Function done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ESP_INTR_BSERV 0x10 /* Bus service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ESP_INTR_DC 0x20 /* Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ESP_INTR_IC 0x40 /* Illegal command given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* ESP sequence step register read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ESP_STEP_VBITS 0x07 /* Valid bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ESP_STEP_SID 0x01 /* One msg byte sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * bytes to be lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ESP_STEP_FINI4 0x04 /* Command was sent ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Ho hum, some ESP's set the step register to this as well... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ESP_STEP_FINI5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ESP_STEP_FINI6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ESP_STEP_FINI7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* ESP chip-test register read-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ESP_TEST_TARG 0x01 /* Target test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ESP_TEST_INI 0x02 /* Initiator test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ESP_TEST_TS 0x04 /* Tristate test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* ESP unique ID register read-only, found on fas236+fas100a only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ESP_UID_FAM 0xf8 /* ESP family bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Values for the ESP family bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ESP_UID_F100A 0x00 /* ESP FAS100A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ESP_UID_F236 0x02 /* ESP FAS236 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ESP_UID_HME 0x0a /* FAS HME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* ESP fifo flags register read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Note that the following implies a 16 byte FIFO on the ESP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ESP_FF_SSTEP 0xe0 /* Sequence step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* ESP clock conversion factor register write-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ESP_CCF_F2 0x02 /* 10MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* HME only... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ESP_BUSID_RESELID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ESP_BUSID_CTR32BIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ESP_TIMEO_CONST 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ESP_NEG_DEFP(mhz, cfact) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * input clock rates we try to do 10mb/s although I don't think a transfer can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * even run that fast with an ESP even with DMA2 scatter gather pipelining.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SYNC_DEFP_FAST 0x19 /* 10mb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct esp_cmd_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int cur_residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct scatterlist *prv_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct scatterlist *cur_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int tot_residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* NOTE: this enum is ordered based on chip features! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum esp_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ESP100, /* NCR53C90 - very broken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ESP100A, /* NCR53C90A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ESP236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FAS236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PCSCSI, /* AM53c974 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FSC, /* NCR/Symbios Logic 53CF9x-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FAS100A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FASHME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct esp_cmd_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int saved_cur_residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct scatterlist *saved_prv_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct scatterlist *saved_cur_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int saved_tot_residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ESP_CMD_FLAG_RESIDUAL 0x08 /* AM53c974 BLAST residual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 tag[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 orig_tag[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned char *sense_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned char *saved_sense_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_addr_t sense_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct completion *eh_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ESP_DEFAULT_TAGS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ESP_MAX_TARGET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ESP_MAX_LUN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ESP_MAX_TAG 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct esp_lun_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct esp_cmd_entry *non_tagged_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int num_tagged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct esp_target_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * match the currently negotiated settings for this target. The SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * protocol values are maintained in spi_{offset,period,wide}(starget).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 esp_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 esp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 esp_config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ESP_TGT_WIDE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ESP_TGT_DISCONNECT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ESP_TGT_NEGO_WIDE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ESP_TGT_NEGO_SYNC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ESP_TGT_CHECK_NEGO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ESP_TGT_BROKEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * device we will try to negotiate the following parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 nego_goal_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 nego_goal_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 nego_goal_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 nego_goal_tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct scsi_target *starget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct esp_event_ent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ESP_EVENT_TYPE_EVENT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ESP_EVENT_TYPE_CMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 seqreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 sreg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 select_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct esp_driver_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Read and write the ESP 8-bit registers. On some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * applications of the ESP chip the registers are at 4-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * instead of 1-byte intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 (*esp_read8)(struct esp *esp, unsigned long reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Return non-zero if there is an IRQ pending. Usually this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * status bit lives in the DMA controller sitting in front of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * the ESP. This has to be accurate or else the ESP interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * handler will not run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int (*irq_pending)(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Return the maximum allowable size of a DMA transfer for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * given buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Reset the DMA engine entirely. On return, ESP interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * should be enabled. Often the interrupt enabling is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * controlled in the DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void (*reset_dma)(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Drain any pending DMA in the DMA engine after a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * This is for writes to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void (*dma_drain)(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Invalidate the DMA engine after a DMA transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void (*dma_invalidate)(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Setup an ESP command that will use a DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * The 'esp_count' specifies what transfer length should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * programmed into the ESP transfer counter registers, whereas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * the 'dma_count' is the length that should be programmed into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * the DMA controller. Usually they are the same. If 'write'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * is non-zero, this transfer is a write into memory. 'cmd'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * holds the ESP command that should be issued by calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * scsi_esp_cmd() at the appropriate time while programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * the DMA hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 dma_count, int write, u8 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Return non-zero if the DMA engine is reporting an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int (*dma_error)(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define ESP_MAX_MSG_SZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define ESP_EVENT_LOG_SZ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define ESP_QUICKIRQ_LIMIT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ESP_RESELECT_TAG_LIMIT 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct esp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void __iomem *dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) const struct esp_driver_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct esp_cmd_entry *active_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct list_head queued_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct list_head active_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 *command_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_addr_t command_block_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int data_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* The following are used to determine the cause of an IRQ. Upon every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * IRQ entry we synchronize these with the hardware registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u8 sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 seqreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 sreg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 prev_hme_dmacsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 prev_soff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 prev_stp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 prev_cfg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 num_tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct list_head esp_cmd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct esp_target_data target[ESP_MAX_TARGET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int fifo_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 fifo[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int esp_event_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 msg_out[ESP_MAX_MSG_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int msg_out_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 msg_in[ESP_MAX_MSG_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int msg_in_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 scsi_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) enum esp_rev rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ESP_FLAG_DIFFERENTIAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define ESP_FLAG_RESETTING 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define ESP_FLAG_WIDE_CAPABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define ESP_FLAG_DISABLE_SYNC 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define ESP_FLAG_USE_FIFO 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define ESP_FLAG_NO_DMA_MAP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 select_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define ESP_SELECT_NONE 0x00 /* Not selecting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* When we are not selecting, we are expecting an event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ESP_EVENT_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define ESP_EVENT_CMD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define ESP_EVENT_CMD_DONE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define ESP_EVENT_DATA_IN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define ESP_EVENT_DATA_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define ESP_EVENT_DATA_DONE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define ESP_EVENT_MSGIN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define ESP_EVENT_MSGIN_MORE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ESP_EVENT_MSGIN_DONE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ESP_EVENT_MSGOUT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define ESP_EVENT_MSGOUT_DONE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ESP_EVENT_STATUS 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define ESP_EVENT_FREE_BUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define ESP_EVENT_CHECK_PHASE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define ESP_EVENT_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Probed in esp_get_clock_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 cfact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 ccycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 ctick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 neg_defp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 sync_defp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Computed in esp_reset_esp() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 max_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 min_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 radelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* ESP_CMD_SELAS command state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 *cmd_bytes_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int cmd_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct completion *eh_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int dmarev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* These are used by esp_send_pio_cmd() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 __iomem *fifo_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int send_cmd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 send_cmd_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* A front-end driver for the ESP chip should do the following in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * it's device probe routine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * 1) Allocate the host and private area using scsi_host_alloc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * with size 'sizeof(struct esp)'. The first argument to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * scsi_host_alloc() should be &scsi_esp_template.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * 2) Set host->max_id as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * 3) Set esp->host to the scsi_host itself, and esp->dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * to the device object pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * 4) Hook up esp->ops to the front-end implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * in esp->flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * 6) Map the DMA and ESP chip registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 7) DMA map the ESP command block, store the DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * in esp->command_block_dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * 8) Register the scsi_esp_intr() interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * 9) Probe for and provide the following chip properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * esp->scsi_id (assign to esp->host->this_id too)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * esp->scsi_id_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * esp->cfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * DMA burst bit mask in esp->bursts, if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * 10) Perform any actions necessary before the ESP device can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * be programmed for the first time. On some configs, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * example, the DMA engine has to be reset before ESP can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * be programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * 11) If necessary, call dev_set_drvdata() as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * 12) Call scsi_esp_register() with prepared 'esp' structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * 13) Check scsi_esp_register() return value, release all resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * if an error was returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) extern struct scsi_host_template scsi_esp_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) extern int scsi_esp_register(struct esp *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) extern void scsi_esp_unregister(struct esp *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) extern irqreturn_t scsi_esp_intr(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) extern void scsi_esp_cmd(struct esp *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 dma_count, int write, u8 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #endif /* !(_ESP_SCSI_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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