^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/scsi/esas2r/esas2r.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2001-2013 ATTO Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (mailto:linuxdrivers@attotech.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * as published by the Free Software Foundation; either version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "esas2r_log.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "atioctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "atvda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifndef ESAS2R_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ESAS2R_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Global Variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern struct esas2r_adapter *esas2r_adapters[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern u8 *esas2r_buffered_ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern dma_addr_t esas2r_buffered_ioctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern u32 esas2r_buffered_ioctl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern struct pci_dev *esas2r_buffered_ioctl_pcid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SGL_PG_SZ_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SGL_PG_SZ_MAX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern int sgl_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NUM_SGL_MIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NUM_SGL_MAX 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern int num_sg_lists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NUM_REQ_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NUM_REQ_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern int num_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NUM_AE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NUM_AE_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern int num_ae_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern int cmd_per_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern int esas2r_max_sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern int sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern int interrupt_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern int num_io_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Macro defintions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ESAS2R_MAX_ID 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX_ADAPTERS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ESAS2R_DRVR_NAME "esas2r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ESAS2R_LONGNAME "ATTO ExpressSAS 6GB RAID Adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ESAS2R_MAX_DEVICES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ATTONODE_NAME "ATTONode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ESAS2R_MAJOR_REV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ESAS2R_MINOR_REV 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ESAS2R_VERSION_STR DEFINED_NUM_TO_STR(ESAS2R_MAJOR_REV) "." \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINED_NUM_TO_STR(ESAS2R_MINOR_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ESAS2R_COPYRIGHT_YEARS "2001-2013"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ESAS2R_DEFAULT_SGL_PAGE_SIZE 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ESAS2R_DEFAULT_CMD_PER_LUN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ESAS2R_DEFAULT_NUM_SG_LISTS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DEFINED_NUM_TO_STR(num) NUM_TO_STR(num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NUM_TO_STR(num) #num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ESAS2R_SGL_ALIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ESAS2R_LIST_ALIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ESAS2R_LIST_EXTRA ESAS2R_NUM_EXTRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ESAS2R_DATA_BUF_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ESAS2R_DEFAULT_TMO 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ESAS2R_DISC_BUF_LEN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ESAS2R_FWCOREDUMP_SZ 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ESAS2R_NUM_PHYS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ESAS2R_TARG_ID_INV 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ESAS2R_INT_STS_MASK MU_INTSTAT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ESAS2R_INT_ENB_MASK MU_INTSTAT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ESAS2R_INT_DIS_MASK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ESAS2R_MAX_TARGETS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ESAS2R_KOBJ_NAME_LEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* u16 (WORD) component macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LOBYTE(w) ((u8)(u16)(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HIBYTE(w) ((u8)(((u16)(w)) >> 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAKEWORD(lo, hi) ((u16)((u8)(lo) | ((u16)(u8)(hi) << 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* u32 (DWORD) component macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LOWORD(d) ((u16)(u32)(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HIWORD(d) ((u16)(((u32)(d)) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAKEDWORD(lo, hi) ((u32)((u16)(lo) | ((u32)(u16)(hi) << 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* macro to get the lowest nonzero bit of a value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LOBIT(x) ((x) & (0 - (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* These functions are provided to access the chip's control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * The register is specified by its byte offset from the register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * for the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define esas2r_read_register_dword(a, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define esas2r_write_register_dword(a, reg, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* This function is provided to access the chip's data window. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * register is specified by its byte offset from the window base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * for the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define esas2r_read_data_byte(a, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) readb((void __iomem *)a->data_window + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* ATTO vendor and device Ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ATTO_VENDOR_ID 0x117C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ATTO_DID_INTEL_IOP348 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ATTO_DID_MV_88RC9580 0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ATTO_DID_MV_88RC9580TS 0x0066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ATTO_DID_MV_88RC9580TSE 0x0067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ATTO_DID_MV_88RC9580TL 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* ATTO subsystem device Ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ATTO_SSDID_TBT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ATTO_TSSC_3808 0x4066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ATTO_TSSC_3808E 0x4067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ATTO_TLSH_1068 0x4068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ATTO_ESAS_R680 0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ATTO_ESAS_R608 0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ATTO_ESAS_R60F 0x004B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ATTO_ESAS_R6F0 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ATTO_ESAS_R644 0x004D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ATTO_ESAS_R648 0x004E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * flash definitions & structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * define the code types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FBT_CPYR 0xAA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FBT_SETUP 0xAA02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FBT_FLASH_VER 0xAA04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* offsets to various locations in flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FLS_OFFSET_BOOT (u32)(0x00700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FLS_OFFSET_NVR (u32)(0x007C0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FLS_OFFSET_CPYR FLS_OFFSET_NVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FLS_LENGTH_BOOT (FLS_OFFSET_CPYR - FLS_OFFSET_BOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FLS_BLOCK_SIZE (u32)(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FI_NVR_2KB 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FI_NVR_8KB 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FM_BUF_SZ 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * marvell frey (88R9580) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * chip revision identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MVR_FREY_B2 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * memory window definitions. window 0 is the data window with definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * of MW_DATA_XXX. window 1 is the register window with definitions of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * MW_REG_XXX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MW_REG_WINDOW_SIZE (u32)(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MW_REG_OFFSET_HWREG (u32)(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MW_REG_OFFSET_PCI (u32)(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MW_REG_PCI_HWREG_DELTA (MW_REG_OFFSET_PCI - MW_REG_OFFSET_HWREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MW_DATA_WINDOW_SIZE (u32)(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MW_DATA_ADDR_SER_FLASH (u32)(0xEC000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MW_DATA_ADDR_SRAM (u32)(0xF4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MW_DATA_ADDR_PAR_FLASH (u32)(0xFC000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * the following registers are for the communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * list interface (AKA message unit (MU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MU_IN_LIST_ADDR_LO (u32)(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MU_IN_LIST_ADDR_HI (u32)(0x00004004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MU_IN_LIST_WRITE (u32)(0x00004018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MU_ILW_TOGGLE (u32)(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MU_IN_LIST_READ (u32)(0x0000401C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MU_ILR_TOGGLE (u32)(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MU_ILIC_LIST (u32)(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MU_ILIC_LIST_F0 (u32)(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MU_ILIC_DEST (u32)(0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MU_ILIC_DEST_DDR (u32)(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MU_IN_LIST_IFC_CONFIG (u32)(0x00004028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MU_IN_LIST_CONFIG (u32)(0x0000402C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MU_ILC_ENABLE (u32)(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MU_ILC_ENTRY_MASK (u32)(0x000000F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MU_ILC_ENTRY_4_DW (u32)(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MU_ILC_DYNAMIC_SRC (u32)(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MU_ILC_NUMBER_MASK (u32)(0x7FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MU_ILC_NUMBER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MU_OUT_LIST_ADDR_LO (u32)(0x00004050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MU_OUT_LIST_ADDR_HI (u32)(0x00004054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MU_OUT_LIST_COPY_PTR_LO (u32)(0x00004058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MU_OUT_LIST_COPY_PTR_HI (u32)(0x0000405C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MU_OUT_LIST_WRITE (u32)(0x00004068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MU_OLW_TOGGLE (u32)(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MU_OUT_LIST_COPY (u32)(0x0000406C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MU_OLC_TOGGLE (u32)(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MU_OLC_WRT_PTR (u32)(0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MU_OUT_LIST_IFC_CONFIG (u32)(0x00004078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MU_OLIC_LIST (u32)(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MU_OLIC_LIST_F0 (u32)(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MU_OLIC_SOURCE (u32)(0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MU_OLIC_SOURCE_DDR (u32)(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MU_OUT_LIST_CONFIG (u32)(0x0000407C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MU_OLC_ENABLE (u32)(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MU_OLC_ENTRY_MASK (u32)(0x000000F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MU_OLC_ENTRY_4_DW (u32)(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MU_OLC_NUMBER_MASK (u32)(0x7FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MU_OLC_NUMBER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MU_OUT_LIST_INT_STAT (u32)(0x00004088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MU_OLIS_INT (u32)(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MU_OUT_LIST_INT_MASK (u32)(0x0000408C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MU_OLIS_MASK (u32)(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * the maximum size of the communication lists is two greater than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * maximum amount of VDA requests. the extra are to prevent queue overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ESAS2R_MAX_NUM_REQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ESAS2R_NUM_EXTRA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ESAS2R_MAX_COMM_LIST_SIZE (ESAS2R_MAX_NUM_REQS + ESAS2R_NUM_EXTRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * the following registers are for the CPU interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MU_CTL_STATUS_IN (u32)(0x00010108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MU_CTL_IN_FULL_RST (u32)(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MU_CTL_STATUS_IN_B2 (u32)(0x00010130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MU_CTL_IN_FULL_RST2 (u32)(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MU_DOORBELL_IN (u32)(0x00010460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRBL_RESET_BUS (u32)(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DRBL_PAUSE_AE (u32)(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRBL_RESUME_AE (u32)(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRBL_MSG_IFC_DOWN (u32)(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DRBL_FLASH_REQ (u32)(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRBL_FLASH_DONE (u32)(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DRBL_FORCE_INT (u32)(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DRBL_MSG_IFC_INIT (u32)(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRBL_POWER_DOWN (u32)(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRBL_DRV_VER_1 (u32)(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRBL_DRV_VER DRBL_DRV_VER_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MU_DOORBELL_IN_ENB (u32)(0x00010464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MU_DOORBELL_OUT (u32)(0x00010480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRBL_PANIC_REASON_MASK (u32)(0x00F00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRBL_UNUSED_HANDLER (u32)(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRBL_UNDEF_INSTR (u32)(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRBL_PREFETCH_ABORT (u32)(0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRBL_DATA_ABORT (u32)(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRBL_JUMP_TO_ZERO (u32)(0x00500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRBL_FW_RESET (u32)(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRBL_FW_VER_MSK (u32)(0x00070000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRBL_FW_VER_0 (u32)(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRBL_FW_VER_1 (u32)(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRBL_FW_VER DRBL_FW_VER_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MU_DOORBELL_OUT_ENB (u32)(0x00010484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRBL_ENB_MASK (u32)(0x00F803FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MU_INT_STATUS_OUT (u32)(0x00010200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MU_INTSTAT_POST_OUT (u32)(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MU_INTSTAT_DRBL_IN (u32)(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MU_INTSTAT_DRBL (u32)(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MU_INTSTAT_MASK (u32)(0x00001010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MU_INT_MASK_OUT (u32)(0x0001020C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* PCI express registers accessed via window 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MVR_PCI_WIN1_REMAP (u32)(0x00008438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MVRPW1R_ENABLE (u32)(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* inbound list dynamic source entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct esas2r_inbound_list_source_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HWILSE_INTERFACE_F0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* PCI data structure in expansion ROM images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct __packed esas2r_boot_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) char signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u16 VPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 struct_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 struct_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 class_code[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 image_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 code_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 code_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CODE_TYPE_PC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CODE_TYPE_OPEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CODE_TYPE_EFI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 indicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define INDICATOR_LAST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct __packed esas2r_boot_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u16 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 reserved[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u16 header_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u16 pnp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct __packed esas2r_pc_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u16 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 entry_point[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 image_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 min_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 rom_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u16 header_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u16 pnp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct esas2r_boot_header boot_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct __packed esas2r_efi_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 efi_signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define EFI_ROM_SIG 0x00000EF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u16 image_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define EFI_IMAGE_APP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define EFI_IMAGE_BSD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define EFI_IMAGE_RTD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u16 machine_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define EFI_MACHINE_IA32 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define EFI_MACHINE_IA64 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define EFI_MACHINE_X64 0x8664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define EFI_MACHINE_EBC 0x0EBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 compression;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define EFI_UNCOMPRESSED 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define EFI_COMPRESSED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u16 efi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 header_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct esas2r_boot_header boot_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct esas2r_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct esas2r_sg_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct esas2r_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) typedef void (*RQCALLBK) (struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) typedef bool (*RQBUILDSGL) (struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct esas2r_component_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 img_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CH_IT_FW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CH_IT_NVR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CH_IT_BIOS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CH_IT_MAC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CH_IT_CFG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CH_IT_EFI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CH_STAT_PENDING 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CH_STAT_FAILED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CH_STAT_SUCCESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CH_STAT_RETRY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CH_STAT_INVALID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 image_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define FI_REL_VER_SZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct esas2r_flash_img_v0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 fi_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define FI_VERSION_0 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 adap_typ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u16 driver_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u16 num_comps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define FI_NUM_COMPS_V0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 rel_version[FI_REL_VER_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 scratch_buf[FM_BUF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct esas2r_flash_img {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 fi_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define FI_VERSION_1 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define FI_STAT_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FI_STAT_FAILED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FI_STAT_REBOOT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define FI_STAT_ADAPTYP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FI_STAT_INVALID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define FI_STAT_CHKSUM 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define FI_STAT_LENGTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FI_STAT_UNKNOWN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define FI_STAT_IMG_VER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define FI_STAT_BUSY 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define FI_STAT_DUAL 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define FI_STAT_MISSING 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define FI_STAT_UNSUPP 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define FI_STAT_ERASE 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define FI_STAT_FLASH 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FI_STAT_DEGRADED 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 adap_typ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define FI_AT_UNKNWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FI_AT_SUN_LAKE 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define FI_AT_MV_9580 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define FI_ACT_DOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define FI_ACT_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define FI_ACT_UPSZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define FI_ACT_MAX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define FI_ACT_DOWN1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u16 driver_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FI_FLG_NVR_DEF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 num_comps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FI_NUM_COMPS_V1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 rel_version[FI_REL_VER_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 scratch_buf[FM_BUF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* definitions for flash script (FS) commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct esas2r_ioctlfs_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define ESAS2R_FS_CMD_ERASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define ESAS2R_FS_CMD_READ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define ESAS2R_FS_CMD_BEGINW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define ESAS2R_FS_CMD_WRITE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define ESAS2R_FS_CMD_COMMIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ESAS2R_FS_CMD_CANCEL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 image_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct esas2r_ioctl_fs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ESAS2R_FS_VER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 driver_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 adap_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define ESAS2R_FS_AT_ESASRAID2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define ESAS2R_FS_AT_TSSASRAID2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define ESAS2R_FS_AT_TSSASRAID2E 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define ESAS2R_FS_AT_TLSASHBA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 driver_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 reserved[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct esas2r_ioctlfs_command command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct esas2r_sas_nvram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SASNVR_VERSION_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SASNVR_VERSION SASNVR_VERSION_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SASNVR_CKSUM_SEED 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 max_lun_for_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 pci_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SASNVR_PCILAT_DIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SASNVR_PCILAT_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SASNVR_PCILAT_MAX 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 options1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SASNVR1_BOOT_DRVR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SASNVR1_BOOT_SCAN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SASNVR1_DIS_PCI_MWI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SASNVR1_FORCE_ORD_Q 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SASNVR1_CACHELINE_0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SASNVR1_DIS_DEVSORT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SASNVR1_PWR_MGT_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SASNVR1_WIDEPORT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 options2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SASNVR2_SINGLE_BUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SASNVR2_SLOT_BIND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SASNVR2_EXP_PROG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SASNVR2_CMDTHR_LUN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SASNVR2_HEARTBEAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SASNVR2_INT_CONNECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SASNVR2_SW_MUX_CTRL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SASNVR2_DISABLE_NCQ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 int_coalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SASNVR_COAL_DIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SASNVR_COAL_LOW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SASNVR_COAL_MED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SASNVR_COAL_HI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 cmd_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SASNVR_CMDTHR_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 dev_wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 dev_wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 spin_up_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SASNVR_SPINUP_MAX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 ssp_align_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 sas_addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 phy_speed[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SASNVR_SPEED_AUTO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SASNVR_SPEED_1_5GB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SASNVR_SPEED_3GB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SASNVR_SPEED_6GB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SASNVR_SPEED_12GB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 phy_mux[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SASNVR_MUX_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SASNVR_MUX_1_5GB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SASNVR_MUX_3GB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SASNVR_MUX_6GB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 phy_flags[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SASNVR_PHF_DISABLED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SASNVR_PHF_RD_ONLY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 sort_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SASNVR_SORT_SAS_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SASNVR_SORT_H308_CONN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SASNVR_SORT_PHY_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SASNVR_SORT_SLOT_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 dpm_reqcmd_lmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 dpm_stndby_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 dpm_active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 phy_target_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SASNVR_PTI_DISABLED 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 virt_ses_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SASNVR_VSMH_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u8 read_write_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SASNVR_RWM_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 link_down_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u8 reserved[0xA1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) typedef u32 (*PGETPHYSADDR) (struct esas2r_sg_context *sgc, u64 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct esas2r_sg_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct esas2r_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct esas2r_request *first_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 *cur_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PGETPHYSADDR get_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct atto_vda_sge *curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct atto_vda_sge *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct atto_vda_sge *limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct atto_vda_sge *chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } a64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct atto_physical_region_description *curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct atto_physical_region_description *chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 sgl_max_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 sge_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct scatterlist *cur_sgel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 *exp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int num_sgel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int sgel_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct esas2r_target {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define TF_PASS_THRU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define TF_USED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 new_target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u8 buffered_target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define TS_NOT_PRESENT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TS_PRESENT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TS_LUN_CHANGE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define TS_INVALID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 inter_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 inter_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u16 virt_targ_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u16 phys_targ_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 identifier_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u64 sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 identifier[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct atto_vda_ae_lu lu_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct esas2r_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct list_head comp_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct list_head req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) union atto_vda_req *vrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct esas2r_mem_desc *vrq_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void *data_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) union atto_vda_rsp_data *vda_rsp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u8 *sense_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct list_head sg_table_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct esas2r_mem_desc *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define RQ_TIMEOUT_S1 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define RQ_TIMEOUT_S2 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define RQ_MAX_TIMEOUT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u16 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u8 req_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define RT_INI_REQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define RT_DISC_REQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) union atto_vda_func_rsp func_rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RQCALLBK comp_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) RQCALLBK interrupt_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void *interrupt_cx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define RF_1ST_IBLK_BASE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define RF_FAILURE_OK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 req_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u16 vda_req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define RQ_SIZE_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u64 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RQCALLBK aux_req_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) void *aux_req_cx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 max_blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 *task_management_status_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct esas2r_flash_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct esas2r_flash_img *fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RQCALLBK interrupt_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 *sgc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 fi_hdr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define FMTSK_ERASE_BOOT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define FMTSK_WRTBIOS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define FMTSK_READBIOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define FMTSK_WRTMAC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define FMTSK_READMAC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define FMTSK_WRTEFI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define FMTSK_READEFI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define FMTSK_WRTCFG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define FMTSK_READCFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u8 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u16 num_comps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 cmp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 flsh_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 curr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 comp_typ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct esas2r_sg_context sgc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct esas2r_disc_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 disc_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define DCDE_DEV_CHANGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define DCDE_DEV_SCAN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define DCS_DEV_RMV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define DCS_DEV_ADD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define DCS_BLOCK_DEV_SCAN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define DCS_RAID_GRP_INFO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define DCS_PART_INFO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define DCS_PT_DEV_INFO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define DCS_PT_DEV_ADDR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define DCS_DISC_DONE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define DCF_DEV_CHANGE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define DCF_DEV_SCAN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define DCF_POLLED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u16 dev_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u8 part_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u8 raid_grp_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) char raid_grp_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct esas2r_target *curr_targ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u16 curr_virt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u16 curr_phys_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u8 scan_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 dev_addr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u64 sas_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct esas2r_mem_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct list_head next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) void *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) void *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void *esas2r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 esas2r_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) enum fw_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fw_event_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) fw_event_lun_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fw_event_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fw_event_not_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) fw_event_vda_ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct esas2r_vda_ae {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define ESAS2R_VDA_EVENT_SIG 0x4154544F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u8 bus_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u8 pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) union atto_vda_ae vda_ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct esas2r_fw_event_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct esas2r_adapter *a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) enum fw_event_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 data[sizeof(struct esas2r_vda_ae)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) enum state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) FW_INVALID_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) FW_STATUS_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) FW_COMMAND_ST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct esas2r_firmware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) enum state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct esas2r_flash_img header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u64 phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int orig_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) void *header_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u64 header_buff_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct esas2r_adapter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct esas2r_target targetdb[ESAS2R_MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct esas2r_target *targetdb_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned char *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned char *data_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define AF_PORT_CHANGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define AF_CHPRST_NEEDED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AF_CHPRST_PENDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define AF_CHPRST_DETECTED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define AF_BUSRST_NEEDED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define AF_BUSRST_PENDING 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define AF_BUSRST_DETECTED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define AF_DISABLED 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define AF_FLASH_LOCK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define AF_OS_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define AF_FLASHING 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define AF_POWER_MGT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define AF_NVR_VALID 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define AF_DEGRADED_MODE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define AF_DISC_PENDING 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define AF_TASKLET_SCHEDULED 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define AF_HEARTBEAT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define AF_HEARTBEAT_ENB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define AF_NOT_PRESENT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define AF_CHPRST_STARTED 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define AF_FIRST_INIT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define AF_POWER_DOWN 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define AF_DISC_IN_PROG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define AF_COMM_LIST_TOGGLE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define AF_LEGACY_SGE_MODE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define AF_DISC_POLLED 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) long flags2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define AF2_SERIAL_FLASH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define AF2_DEV_SCAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define AF2_DEV_CNT_OK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define AF2_COREDUMP_AVAIL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define AF2_COREDUMP_SAVED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define AF2_VDA_POWER_DOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define AF2_THUNDERLINK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define AF2_THUNDERBOLT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define AF2_INIT_DONE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define AF2_INT_PENDING 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define AF2_TIMER_TICK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define AF2_IRQ_CLAIMED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define AF2_MSI_ENABLED 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) atomic_t disable_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) atomic_t dis_ints_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u32 volatile *outbound_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct list_head avail_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) spinlock_t request_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spinlock_t sg_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spinlock_t mem_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct list_head free_sg_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct esas2r_mem_desc *sg_list_mds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct list_head active_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct list_head defer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct esas2r_request **req_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u16 prev_dev_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 heartbeat_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define ESAS2R_HEARTBEAT_TIME (3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 chip_uptime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define ESAS2R_CHP_UPTIME_MAX (60000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define ESAS2R_CHP_UPTIME_CNT (20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u64 uncached_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 *uncached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct esas2r_sas_nvram *nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct esas2r_request general_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u8 init_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define ESAS2R_INIT_MSG_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define ESAS2R_INIT_MSG_INIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define ESAS2R_INIT_MSG_GET_INIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define ESAS2R_INIT_MSG_REINIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u16 cmd_ref_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 fw_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 chip_init_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ESAS2R_CHPRST_TIME (180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define ESAS2R_CHPRST_WAIT_TIME (2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 last_tick_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 window_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RQBUILDSGL build_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct esas2r_request *first_ae_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 list_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 last_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 last_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u16 max_vdareq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u16 disc_wait_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct esas2r_mem_desc inbound_list_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct esas2r_mem_desc outbound_list_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct esas2r_disc_context disc_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u8 *disc_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 disc_start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 disc_wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 flash_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) char flash_rev[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) char fw_rev[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) char image_type[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct esas2r_flash_context flash_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 num_targets_backend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 ioctl_tunnel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct pci_dev *pcid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct esas2r_firmware firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) wait_queue_head_t nvram_waiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int nvram_command_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) wait_queue_head_t fm_api_waiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int fm_api_command_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) wait_queue_head_t vda_waiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int vda_command_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u8 *vda_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u64 ppvda_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define VDA_BUFFER_HEADER_SZ (offsetof(struct atto_ioctl_vda, data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define VDA_MAX_BUFFER_SIZE (0x40000 + VDA_BUFFER_HEADER_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) wait_queue_head_t fs_api_waiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int fs_api_command_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u64 ppfs_api_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u8 *fs_api_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 fs_api_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) wait_queue_head_t buffered_ioctl_waiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int buffered_ioctl_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int uncached_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct workqueue_struct *fw_event_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct list_head fw_event_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) spinlock_t fw_event_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u8 fw_events_off; /* if '1', then ignore events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) char fw_event_q_name[ESAS2R_KOBJ_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * intr_mode stores the interrupt mode currently being used by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * adapter. it is based on the interrupt_mode module parameter, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * can be changed based on the ability (or not) to utilize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * mode requested by the parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int intr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define INTR_MODE_LEGACY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define INTR_MODE_MSI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define INTR_MODE_MSIX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct esas2r_sg_context fm_api_sgc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 *save_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct list_head vrq_mds_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct esas2r_mem_desc *vrq_mds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int num_vrqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct mutex fm_api_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct mutex fs_api_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct semaphore nvram_semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct atto_ioctl *local_atto_ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u8 fw_coredump_buff[ESAS2R_FWCOREDUMP_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned int sysfs_fw_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned int sysfs_fs_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unsigned int sysfs_vda_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unsigned int sysfs_hw_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned int sysfs_live_nvram_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int sysfs_default_nvram_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * Function Declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * SCSI functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) const char *esas2r_info(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int esas2r_write_params(struct esas2r_adapter *a, struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct esas2r_sas_nvram *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int esas2r_ioctl_handler(void *hostdata, unsigned int cmd, void __user *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int esas2r_ioctl(struct scsi_device *dev, unsigned int cmd, void __user *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u8 handle_hba_ioctl(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct atto_ioctl *ioctl_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int esas2r_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int esas2r_show_info(struct seq_file *m, struct Scsi_Host *sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) long esas2r_proc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* SCSI error handler (eh) functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int esas2r_eh_abort(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int esas2r_device_reset(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int esas2r_host_reset(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int esas2r_bus_reset(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int esas2r_target_reset(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Internal functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int esas2r_read_fw(struct esas2r_adapter *a, char *buf, long off, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int esas2r_write_fw(struct esas2r_adapter *a, const char *buf, long off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int esas2r_read_vda(struct esas2r_adapter *a, char *buf, long off, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int esas2r_write_vda(struct esas2r_adapter *a, const char *buf, long off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int esas2r_read_fs(struct esas2r_adapter *a, char *buf, long off, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int esas2r_write_fs(struct esas2r_adapter *a, const char *buf, long off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) void esas2r_adapter_tasklet(unsigned long context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) irqreturn_t esas2r_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) irqreturn_t esas2r_msi_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) void esas2r_kickoff_timer(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int esas2r_suspend(struct pci_dev *pcid, pm_message_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int esas2r_resume(struct pci_dev *pcid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) void esas2r_fw_event_off(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) void esas2r_fw_event_on(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bool esas2r_nvram_write(struct esas2r_adapter *a, struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct esas2r_sas_nvram *nvram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) void esas2r_nvram_get_defaults(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct esas2r_sas_nvram *nvram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void esas2r_complete_request_cb(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) void esas2r_reset_detected(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) void esas2r_target_state_changed(struct esas2r_adapter *ha, u16 targ_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int esas2r_req_status_to_error(u8 req_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) void esas2r_kill_adapter(int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) void esas2r_free_request(struct esas2r_adapter *a, struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct esas2r_request *esas2r_alloc_request(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 esas2r_get_uncached_size(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) void **uncached_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) bool esas2r_check_adapter(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) void esas2r_start_request(struct esas2r_adapter *a, struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bool esas2r_send_task_mgmt(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct esas2r_request *rqaux, u8 task_mgt_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) void esas2r_do_tasklet_tasks(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) void esas2r_adapter_interrupt(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void esas2r_do_deferred_processes(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) void esas2r_reset_bus(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) void esas2r_reset_adapter(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) void esas2r_timer_tick(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) const char *esas2r_get_model_name(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) const char *esas2r_get_model_name_short(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u32 esas2r_stall_execution(struct esas2r_adapter *a, u32 start_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) u32 *delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) void esas2r_build_flash_req(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u8 sub_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) u8 cksum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void esas2r_build_mgt_req(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) u8 sub_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u8 scan_gen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) u16 dev_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) void esas2r_build_ae_req(struct esas2r_adapter *a, struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) void esas2r_build_cli_req(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 cmd_rsp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) void esas2r_build_ioctl_req(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u8 sub_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) void esas2r_build_cfg_req(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u8 sub_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) void esas2r_power_down(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) void esas2r_wait_request(struct esas2r_adapter *a, struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 esas2r_map_data_window(struct esas2r_adapter *a, u32 addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) bool esas2r_process_fs_ioctl(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct esas2r_ioctl_fs *fs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) bool esas2r_read_flash_block(struct esas2r_adapter *a, void *to, u32 from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) bool esas2r_read_mem_block(struct esas2r_adapter *a, void *to, u32 from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bool esas2r_fm_api(struct esas2r_adapter *a, struct esas2r_flash_img *fi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct esas2r_request *rq, struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) void esas2r_force_interrupt(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) void esas2r_local_start_request(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) void esas2r_process_adapter_reset(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) void esas2r_complete_request(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) void esas2r_dummy_complete(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) void esas2r_ae_complete(struct esas2r_adapter *a, struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) void esas2r_start_vda_request(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) bool esas2r_read_flash_rev(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) bool esas2r_read_image_type(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) bool esas2r_nvram_read_direct(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) bool esas2r_nvram_validate(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) void esas2r_nvram_set_defaults(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) bool esas2r_print_flash_rev(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) void esas2r_send_reset_ae(struct esas2r_adapter *a, bool pwr_mgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) bool esas2r_init_msgs(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) bool esas2r_is_adapter_present(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) void esas2r_nuxi_mgt_data(u8 function, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) void esas2r_nuxi_cfg_data(u8 function, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) void esas2r_nuxi_ae_data(union atto_vda_ae *ae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) void esas2r_reset_chip(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) void esas2r_log_request_failure(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) void esas2r_polled_interrupt(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) bool esas2r_ioreq_aborted(struct esas2r_adapter *a, struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) u8 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) bool esas2r_build_sg_list_sge(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bool esas2r_build_sg_list_prd(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) void esas2r_targ_db_initialize(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) void esas2r_targ_db_remove_all(struct esas2r_adapter *a, bool notify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) void esas2r_targ_db_report_changes(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct esas2r_target *esas2r_targ_db_add_raid(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct esas2r_disc_context *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct esas2r_target *esas2r_targ_db_add_pthru(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct esas2r_disc_context *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u8 *ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u8 ident_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) void esas2r_targ_db_remove(struct esas2r_adapter *a, struct esas2r_target *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct esas2r_target *esas2r_targ_db_find_by_sas_addr(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u64 *sas_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct esas2r_target *esas2r_targ_db_find_by_ident(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) void *identifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u8 ident_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) u16 esas2r_targ_db_find_next_present(struct esas2r_adapter *a, u16 target_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct esas2r_target *esas2r_targ_db_find_by_virt_id(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) u16 virt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u16 esas2r_targ_db_get_tgt_cnt(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) void esas2r_disc_initialize(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) void esas2r_disc_start_waiting(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) void esas2r_disc_check_for_work(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) void esas2r_disc_check_complete(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) void esas2r_disc_queue_event(struct esas2r_adapter *a, u8 disc_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) bool esas2r_disc_start_port(struct esas2r_adapter *a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) void esas2r_disc_local_start_request(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct esas2r_request *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) bool esas2r_process_vda_ioctl(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct atto_ioctl_vda *vi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct esas2r_sg_context *sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) void esas2r_queue_fw_event(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) enum fw_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Inline functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Allocate a chip scatter/gather list entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static inline struct esas2r_mem_desc *esas2r_alloc_sgl(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct list_head *sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct esas2r_mem_desc *result = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) spin_lock_irqsave(&a->sg_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (likely(!list_empty(&a->free_sg_list_head))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) sgl = a->free_sg_list_head.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) result = list_entry(sgl, struct esas2r_mem_desc, next_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) list_del_init(sgl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) spin_unlock_irqrestore(&a->sg_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Initialize a scatter/gather context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static inline void esas2r_sgc_init(struct esas2r_sg_context *sgc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct atto_vda_sge *first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) sgc->adapter = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) sgc->first_req = rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * set the limit pointer such that an SGE pointer above this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * would be the first one to overflow the SGL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) sgc->sge.a64.limit = (struct atto_vda_sge *)((u8 *)rq->vrq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) + (sizeof(union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) atto_vda_req) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) - sizeof(struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) atto_vda_sge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) sgc->sge.a64.last =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) sgc->sge.a64.curr = first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rq->vrq->scsi.sg_list_offset = (u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ((u8 *)first -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) (u8 *)rq->vrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) sgc->sge.a64.last =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) sgc->sge.a64.curr = &rq->vrq->scsi.u.sge[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) rq->vrq->scsi.sg_list_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) (u8)offsetof(struct atto_vda_scsi_req, u.sge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) sgc->sge.a64.chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static inline void esas2r_rq_init_request(struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) union atto_vda_req *vrq = rq->vrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) INIT_LIST_HEAD(&rq->sg_table_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rq->data_buf = (void *)(vrq + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) rq->interrupt_cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) rq->comp_cb = esas2r_complete_request_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) rq->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rq->timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) rq->req_stat = RS_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) rq->req_type = RT_INI_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* clear the outbound response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) rq->func_rsp.dwords[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rq->func_rsp.dwords[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * clear the size of the VDA request. esas2r_build_sg_list() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * only allow the size of the request to grow. there are some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * management requests that go through there twice and the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * time through sets a smaller request size. if this is not modified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * at all we'll set it to the size of the entire VDA request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rq->vda_req_sz = RQ_SIZE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* req_table entry should be NULL at this point - if not, halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (a->req_table[LOWORD(vrq->scsi.handle)]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) esas2r_bugon();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* fill in the table for this handle so we can get back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) a->req_table[LOWORD(vrq->scsi.handle)] = rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * add a reference number to the handle to make it unique (until it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * wraps of course) while preserving the least significant word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) vrq->scsi.handle = (a->cmd_ref_no++ << 16) | (u16)vrq->scsi.handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * the following formats a SCSI request. the caller can override as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * necessary. clear_vda_request can be called to clear the VDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * request for another type of request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) vrq->scsi.function = VDA_FUNC_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) vrq->scsi.sense_len = SENSE_DATA_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* clear out sg_list_offset and chain_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) vrq->scsi.sg_list_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) vrq->scsi.chain_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) vrq->scsi.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) vrq->scsi.reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* set the sense buffer to be the data payload buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) vrq->scsi.ppsense_buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) = cpu_to_le64(rq->vrq_md->phys_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sizeof(union atto_vda_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static inline void esas2r_rq_free_sg_lists(struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (list_empty(&rq->sg_table_head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) spin_lock_irqsave(&a->sg_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) list_splice_tail_init(&rq->sg_table_head, &a->free_sg_list_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) spin_unlock_irqrestore(&a->sg_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static inline void esas2r_rq_destroy_request(struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) esas2r_rq_free_sg_lists(rq, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) a->req_table[LOWORD(rq->vrq->scsi.handle)] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) rq->data_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static inline bool esas2r_is_tasklet_pending(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return test_bit(AF_BUSRST_NEEDED, &a->flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) test_bit(AF_BUSRST_DETECTED, &a->flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) test_bit(AF_CHPRST_NEEDED, &a->flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) test_bit(AF_CHPRST_DETECTED, &a->flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) test_bit(AF_PORT_CHANGE, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * Build the scatter/gather list for an I/O request according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * specifications placed in the esas2r_sg_context. The caller must initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * struct esas2r_sg_context prior to the initial call by calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * esas2r_sgc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static inline bool esas2r_build_sg_list(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct esas2r_request *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct esas2r_sg_context *sgc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (unlikely(le32_to_cpu(rq->vrq->scsi.length) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return (*a->build_sgl)(a, sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static inline void esas2r_disable_chip_interrupts(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (atomic_inc_return(&a->dis_ints_cnt) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) esas2r_write_register_dword(a, MU_INT_MASK_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ESAS2R_INT_DIS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static inline void esas2r_enable_chip_interrupts(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (atomic_dec_return(&a->dis_ints_cnt) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) esas2r_write_register_dword(a, MU_INT_MASK_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ESAS2R_INT_ENB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Schedule a TASKLET to perform non-interrupt tasks that may require delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * or long completion times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static inline void esas2r_schedule_tasklet(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* make sure we don't schedule twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (!test_and_set_bit(AF_TASKLET_SCHEDULED, &a->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) tasklet_hi_schedule(&a->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static inline void esas2r_enable_heartbeat(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!test_bit(AF_DEGRADED_MODE, &a->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) !test_bit(AF_CHPRST_PENDING, &a->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) (a->nvram->options2 & SASNVR2_HEARTBEAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) set_bit(AF_HEARTBEAT_ENB, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) clear_bit(AF_HEARTBEAT_ENB, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static inline void esas2r_disable_heartbeat(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) clear_bit(AF_HEARTBEAT_ENB, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) clear_bit(AF_HEARTBEAT, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Set the initial state for resetting the adapter on the next pass through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * esas2r_do_deferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static inline void esas2r_local_reset_adapter(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) esas2r_disable_heartbeat(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) set_bit(AF_CHPRST_NEEDED, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) set_bit(AF_CHPRST_PENDING, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) set_bit(AF_DISC_PENDING, &a->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* See if an interrupt is pending on the adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static inline bool esas2r_adapter_interrupt_pending(struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u32 intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (a->int_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) intstat = esas2r_read_register_dword(a, MU_INT_STATUS_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if ((intstat & a->int_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) esas2r_disable_chip_interrupts(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) a->int_stat = intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) a->int_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static inline u16 esas2r_targ_get_id(struct esas2r_target *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct esas2r_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return (u16)(uintptr_t)(t - a->targetdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Build and start an asynchronous event request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static inline void esas2r_start_ae_request(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct esas2r_request *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) esas2r_build_ae_req(a, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) spin_lock_irqsave(&a->queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) esas2r_start_vda_request(a, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) spin_unlock_irqrestore(&a->queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static inline void esas2r_comp_list_drain(struct esas2r_adapter *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct list_head *comp_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct esas2r_request *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct list_head *element, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) list_for_each_safe(element, next, comp_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) rq = list_entry(element, struct esas2r_request, comp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) list_del_init(element);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) esas2r_complete_request(a, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* sysfs handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) extern struct bin_attribute bin_attr_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) extern struct bin_attribute bin_attr_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) extern struct bin_attribute bin_attr_vda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) extern struct bin_attribute bin_attr_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) extern struct bin_attribute bin_attr_live_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) extern struct bin_attribute bin_attr_default_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #endif /* ESAS2R_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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