^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) dpti.c - description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) begin : Thu Sep 7 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) copyright : (C) 2000 by Adaptec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) July 30, 2001 First version being submitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) for inclusion in the kernel. V2.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) See Documentation/scsi/dpti.rst for history, notes, license info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) and credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Sat Dec 20 2003 Go Taniguchi <go@turbolinux.co.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - Support 2.6 kernel and DMA-mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - ioctl fix for raid tools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - use schedule_timeout in long long loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*#define DEBUG 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*#define UARTDELAY 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_AUTHOR("Deanna Bonds, with _lots_ of help from Mark Salyzyn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DESCRIPTION("Adaptec I2O RAID Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/ioctl.h> /* For SCSI-Passthrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/slab.h> /* for kmalloc() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/pci.h> /* for PCI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/delay.h> /* for udelay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/kernel.h> /* for printk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/processor.h> /* for boot_cpu_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <asm/io.h> /* for virt_to_bus, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "dpt/dptsig.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "dpti.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Create a binary signature - this is read by dptsig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Needed for our management apps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static DEFINE_MUTEX(adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static dpt_sig_S DPTI_sig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {'d', 'P', 't', 'S', 'i', 'G'}, SIG_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PROC_INTEL, PROC_386 | PROC_486 | PROC_PENTIUM | PROC_SEXIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #elif defined(__ia64__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PROC_INTEL, PROC_IA64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #elif defined(__sparc__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PROC_ULTRASPARC, PROC_ULTRASPARC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #elif defined(__alpha__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PROC_ALPHA, PROC_ALPHA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (-1),(-1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FT_HBADRVR, 0, OEM_DPT, OS_LINUX, CAP_OVERLAP, DEV_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADF_ALL_SC5, 0, 0, DPT_VERSION, DPT_REVISION, DPT_SUBREVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DPT_MONTH, DPT_DAY, DPT_YEAR, "Adaptec Linux I2O RAID Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Globals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static DEFINE_MUTEX(adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct i2o_sys_tbl *sys_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static dma_addr_t sys_tbl_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int sys_tbl_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int sys_tbl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static adpt_hba* hba_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int hba_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct class *adpt_sysfs_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static long adpt_unlocked_ioctl(struct file *, unsigned int, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static long compat_adpt_ioctl(struct file *, unsigned int, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct file_operations adpt_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .unlocked_ioctl = adpt_unlocked_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .open = adpt_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .release = adpt_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .compat_ioctl = compat_adpt_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .llseek = noop_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Structures and definitions for synchronous message posting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * See adpt_i2o_post_wait() for description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct adpt_i2o_post_wait_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) adpt_wait_queue_head_t *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct adpt_i2o_post_wait_data *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct adpt_i2o_post_wait_data *adpt_post_wait_queue = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static u32 adpt_post_wait_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static DEFINE_SPINLOCK(adpt_post_wait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline int dpt_dma64(adpt_hba *pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return (sizeof(dma_addr_t) > 4 && (pHba)->dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline u32 dma_high(dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline u32 dma_low(dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return (u32)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static u8 adpt_read_blink_led(adpt_hba* host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (host->FwDebugBLEDflag_P) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if( readb(host->FwDebugBLEDflag_P) == 0xbc ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return readb(host->FwDebugBLEDvalue_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Scsi host template interface functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct pci_device_id dptids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { PCI_DPT_VENDOR_ID, PCI_DPT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { PCI_DPT_VENDOR_ID, PCI_DPT_RAPTOR_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DEVICE_TABLE(pci,dptids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int adpt_detect(struct scsi_host_template* sht)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct pci_dev *pDev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) adpt_hba *pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) adpt_hba *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINFO("Detecting Adaptec I2O RAID controllers...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* search for all Adatpec I2O RAID cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) while ((pDev = pci_get_device( PCI_DPT_VENDOR_ID, PCI_ANY_ID, pDev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if(pDev->device == PCI_DPT_DEVICE_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pDev->device == PCI_DPT_RAPTOR_DEVICE_ID){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if(adpt_install_hba(sht, pDev) ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PERROR("Could not Init an I2O RAID device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PERROR("Will not try to detect others.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return hba_count-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pci_dev_get(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* In INIT state, Activate IOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (pHba = hba_chain; pHba; pHba = next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) next = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) // Activate does get status , init outbound, and get hrt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (adpt_i2o_activate_hba(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Active IOPs in HOLD state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rebuild_sys_tab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (hba_chain == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * If build_sys_table fails, we kill everything and bail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * as we can't init the IOPs w/o a system table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (adpt_i2o_build_sys_table() < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) adpt_i2o_sys_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PDEBUG("HBA's in HOLD state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* If IOP don't get online, we need to rebuild the System table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (adpt_i2o_online_hba(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto rebuild_sys_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Active IOPs now in OPERATIONAL state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PDEBUG("HBA's in OPERATIONAL state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) printk("dpti: If you have a lot of devices this could take a few minutes.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (pHba = hba_chain; pHba; pHba = next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) next = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) printk(KERN_INFO"%s: Reading the hardware resource table.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (adpt_i2o_lct_get(pHba) < 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (adpt_i2o_parse_lct(pHba) < 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) adpt_inquiry(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) adpt_sysfs_class = class_create(THIS_MODULE, "dpt_i2o");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (IS_ERR(adpt_sysfs_class)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) printk(KERN_WARNING"dpti: unable to create dpt_i2o class\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) adpt_sysfs_class = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (pHba = hba_chain; pHba; pHba = next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) next = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (adpt_scsi_host_alloc(pHba, sht) < 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pHba->initialized = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pHba->state &= ~DPTI_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (adpt_sysfs_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct device *dev = device_create(adpt_sysfs_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) NULL, MKDEV(DPTI_I2O_MAJOR, pHba->unit), NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "dpti%d", pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (IS_ERR(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) printk(KERN_WARNING"dpti%d: unable to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "create device in dpt_i2o class\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) // Register our control device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) // nodes will need to be created in /dev to access this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) // the nodes can not be created from within the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (hba_count && register_chrdev(DPTI_I2O_MAJOR, DPT_DRIVER, &adpt_fops)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) adpt_i2o_sys_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return hba_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void adpt_release(adpt_hba *pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct Scsi_Host *shost = pHba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) scsi_remove_host(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) // adpt_i2o_quiesce_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void adpt_inquiry(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 msg[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 *mptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 *lenptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int scsidir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 reqlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8* buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 scb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) s32 rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) memset(msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) buf = dma_alloc_coherent(&pHba->pDev->dev, 80, &addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if(!buf){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) printk(KERN_ERR"%s: Could not allocate buffer\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) memset((void*)buf, 0, 36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) len = 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) direction = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) scsidir =0x40000000; // DATA IN (iop<--dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (dpt_dma64(pHba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reqlen = 17; // SINGLE SGE, 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reqlen = 14; // SINGLE SGE, 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Stick the headers on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) msg[0] = reqlen<<16 | SGL_OFFSET_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) msg[1] = (0xff<<24|HOST_TID<<12|ADAPTER_TID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) // Adaptec/DPT Private stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) msg[4] = I2O_CMD_SCSI_EXEC|DPT_ORGANIZATION_ID<<16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) msg[5] = ADAPTER_TID | 1<<16 /* Interpret*/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Direction, disconnect ok | sense data | simple queue , CDBLen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) // I2O_SCB_FLAG_ENABLE_DISCONNECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) // I2O_SCB_FLAG_SIMPLE_QUEUE_TAG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) // I2O_SCB_FLAG_SENSE_DATA_IN_MESSAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) msg[6] = scsidir|0x20a00000| 6 /* cmd len*/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mptr=msg+7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) memset(scb, 0, sizeof(scb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) // Write SCSI command into the message - always 16 byte block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) scb[0] = INQUIRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) scb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) scb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) scb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) scb[4] = 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) scb[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) // Don't care about the rest of scb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) memcpy(mptr, scb, sizeof(scb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mptr+=4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) lenptr=mptr++; /* Remember me - fill in when we know */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Now fill in the SGList and command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *lenptr = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (dpt_dma64(pHba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *mptr++ = (0x7C<<24)+(2<<16)+0x02; /* Enable 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *mptr++ = 1 << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *mptr++ = 0xD0000000|direction|len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *mptr++ = dma_low(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *mptr++ = dma_high(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *mptr++ = 0xD0000000|direction|len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *mptr++ = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) // Send it on it's way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rcode = adpt_i2o_post_wait(pHba, msg, reqlen<<2, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (rcode != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sprintf(pHba->detail, "Adaptec I2O RAID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) printk(KERN_INFO "%s: Inquiry Error (%d)\n",pHba->name,rcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (rcode != -ETIME && rcode != -EINTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dma_free_coherent(&pHba->pDev->dev, 80, buf, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) memset(pHba->detail, 0, sizeof(pHba->detail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) memcpy(&(pHba->detail), "Vendor: Adaptec ", 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) memcpy(&(pHba->detail[16]), " Model: ", 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) memcpy(&(pHba->detail[24]), (u8*) &buf[16], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) memcpy(&(pHba->detail[40]), " FW: ", 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) memcpy(&(pHba->detail[44]), (u8*) &buf[32], 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pHba->detail[48] = '\0'; /* precautionary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dma_free_coherent(&pHba->pDev->dev, 80, buf, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int adpt_slave_configure(struct scsi_device * device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct Scsi_Host *host = device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (host->can_queue && device->tagged_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) scsi_change_queue_depth(device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) host->can_queue - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int adpt_queue_lck(struct scsi_cmnd * cmd, void (*done) (struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) adpt_hba* pHba = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct adpt_device* pDev = NULL; /* dpt per device information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * SCSI REQUEST_SENSE commands will be executed automatically by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Host Adapter for any errors, so they should not be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * explicitly unless the Sense Data is zero indicating that no error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((cmd->cmnd[0] == REQUEST_SENSE) && (cmd->sense_buffer[0] != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cmd->result = (DID_OK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pHba = (adpt_hba*)cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!pHba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if ((pHba->state) & DPTI_STATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) // TODO if the cmd->device if offline then I may need to issue a bus rescan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) // followed by a get_lct to see if the device is there anymore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if((pDev = (struct adpt_device*) (cmd->device->hostdata)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * First command request for this device. Set up a pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * to the device structure. This should be a TEST_UNIT_READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * command from scan_scsis_single.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((pDev = adpt_find_device(pHba, (u32)cmd->device->channel, (u32)cmd->device->id, cmd->device->lun)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) // TODO: if any luns are at this bus, scsi id then fake a TEST_UNIT_READY and INQUIRY response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) // with type 7F (for all luns less than the max for this bus,id) so the lun scan will continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cmd->result = (DID_NO_CONNECT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cmd->device->hostdata = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pDev->pScsi_dev = cmd->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * If we are being called from when the device is being reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * delay processing of the command until later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (pDev->state & DPTI_DEV_RESET ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return adpt_scsi_to_i2o(pHba, cmd, pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static DEF_SCSI_QCMD(adpt_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int adpt_bios_param(struct scsi_device *sdev, struct block_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sector_t capacity, int geom[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int heads=-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int sectors=-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int cylinders=-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) // *** First lets set the default geometry ****
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) // If the capacity is less than ox2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (capacity < 0x2000 ) { // floppy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) heads = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sectors = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) // else if between 0x2000 and 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if (capacity < 0x20000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) heads = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sectors = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) // else if between 0x20000 and 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else if (capacity < 0x40000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) heads = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) // else if between 0x4000 and 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else if (capacity < 0x80000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) heads = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) // else if greater than 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) heads = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cylinders = sector_div(capacity, heads * sectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) // Special case if CDROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if(sdev->type == 5) { // CDROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) heads = 252;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cylinders = 1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) geom[0] = heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) geom[1] = sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) geom[2] = cylinders;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PDEBUG("adpt_bios_param: exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const char *adpt_info(struct Scsi_Host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pHba = (adpt_hba *) host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return (char *) (pHba->detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int adpt_show_info(struct seq_file *m, struct Scsi_Host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct adpt_device* d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) // Find HBA (host bus adapter) we are looking for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (pHba->host == host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break; /* found adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (pHba == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) host = pHba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) seq_printf(m, "Adaptec I2O RAID Driver Version: %s\n\n", DPT_I2O_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) seq_printf(m, "%s\n", pHba->detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) seq_printf(m, "SCSI Host=scsi%d Control Node=/dev/%s irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pHba->host->host_no, pHba->name, host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) seq_printf(m, "\tpost fifo size = %d\n\treply fifo size = %d\n\tsg table size = %d\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) host->can_queue, (int) pHba->reply_fifo_size , host->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) seq_puts(m, "Devices:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for(chan = 0; chan < MAX_CHANNEL; chan++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for(id = 0; id < MAX_ID; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) d = pHba->channel[chan].device[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) while(d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) seq_printf(m,"\t%-24.24s", d->pScsi_dev->vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) seq_printf(m," Rev: %-8.8s\n", d->pScsi_dev->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unit = d->pI2o_dev->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) seq_printf(m, "\tTID=%d, (Channel=%d, Target=%d, Lun=%llu) (%s)\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unit, (int)d->scsi_channel, (int)d->scsi_id, d->scsi_lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) scsi_device_online(d->pScsi_dev)? "online":"offline");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) d = d->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Turn a pointer to ioctl reply data into an u32 'context'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static u32 adpt_ioctl_to_context(adpt_hba * pHba, void *reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #if BITS_PER_LONG == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return (u32)(unsigned long)reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 nr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) spin_lock_irqsave(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) nr = ARRAY_SIZE(pHba->ioctl_reply_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (i = 0; i < nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (pHba->ioctl_reply_context[i] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pHba->ioctl_reply_context[i] = reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) spin_unlock_irqrestore(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (i >= nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) printk(KERN_WARNING"%s: Too many outstanding "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "ioctl commands\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return (u32)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Go from an u32 'context' to a pointer to ioctl reply data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void *adpt_ioctl_from_context(adpt_hba *pHba, u32 context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #if BITS_PER_LONG == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return (void *)(unsigned long)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) void *p = pHba->ioctl_reply_context[context];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pHba->ioctl_reply_context[context] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*===========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Error Handling routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *===========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int adpt_abort(struct scsi_cmnd * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) adpt_hba* pHba = NULL; /* host bus adapter structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct adpt_device* dptdevice; /* dpt per device information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 msg[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pHba = (adpt_hba*) cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) printk(KERN_INFO"%s: Trying to Abort\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((dptdevice = (void*) (cmd->device->hostdata)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) printk(KERN_ERR "%s: Unable to abort: No device in cmnd\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) memset(msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) msg[1] = I2O_CMD_SCSI_ABORT<<24|HOST_TID<<12|dptdevice->tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) msg[3]= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Add 1 to avoid firmware treating it as invalid command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msg[4] = cmd->request->tag + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_lock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rcode = adpt_i2o_post_wait(pHba, msg, sizeof(msg), FOREVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) spin_unlock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (rcode != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if(rcode == -EOPNOTSUPP ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) printk(KERN_INFO"%s: Abort cmd not supported\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) printk(KERN_INFO"%s: Abort failed.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) printk(KERN_INFO"%s: Abort complete.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define I2O_DEVICE_RESET 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) // This is the same for BLK and SCSI devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) // NOTE this is wrong in the i2o.h definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) // This is not currently supported by our adapter but we issue it anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int adpt_device_reset(struct scsi_cmnd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 msg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int old_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct adpt_device* d = cmd->device->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pHba = (void*) cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) printk(KERN_INFO"%s: Trying to reset device\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) printk(KERN_INFO"%s: Reset Device: Device Not found\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) memset(msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) msg[1] = (I2O_DEVICE_RESET<<24|HOST_TID<<12|d->tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) spin_lock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) old_state = d->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) d->state |= DPTI_DEV_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rcode = adpt_i2o_post_wait(pHba, msg,sizeof(msg), FOREVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) d->state = old_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) spin_unlock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (rcode != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if(rcode == -EOPNOTSUPP ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) printk(KERN_INFO"%s: Device reset not supported\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) printk(KERN_INFO"%s: Device reset failed\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) printk(KERN_INFO"%s: Device reset successful\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define I2O_HBA_BUS_RESET 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) // This version of bus reset is called by the eh_error handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int adpt_bus_reset(struct scsi_cmnd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 msg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pHba = (adpt_hba*)cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) memset(msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) printk(KERN_WARNING"%s: Bus reset: SCSI Bus %d: tid: %d\n",pHba->name, cmd->device->channel,pHba->channel[cmd->device->channel].tid );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) msg[1] = (I2O_HBA_BUS_RESET<<24|HOST_TID<<12|pHba->channel[cmd->device->channel].tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) spin_lock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rcode = adpt_i2o_post_wait(pHba, msg,sizeof(msg), FOREVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) spin_unlock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (rcode != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) printk(KERN_WARNING"%s: Bus reset failed.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) printk(KERN_WARNING"%s: Bus reset success.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) // This version of reset is called by the eh_error_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int __adpt_reset(struct scsi_cmnd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pHba = (adpt_hba*)cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) strncpy(name, pHba->name, sizeof(name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) printk(KERN_WARNING"%s: Hba Reset: scsi id %d: tid: %d\n", name, cmd->device->channel, pHba->channel[cmd->device->channel].tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rcode = adpt_hba_reset(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if(rcode == 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) printk(KERN_WARNING"%s: HBA reset complete\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) printk(KERN_WARNING"%s: HBA reset failed (%x)\n", name, rcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int adpt_reset(struct scsi_cmnd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_lock_irq(cmd->device->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) rc = __adpt_reset(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) spin_unlock_irq(cmd->device->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) // This version of reset is called by the ioctls and indirectly from eh_error_handler via adpt_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int adpt_hba_reset(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pHba->state |= DPTI_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) // Activate does get status , init outbound, and get hrt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if ((rcode=adpt_i2o_activate_hba(pHba)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) printk(KERN_ERR "%s: Could not activate\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if ((rcode=adpt_i2o_build_sys_table()) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PDEBUG("%s: in HOLD state\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if ((rcode=adpt_i2o_online_hba(pHba)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PDEBUG("%s: in OPERATIONAL state\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if ((rcode=adpt_i2o_lct_get(pHba)) < 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if ((rcode=adpt_i2o_reparse_lct(pHba)) < 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pHba->state &= ~DPTI_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) scsi_host_complete_all_commands(pHba->host, DID_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0; /* return success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*===========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) *===========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static void adpt_i2o_sys_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) adpt_hba *pHba, *pNext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct adpt_i2o_post_wait_data *p1, *old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) printk(KERN_INFO "Shutting down Adaptec I2O controllers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) printk(KERN_INFO " This could take a few minutes if there are many devices attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Delete all IOPs from the controller chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* They should have already been released by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * scsi-core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) for (pHba = hba_chain; pHba; pHba = pNext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pNext = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Remove any timedout entries from the wait queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) // spin_lock_irqsave(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Nothing should be outstanding at this point so just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * free them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) for(p1 = adpt_post_wait_queue; p1;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) old = p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) p1 = p1->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) kfree(old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) // spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) adpt_post_wait_queue = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) printk(KERN_INFO "Adaptec I2O controllers down.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int adpt_install_hba(struct scsi_host_template* sht, struct pci_dev* pDev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) adpt_hba* pHba = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) adpt_hba* p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ulong base_addr0_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ulong base_addr1_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 hba_map0_area_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 hba_map1_area_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) void __iomem *base_addr_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) void __iomem *msg_addr_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int dma64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int raptorFlag = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if(pci_enable_device(pDev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (pci_request_regions(pDev, "dpt_i2o")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PERROR("dpti: adpt_config_hba: pci request region failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pci_set_master(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * See if we should enable dma64 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (sizeof(dma_addr_t) > 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dma_get_required_mask(&pDev->dev) > DMA_BIT_MASK(32) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma_set_mask(&pDev->dev, DMA_BIT_MASK(64)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dma64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!dma64 && dma_set_mask(&pDev->dev, DMA_BIT_MASK(32)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* adapter only supports message blocks below 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dma_set_coherent_mask(&pDev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) base_addr0_phys = pci_resource_start(pDev,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hba_map0_area_size = pci_resource_len(pDev,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) // Check if standard PCI card or single BAR Raptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if(pDev->device == PCI_DPT_DEVICE_ID){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if(pDev->subsystem_device >=0xc032 && pDev->subsystem_device <= 0xc03b){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) // Raptor card with this device id needs 4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) hba_map0_area_size = 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } else { // Not Raptor - it is a PCI card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if(hba_map0_area_size > 0x100000 ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) hba_map0_area_size = 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) } else {// Raptor split BAR config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) // Use BAR1 in this configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) base_addr1_phys = pci_resource_start(pDev,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) hba_map1_area_size = pci_resource_len(pDev,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) raptorFlag = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #if BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * The original Adaptec 64 bit driver has this comment here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * "x86_64 machines need more optimal mappings"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * I assume some HBAs report ridiculously large mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * and we need to limit them on platforms with IOMMUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (raptorFlag == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (hba_map0_area_size > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) hba_map0_area_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (hba_map1_area_size > 524288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) hba_map1_area_size = 524288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (hba_map0_area_size > 524288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) hba_map0_area_size = 524288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) base_addr_virt = ioremap(base_addr0_phys,hba_map0_area_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!base_addr_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pci_release_regions(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PERROR("dpti: adpt_config_hba: io remap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if(raptorFlag == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) msg_addr_virt = ioremap(base_addr1_phys, hba_map1_area_size );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!msg_addr_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PERROR("dpti: adpt_config_hba: io remap failed on BAR1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) iounmap(base_addr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pci_release_regions(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) msg_addr_virt = base_addr_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) // Allocate and zero the data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pHba = kzalloc(sizeof(adpt_hba), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!pHba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (msg_addr_virt != base_addr_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) iounmap(msg_addr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) iounmap(base_addr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pci_release_regions(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if(hba_chain != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) for(p = hba_chain; p->next; p = p->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) p->next = pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) hba_chain = pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pHba->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pHba->unit = hba_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) sprintf(pHba->name, "dpti%d", hba_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) hba_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pHba->pDev = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pHba->base_addr_phys = base_addr0_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) // Set up the Virtual Base Address of the I2O Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pHba->base_addr_virt = base_addr_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pHba->msg_addr_virt = msg_addr_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pHba->irq_mask = base_addr_virt+0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pHba->post_port = base_addr_virt+0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pHba->reply_port = base_addr_virt+0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pHba->hrt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pHba->lct = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pHba->lct_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pHba->status_block = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pHba->post_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pHba->state = DPTI_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pHba->pDev = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pHba->devices = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pHba->dma64 = dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) // Initializing the spinlocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) spin_lock_init(&pHba->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) spin_lock_init(&adpt_post_wait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if(raptorFlag == 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) printk(KERN_INFO "Adaptec I2O RAID controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) " %d at %p size=%x irq=%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) hba_count-1, base_addr_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) hba_map0_area_size, pDev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dma64 ? " (64-bit DMA)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) printk(KERN_INFO"Adaptec I2O RAID controller %d irq=%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) hba_count-1, pDev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dma64 ? " (64-bit DMA)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) printk(KERN_INFO" BAR0 %p - size= %x\n",base_addr_virt,hba_map0_area_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) printk(KERN_INFO" BAR1 %p - size= %x\n",msg_addr_virt,hba_map1_area_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (request_irq (pDev->irq, adpt_isr, IRQF_SHARED, pHba->name, pHba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) printk(KERN_ERR"%s: Couldn't register IRQ %d\n", pHba->name, pDev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) adpt_i2o_delete_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void adpt_i2o_delete_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) adpt_hba* p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) adpt_hba* p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct i2o_device* d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct i2o_device* next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct adpt_device* pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct adpt_device* pNext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if(pHba->host){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) free_irq(pHba->host->irq, pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) p2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) for( p1 = hba_chain; p1; p2 = p1,p1=p1->next){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if(p1 == pHba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if(p2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) p2->next = p1->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) hba_chain = p1->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) hba_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) iounmap(pHba->base_addr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pci_release_regions(pHba->pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if(pHba->msg_addr_virt != pHba->base_addr_virt){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) iounmap(pHba->msg_addr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if(pHba->FwDebugBuffer_P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) iounmap(pHba->FwDebugBuffer_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if(pHba->hrt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dma_free_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) pHba->hrt->num_entries * pHba->hrt->entry_len << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pHba->hrt, pHba->hrt_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if(pHba->lct) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dma_free_coherent(&pHba->pDev->dev, pHba->lct_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pHba->lct, pHba->lct_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if(pHba->status_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dma_free_coherent(&pHba->pDev->dev, sizeof(i2o_status_block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pHba->status_block, pHba->status_block_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if(pHba->reply_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dma_free_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pHba->reply_pool, pHba->reply_pool_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) for(d = pHba->devices; d ; d = next){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) next = d->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) for(i = 0 ; i < pHba->top_scsi_channel ; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) for(j = 0; j < MAX_ID; j++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if(pHba->channel[i].device[j] != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for(pDev = pHba->channel[i].device[j]; pDev; pDev = pNext){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pNext = pDev->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) kfree(pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pci_dev_put(pHba->pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (adpt_sysfs_class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) device_destroy(adpt_sysfs_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) MKDEV(DPTI_I2O_MAJOR, pHba->unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) kfree(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if(hba_count <= 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) unregister_chrdev(DPTI_I2O_MAJOR, DPT_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (adpt_sysfs_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) class_destroy(adpt_sysfs_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) adpt_sysfs_class = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static struct adpt_device* adpt_find_device(adpt_hba* pHba, u32 chan, u32 id, u64 lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct adpt_device* d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (chan >= MAX_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) d = pHba->channel[chan].device[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if(!d || d->tid == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* If it is the only lun at that address then this should match*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if(d->scsi_lun == lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* else we need to look through all the luns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) for(d=d->next_lun ; d ; d = d->next_lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if(d->scsi_lun == lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int adpt_i2o_post_wait(adpt_hba* pHba, u32* msg, int len, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) // I used my own version of the WAIT_QUEUE_HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) // to handle some version differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) // When embedded in the kernel this could go back to the vanilla one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ADPT_DECLARE_WAIT_QUEUE_HEAD(adpt_wq_i2o_post);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct adpt_i2o_post_wait_data *p1, *p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct adpt_i2o_post_wait_data *wait_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) kmalloc(sizeof(struct adpt_i2o_post_wait_data), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!wait_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * The spin locking is needed to keep anyone from playing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * with the queue pointers and id while we do the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) spin_lock_irqsave(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) // TODO we need a MORE unique way of getting ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) // to support async LCT get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) wait_data->next = adpt_post_wait_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) adpt_post_wait_queue = wait_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) adpt_post_wait_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) adpt_post_wait_id &= 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) wait_data->id = adpt_post_wait_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) wait_data->wq = &adpt_wq_i2o_post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) wait_data->status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) add_wait_queue(&adpt_wq_i2o_post, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) msg[2] |= 0x80000000 | ((u32)wait_data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) timeout *= HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if((status = adpt_i2o_post_this(pHba, msg, len)) == 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spin_unlock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) timeout = schedule_timeout(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) // I/O issued, but cannot get result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) // specified time. Freeing resorces is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) // dangerous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) status = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) spin_lock_irq(pHba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) remove_wait_queue(&adpt_wq_i2o_post, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if(status == -ETIMEDOUT){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) printk(KERN_INFO"dpti%d: POST WAIT TIMEOUT\n",pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) // We will have to free the wait_data memory during shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Remove the entry from the queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) p2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) spin_lock_irqsave(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) for(p1 = adpt_post_wait_queue; p1; p2 = p1, p1 = p1->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if(p1 == wait_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if(p1->status == I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) status = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if(p2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) p2->next = p1->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) adpt_post_wait_queue = p1->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) kfree(wait_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static s32 adpt_i2o_post_this(adpt_hba* pHba, u32* data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u32 m = EMPTY_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 __iomem *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ulong timeout = jiffies + 30*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (m != EMPTY_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) printk(KERN_WARNING"dpti%d: Timeout waiting for message frame!\n", pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) } while(m == EMPTY_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) msg = pHba->msg_addr_virt + m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) memcpy_toio(msg, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) //post message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) writel(m, pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void adpt_i2o_post_wait_complete(u32 context, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct adpt_i2o_post_wait_data *p1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * We need to search through the adpt_post_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * queue to see if the given message is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * outstanding. If not, it means that the IOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * took longer to respond to the message than we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * had allowed and timer has already expired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * Not much we can do about that except log
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * it for debug purposes, increase timeout, and recompile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * Lock needed to keep anyone from moving queue pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * around while we're looking through them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) context &= 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) spin_lock(&adpt_post_wait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for(p1 = adpt_post_wait_queue; p1; p1 = p1->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if(p1->id == context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) p1->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) spin_unlock(&adpt_post_wait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) wake_up_interruptible(p1->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) spin_unlock(&adpt_post_wait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) // If this happens we lose commands that probably really completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) printk(KERN_DEBUG"dpti: Could Not find task %d in wait queue\n",context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) printk(KERN_DEBUG" Tasks in wait queue:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for(p1 = adpt_post_wait_queue; p1; p1 = p1->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) printk(KERN_DEBUG" %d\n",p1->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static s32 adpt_i2o_reset_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) u32 msg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) u8* status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) u32 m = EMPTY_QUEUE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ulong timeout = jiffies + (TMOUT_IOPRESET*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if(pHba->initialized == FALSE) { // First time reset should be quick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) timeout = jiffies + (25*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) adpt_i2o_quiesce_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (m != EMPTY_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) printk(KERN_WARNING"Timeout waiting for message!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) } while (m == EMPTY_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) status = dma_alloc_coherent(&pHba->pDev->dev, 4, &addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if(status == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) adpt_send_nop(pHba, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) printk(KERN_ERR"IOP reset failed - no free memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) msg[0]=EIGHT_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) msg[1]=I2O_CMD_ADAPTER_RESET<<24|HOST_TID<<12|ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) msg[2]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) msg[3]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) msg[4]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) msg[5]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) msg[6]=dma_low(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) msg[7]=dma_high(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) memcpy_toio(pHba->msg_addr_virt+m, msg, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) writel(m, pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) while(*status == 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) printk(KERN_WARNING"%s: IOP Reset Timeout\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* We lose 4 bytes of "status" here, but we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) free these because controller may awake and corrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) those bytes at any time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* dma_free_coherent(&pHba->pDev->dev, 4, buf, addr); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if(*status == 0x01 /*I2O_EXEC_IOP_RESET_IN_PROGRESS*/) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PDEBUG("%s: Reset in progress...\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) // Here we wait for message frame to become available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) // indicated that reset has finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (m != EMPTY_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) printk(KERN_ERR "%s:Timeout waiting for IOP Reset.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* We lose 4 bytes of "status" here, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) cannot free these because controller may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) awake and corrupt those bytes at any time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* dma_free_coherent(&pHba->pDev->dev, 4, buf, addr); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) } while (m == EMPTY_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) // Flush the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) adpt_send_nop(pHba, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if(*status == 0x02 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pHba->status_block->iop_state != ADAPTER_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) printk(KERN_WARNING"%s: Reset reject, trying to clear\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PDEBUG("%s: Reset completed.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #ifdef UARTDELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) // This delay is to allow someone attached to the card through the debug UART to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) // set up the dump levels that they want before the rest of the initialization sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) adpt_delay(20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static int adpt_i2o_parse_lct(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct i2o_device *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) i2o_lct *lct = pHba->lct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u8 bus_no = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) s16 scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u64 scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 buf[10]; // larger than 7, or 8 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct adpt_device* pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (lct == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) printk(KERN_ERR "%s: LCT is empty???\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) max = lct->table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) max -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) max /= 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) for(i=0;i<max;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if( lct->lct_entry[i].user_tid != 0xfff){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * If we have hidden devices, we need to inform the upper layers about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * the possible maximum id reference to handle device access when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * an array is disassembled. This code has no other purpose but to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * allow us future access to devices that are currently hidden
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * behind arrays, hotspares or have not been configured (JBOD mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if( lct->lct_entry[i].class_id != I2O_CLASS_RANDOM_BLOCK_STORAGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) lct->lct_entry[i].class_id != I2O_CLASS_SCSI_PERIPHERAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) lct->lct_entry[i].class_id != I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) tid = lct->lct_entry[i].tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) // I2O_DPT_DEVICE_INFO_GROUP_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)<0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) bus_no = buf[0]>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) scsi_id = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) scsi_lun = scsilun_to_int((struct scsi_lun *)&buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) printk(KERN_WARNING"%s: Channel number %d out of range \n", pHba->name, bus_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (scsi_id >= MAX_ID){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) printk(KERN_WARNING"%s: SCSI ID %d out of range \n", pHba->name, bus_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if(bus_no > pHba->top_scsi_channel){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) pHba->top_scsi_channel = bus_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if(scsi_id > pHba->top_scsi_id){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pHba->top_scsi_id = scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if(scsi_lun > pHba->top_scsi_lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pHba->top_scsi_lun = scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) d = kmalloc(sizeof(struct i2o_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if(d==NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) printk(KERN_CRIT"%s: Out of memory for I2O device data.\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) d->controller = pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) d->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) d->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) tid = d->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) adpt_i2o_report_hba_unit(pHba, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) adpt_i2o_install_device(pHba, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) bus_no = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) for(d = pHba->devices; d ; d = d->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if(d->lct_data.class_id == I2O_CLASS_BUS_ADAPTER_PORT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) d->lct_data.class_id == I2O_CLASS_FIBRE_CHANNEL_PORT){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) tid = d->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) // TODO get the bus_no from hrt-but for now they are in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) //bus_no =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if(bus_no > pHba->top_scsi_channel){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) pHba->top_scsi_channel = bus_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pHba->channel[bus_no].type = d->lct_data.class_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) pHba->channel[bus_no].tid = tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if(adpt_i2o_query_scalar(pHba, tid, 0x0200, -1, buf, 28)>=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) pHba->channel[bus_no].scsi_id = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PDEBUG("Bus %d - SCSI ID %d.\n", bus_no, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) // TODO remove - this is just until we get from hrt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) bus_no++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) printk(KERN_WARNING"%s: Channel number %d out of range - LCT\n", pHba->name, bus_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) // Setup adpt_device table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) for(d = pHba->devices; d ; d = d->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if(d->lct_data.class_id == I2O_CLASS_RANDOM_BLOCK_STORAGE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) d->lct_data.class_id == I2O_CLASS_SCSI_PERIPHERAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) d->lct_data.class_id == I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) tid = d->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) scsi_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) // I2O_DPT_DEVICE_INFO_GROUP_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)>=0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) bus_no = buf[0]>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) scsi_id = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) scsi_lun = scsilun_to_int((struct scsi_lun *)&buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (scsi_id >= MAX_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if( pHba->channel[bus_no].device[scsi_id] == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) pDev = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if(pDev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pHba->channel[bus_no].device[scsi_id] = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) for( pDev = pHba->channel[bus_no].device[scsi_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pDev->next_lun; pDev = pDev->next_lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pDev->next_lun = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if(pDev->next_lun == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pDev = pDev->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pDev->tid = tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pDev->scsi_channel = bus_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pDev->scsi_id = scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) pDev->scsi_lun = scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) pDev->pI2o_dev = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) d->owner = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pDev->type = (buf[0])&0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) pDev->flags = (buf[0]>>8)&0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if(scsi_id > pHba->top_scsi_id){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) pHba->top_scsi_id = scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if(scsi_lun > pHba->top_scsi_lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) pHba->top_scsi_lun = scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if(scsi_id == -1){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) printk(KERN_WARNING"Could not find SCSI ID for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) d->lct_data.identity_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * Each I2O controller has a chain of devices on it - these match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * the useful parts of the LCT of the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static int adpt_i2o_install_device(adpt_hba* pHba, struct i2o_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) d->controller=pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) d->owner=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) d->next=pHba->devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) d->prev=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (pHba->devices != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) pHba->devices->prev=d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) pHba->devices=d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) *d->dev_name = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static int adpt_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) int minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mutex_lock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) //TODO check for root access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) minor = iminor(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (minor >= hba_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) mutex_unlock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (pHba->unit == minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) break; /* found adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (pHba == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) mutex_unlock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) // if(pHba->in_use){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) // mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) // return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pHba->in_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) mutex_unlock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static int adpt_close(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) minor = iminor(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (minor >= hba_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (pHba->unit == minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break; /* found adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (pHba == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) pHba->in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int adpt_i2o_passthru(adpt_hba* pHba, u32 __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 msg[MAX_MESSAGE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u32* reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u32 reply_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 __user *user_msg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u32 __user * user_reply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) void **sg_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) u32 sg_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) u32 sg_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int sg_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u32 rcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) void *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) memset(&msg, 0, MAX_MESSAGE_SIZE*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) // get user msg size in u32s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if(get_user(size, &user_msg[0])){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) size = size>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) user_reply = &user_msg[size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if(size > MAX_MESSAGE_SIZE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) size *= 4; // Convert to bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* Copy in the user's I2O command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if(copy_from_user(msg, user_msg, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) get_user(reply_size, &user_reply[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) reply_size = reply_size>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if(reply_size > REPLY_FRAME_SIZE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) reply_size = REPLY_FRAME_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) reply_size *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) reply = kzalloc(REPLY_FRAME_SIZE*4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if(reply == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) printk(KERN_WARNING"%s: Could not allocate reply buffer\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) sg_offset = (msg[0]>>4)&0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) msg[2] = 0x40000000; // IOCTL context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) msg[3] = adpt_ioctl_to_context(pHba, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (msg[3] == (u32)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) rcode = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) sg_list = kcalloc(pHba->sg_tablesize, sizeof(*sg_list), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (!sg_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) rcode = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if(sg_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) // TODO add 64 bit API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct sg_simple_element *sg = (struct sg_simple_element*) (msg+sg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (sg_count > pHba->sg_tablesize){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) printk(KERN_DEBUG"%s:IOCTL SG List too large (%u)\n", pHba->name,sg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) rcode = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) for(i = 0; i < sg_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) int sg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (!(sg[i].flag_count & 0x10000000 /*I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT*/)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) printk(KERN_DEBUG"%s:Bad SG element %d - not simple (%x)\n",pHba->name,i, sg[i].flag_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) rcode = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) sg_size = sg[i].flag_count & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* Allocate memory for the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) p = dma_alloc_coherent(&pHba->pDev->dev, sg_size, &addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if(!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) printk(KERN_DEBUG"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) pHba->name,sg_size,i,sg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) rcode = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) sg_list[sg_index++] = p; // sglist indexed with input frame, not our internal frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* Copy in the user's SG buffer if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if(sg[i].flag_count & 0x04000000 /*I2O_SGL_FLAGS_DIR*/) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) // sg_simple_element API is 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (copy_from_user(p,(void __user *)(ulong)sg[i].addr_bus, sg_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) printk(KERN_DEBUG"%s: Could not copy SG buf %d FROM user\n",pHba->name,i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /* sg_simple_element API is 32 bit, but addr < 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) sg[i].addr_bus = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * Stop any new commands from enterring the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * controller while processing the ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (pHba->host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) scsi_block_requests(pHba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) spin_lock_irqsave(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) rcode = adpt_i2o_post_wait(pHba, msg, size, FOREVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (rcode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) printk("adpt_i2o_passthru: post wait failed %d %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) rcode, reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (pHba->host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) spin_unlock_irqrestore(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) scsi_unblock_requests(pHba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) } while (rcode == -ETIMEDOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if(rcode){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if(sg_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* Copy back the Scatter Gather buffers back to user space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u32 j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) // TODO add 64 bit API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct sg_simple_element* sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) int sg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) // re-acquire the original message to handle correctly the sg copy operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) memset(&msg, 0, MAX_MESSAGE_SIZE*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) // get user msg size in u32s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if(get_user(size, &user_msg[0])){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) size = size>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) size *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (size > MAX_MESSAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) rcode = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Copy in the user's I2O command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (copy_from_user (msg, user_msg, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) // TODO add 64 bit API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) sg = (struct sg_simple_element*)(msg + sg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) for (j = 0; j < sg_count; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* Copy out the SG list to user's buffer if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if(! (sg[j].flag_count & 0x4000000 /*I2O_SGL_FLAGS_DIR*/)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) sg_size = sg[j].flag_count & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) // sg_simple_element API is 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (copy_to_user((void __user *)(ulong)sg[j].addr_bus,sg_list[j], sg_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) printk(KERN_WARNING"%s: Could not copy %p TO user %x\n",pHba->name, sg_list[j], sg[j].addr_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* Copy back the reply to user space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (reply_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) // we wrote our own values for context - now restore the user supplied ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if(copy_from_user(reply+2, user_msg+2, sizeof(u32)*2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) printk(KERN_WARNING"%s: Could not copy message context FROM user\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if(copy_to_user(user_reply, reply, reply_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) printk(KERN_WARNING"%s: Could not copy reply TO user\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) rcode = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (rcode != -ETIME && rcode != -EINTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct sg_simple_element *sg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) (struct sg_simple_element*) (msg +sg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) while(sg_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if(sg_list[--sg_index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) dma_free_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) sg[sg_index].flag_count & 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) sg_list[sg_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) sg[sg_index].addr_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) kfree(sg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) kfree(reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #if defined __ia64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static void adpt_ia64_info(sysInfo_S* si)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) // This is all the info we need for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) // We will add more info as our new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) // managmenent utility requires it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) si->processorType = PROC_IA64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #if defined __sparc__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static void adpt_sparc_info(sysInfo_S* si)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) // This is all the info we need for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) // We will add more info as our new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) // managmenent utility requires it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) si->processorType = PROC_ULTRASPARC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #if defined __alpha__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static void adpt_alpha_info(sysInfo_S* si)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) // This is all the info we need for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) // We will add more info as our new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) // managmenent utility requires it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) si->processorType = PROC_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #if defined __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #include <uapi/asm/vm86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static void adpt_i386_info(sysInfo_S* si)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) // This is all the info we need for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) // We will add more info as our new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) // managmenent utility requires it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) switch (boot_cpu_data.x86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) case CPU_386:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) si->processorType = PROC_386;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) case CPU_486:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) si->processorType = PROC_486;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) case CPU_586:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) si->processorType = PROC_PENTIUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) default: // Just in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) si->processorType = PROC_PENTIUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * This routine returns information about the system. This does not effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * any logic and if the info is wrong - it doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* Get all the info we can not get from kernel services */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static int adpt_system_info(void __user *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) sysInfo_S si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) memset(&si, 0, sizeof(si));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) si.osType = OS_LINUX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) si.osMajorVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) si.osMinorVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) si.osRevision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) si.busType = SI_PCI_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) si.processorFamily = DPTI_sig.dsProcessorFamily;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #if defined __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) adpt_i386_info(&si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #elif defined (__ia64__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) adpt_ia64_info(&si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #elif defined(__sparc__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) adpt_sparc_info(&si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #elif defined (__alpha__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) adpt_alpha_info(&si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) si.processorType = 0xff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (copy_to_user(buffer, &si, sizeof(si))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) printk(KERN_WARNING"dpti: Could not copy buffer TO user\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static int adpt_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) int minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) minor = iminor(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (minor >= DPTI_MAX_HBA){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) mutex_lock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (pHba->unit == minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) break; /* found adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) mutex_unlock(&adpt_configuration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if(pHba == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) while((volatile u32) pHba->state & DPTI_STATE_RESET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) schedule_timeout_uninterruptible(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) // TODO: handle 3 cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case DPT_SIGNATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (copy_to_user(argp, &DPTI_sig, sizeof(DPTI_sig))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) case I2OUSRCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return adpt_i2o_passthru(pHba, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) case DPT_CTRLINFO:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) drvrHBAinfo_S HbaInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define FLG_OSD_PCI_VALID 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define FLG_OSD_DMA 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define FLG_OSD_I2O 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) memset(&HbaInfo, 0, sizeof(HbaInfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) HbaInfo.drvrHBAnum = pHba->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) HbaInfo.baseAddr = (ulong) pHba->base_addr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) HbaInfo.blinkState = adpt_read_blink_led(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) HbaInfo.pciBusNum = pHba->pDev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) HbaInfo.pciDeviceNum=PCI_SLOT(pHba->pDev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) HbaInfo.Interrupt = pHba->pDev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) HbaInfo.hbaFlags = FLG_OSD_PCI_VALID | FLG_OSD_DMA | FLG_OSD_I2O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if(copy_to_user(argp, &HbaInfo, sizeof(HbaInfo))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) printk(KERN_WARNING"%s: Could not copy HbaInfo TO user\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case DPT_SYSINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return adpt_system_info(argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) case DPT_BLINKLED:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) value = (u32)adpt_read_blink_led(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (copy_to_user(argp, &value, sizeof(value))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) case I2ORESETCMD: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct Scsi_Host *shost = pHba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) spin_lock_irqsave(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) adpt_hba_reset(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) spin_unlock_irqrestore(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) case I2ORESCANCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) adpt_rescan(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static long adpt_unlocked_ioctl(struct file *file, uint cmd, ulong arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct inode *inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) inode = file_inode(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) mutex_lock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ret = adpt_ioctl(inode, file, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) mutex_unlock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static long compat_adpt_ioctl(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct inode *inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) inode = file_inode(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) mutex_lock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) switch(cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case DPT_SIGNATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) case I2OUSRCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) case DPT_CTRLINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) case DPT_SYSINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) case DPT_BLINKLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) case I2ORESETCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) case I2ORESCANCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) case (DPT_TARGET_BUSY & 0xFFFF):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) case DPT_TARGET_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ret = adpt_ioctl(inode, file, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) mutex_unlock(&adpt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static irqreturn_t adpt_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct scsi_cmnd* cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) adpt_hba* pHba = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) void __iomem *reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) u32 status=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) u32 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (pHba == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) printk(KERN_WARNING"adpt_isr: NULL dev_id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) spin_lock_irqsave(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) while( readl(pHba->irq_mask) & I2O_INTERRUPT_PENDING_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) m = readl(pHba->reply_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if(m == EMPTY_QUEUE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) // Try twice then give up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) m = readl(pHba->reply_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if(m == EMPTY_QUEUE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) // This really should not happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) printk(KERN_ERR"dpti: Could not get reply frame\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (pHba->reply_pool_pa <= m &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) m < pHba->reply_pool_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) (pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) reply = (u8 *)pHba->reply_pool +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) (m - pHba->reply_pool_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /* Ick, we should *never* be here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) printk(KERN_ERR "dpti: reply frame not from pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) reply = (u8 *)bus_to_virt(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (readl(reply) & MSG_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) u32 old_m = readl(reply+28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) void __iomem *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) u32 old_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) PDEBUG("%s: Failed message\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if(old_m >= 0x100000){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) printk(KERN_ERR"%s: Bad preserved MFA (%x)- dropping frame\n",pHba->name,old_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) writel(m,pHba->reply_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) // Transaction context is 0 in failed reply frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) msg = pHba->msg_addr_virt + old_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) old_context = readl(msg+12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) writel(old_context, reply+12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) adpt_send_nop(pHba, old_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) context = readl(reply+8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if(context & 0x40000000){ // IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) void *p = adpt_ioctl_from_context(pHba, readl(reply+12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if( p != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) memcpy_fromio(p, reply, REPLY_FRAME_SIZE * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) // All IOCTLs will also be post wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if(context & 0x80000000){ // Post wait message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) status = readl(reply+16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if(status >> 24){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) status &= 0xffff; /* Get detail status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) status = I2O_POST_WAIT_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if(!(context & 0x40000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * The request tag is one less than the command tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) * as the firmware might treat a 0 tag as invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) cmd = scsi_host_find_tag(pHba->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) readl(reply + 12) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if(cmd != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) adpt_i2o_post_wait_complete(context, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) } else { // SCSI message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * The request tag is one less than the command tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * as the firmware might treat a 0 tag as invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) cmd = scsi_host_find_tag(pHba->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) readl(reply + 12) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if(cmd != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) adpt_i2o_scsi_complete(reply, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) writel(m, pHba->reply_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) out: if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) spin_unlock_irqrestore(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static s32 adpt_scsi_to_i2o(adpt_hba* pHba, struct scsi_cmnd* cmd, struct adpt_device* d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) u32 msg[MAX_MESSAGE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) u32* mptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) u32* lptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) u32 *lenptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) int scsidir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) int nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) u32 reqlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) s32 rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) memset(msg, 0 , sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) len = scsi_bufflen(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) direction = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) scsidir = 0x00000000; // DATA NO XFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if(len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) * Set SCBFlags to indicate if data is being transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) * in or out, or no data transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) * Note: Do not have to verify index is less than 0 since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * cmd->cmnd[0] is an unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) switch(cmd->sc_data_direction){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) case DMA_FROM_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) scsidir =0x40000000; // DATA IN (iop<--dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) case DMA_TO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) direction=0x04000000; // SGL OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) scsidir =0x80000000; // DATA OUT (iop-->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) case DMA_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) case DMA_BIDIRECTIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) scsidir =0x40000000; // DATA IN (iop<--dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) // Assume In - and continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) printk(KERN_WARNING"%s: scsi opcode 0x%x not supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) pHba->name, cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) cmd->result = (DID_OK <<16) | (INITIATOR_ERROR << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) // msg[0] is set later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) // I2O_CMD_SCSI_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) msg[1] = ((0xff<<24)|(HOST_TID<<12)|d->tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Add 1 to avoid firmware treating it as invalid command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) msg[3] = cmd->request->tag + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) // Our cards use the transaction context as the tag for queueing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) // Adaptec/DPT Private stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) msg[4] = I2O_CMD_SCSI_EXEC|(DPT_ORGANIZATION_ID<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) msg[5] = d->tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* Direction, disconnect ok | sense data | simple queue , CDBLen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) // I2O_SCB_FLAG_ENABLE_DISCONNECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) // I2O_SCB_FLAG_SIMPLE_QUEUE_TAG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) // I2O_SCB_FLAG_SENSE_DATA_IN_MESSAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) msg[6] = scsidir|0x20a00000|cmd->cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) mptr=msg+7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) // Write SCSI command into the message - always 16 byte block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) memset(mptr, 0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) memcpy(mptr, cmd->cmnd, cmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) mptr+=4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) lenptr=mptr++; /* Remember me - fill in when we know */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (dpt_dma64(pHba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) reqlen = 16; // SINGLE SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) *mptr++ = (0x7C<<24)+(2<<16)+0x02; /* Enable 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) *mptr++ = 1 << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) reqlen = 14; // SINGLE SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /* Now fill in the SGList and command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) nseg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) BUG_ON(nseg < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (nseg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) scsi_for_each_sg(cmd, sg, nseg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) lptr = mptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) *mptr++ = direction|0x10000000|sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) len+=sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) *mptr++ = dma_low(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (dpt_dma64(pHba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) *mptr++ = dma_high(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /* Make this an end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (i == nseg - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) *lptr = direction|0xD0000000|sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) reqlen = mptr - msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) *lenptr = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if(cmd->underflow && len != cmd->underflow){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) printk(KERN_WARNING"Cmd len %08X Cmd underflow %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) len, cmd->underflow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) *lenptr = len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) reqlen = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* Stick the headers on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) msg[0] = reqlen<<16 | ((reqlen > 12) ? SGL_OFFSET_12 : SGL_OFFSET_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) // Send it on it's way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) rcode = adpt_i2o_post_this(pHba, msg, reqlen<<2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (rcode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static s32 adpt_scsi_host_alloc(adpt_hba* pHba, struct scsi_host_template *sht)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) host = scsi_host_alloc(sht, sizeof(adpt_hba*));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) printk("%s: scsi_host_alloc returned NULL\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) host->hostdata[0] = (unsigned long)pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) pHba->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) host->irq = pHba->pDev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /* no IO ports, so don't have to set host->io_port and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) * host->n_io_port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) host->io_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) host->n_io_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /* see comments in scsi_host.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) host->max_id = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) host->max_lun = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) host->max_channel = pHba->top_scsi_channel + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) host->cmd_per_lun = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) host->unique_id = (u32)sys_tbl_pa + pHba->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) host->sg_tablesize = pHba->sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) host->can_queue = pHba->post_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) static void adpt_i2o_scsi_complete(void __iomem *reply, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) adpt_hba* pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) u32 hba_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) u32 dev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) u32 reply_flags = readl(reply) & 0xff00; // Leave it shifted up 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) // I know this would look cleaner if I just read bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) // but the model I have been using for all the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) // io is in 4 byte words - so I keep that model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) u16 detailed_status = readl(reply+16) &0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) dev_status = (detailed_status & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) hba_status = detailed_status >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) // calculate resid for sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) scsi_set_resid(cmd, scsi_bufflen(cmd) - readl(reply+20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) pHba = (adpt_hba*) cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) cmd->sense_buffer[0] = '\0'; // initialize sense valid flag to false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if(!(reply_flags & MSG_FAIL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) switch(detailed_status & I2O_SCSI_DSC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) case I2O_SCSI_DSC_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) cmd->result = (DID_OK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) // handle underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (readl(reply+20) < cmd->underflow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) cmd->result = (DID_ERROR <<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) printk(KERN_WARNING"%s: SCSI CMD underflow\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) case I2O_SCSI_DSC_REQUEST_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) cmd->result = (DID_ABORT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) case I2O_SCSI_DSC_PATH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) case I2O_SCSI_DSC_DEVICE_NOT_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) case I2O_SCSI_DSC_SELECTION_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) case I2O_SCSI_DSC_COMMAND_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) case I2O_SCSI_DSC_NO_ADAPTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) case I2O_SCSI_DSC_RESOURCE_UNAVAILABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) printk(KERN_WARNING"%s: SCSI Timeout-Device (%d,%d,%llu) hba status=0x%x, dev status=0x%x, cmd=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, cmd->device->lun, hba_status, dev_status, cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) cmd->result = (DID_TIME_OUT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) case I2O_SCSI_DSC_ADAPTER_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) case I2O_SCSI_DSC_BUS_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) cmd->result = (DID_BUS_BUSY << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) case I2O_SCSI_DSC_SCSI_BUS_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case I2O_SCSI_DSC_BDR_MESSAGE_SENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) cmd->result = (DID_RESET << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) case I2O_SCSI_DSC_PARITY_ERROR_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) printk(KERN_WARNING"%s: SCSI CMD parity error\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) cmd->result = (DID_PARITY << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) case I2O_SCSI_DSC_UNABLE_TO_ABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) case I2O_SCSI_DSC_COMPLETE_WITH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) case I2O_SCSI_DSC_UNABLE_TO_TERMINATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) case I2O_SCSI_DSC_MR_MESSAGE_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) case I2O_SCSI_DSC_AUTOSENSE_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case I2O_SCSI_DSC_DATA_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) case I2O_SCSI_DSC_UNEXPECTED_BUS_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) case I2O_SCSI_DSC_SEQUENCE_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) case I2O_SCSI_DSC_REQUEST_LENGTH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) case I2O_SCSI_DSC_PROVIDE_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) case I2O_SCSI_DSC_REQUEST_TERMINATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) case I2O_SCSI_DSC_IDE_MESSAGE_SENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) case I2O_SCSI_DSC_UNACKNOWLEDGED_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) case I2O_SCSI_DSC_MESSAGE_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) case I2O_SCSI_DSC_INVALID_CDB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) case I2O_SCSI_DSC_LUN_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) case I2O_SCSI_DSC_SCSI_TID_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) case I2O_SCSI_DSC_FUNCTION_UNAVAILABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) case I2O_SCSI_DSC_NO_NEXUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) case I2O_SCSI_DSC_CDB_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) case I2O_SCSI_DSC_LUN_ALREADY_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) case I2O_SCSI_DSC_QUEUE_FROZEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) case I2O_SCSI_DSC_REQUEST_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) printk(KERN_WARNING"%s: SCSI error %0x-Device(%d,%d,%llu) hba_status=0x%x, dev_status=0x%x, cmd=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) pHba->name, detailed_status & I2O_SCSI_DSC_MASK, (u32)cmd->device->channel, (u32)cmd->device->id, cmd->device->lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) hba_status, dev_status, cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) cmd->result = (DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) // copy over the request sense data if it was a check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) // condition status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (dev_status == SAM_STAT_CHECK_CONDITION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) u32 len = min(SCSI_SENSE_BUFFERSIZE, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) // Copy over the sense data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) memcpy_fromio(cmd->sense_buffer, (reply+28) , len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) if(cmd->sense_buffer[0] == 0x70 /* class 7 */ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) cmd->sense_buffer[2] == DATA_PROTECT ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /* This is to handle an array failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) cmd->result = (DID_TIME_OUT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) printk(KERN_WARNING"%s: SCSI Data Protect-Device (%d,%d,%llu) hba_status=0x%x, dev_status=0x%x, cmd=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, cmd->device->lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) hba_status, dev_status, cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) /* In this condtion we could not talk to the tid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * the card rejected it. We should signal a retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * for a limitted number of retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) cmd->result = (DID_TIME_OUT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) printk(KERN_WARNING"%s: I2O MSG_FAIL - Device (%d,%d,%llu) tid=%d, cmd=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, cmd->device->lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ((struct adpt_device*)(cmd->device->hostdata))->tid, cmd->cmnd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) cmd->result |= (dev_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if(cmd->scsi_done != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) static s32 adpt_rescan(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) s32 rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ulong flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) spin_lock_irqsave(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if ((rcode=adpt_i2o_lct_get(pHba)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if ((rcode=adpt_i2o_reparse_lct(pHba)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) rcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) out: if(pHba->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) spin_unlock_irqrestore(pHba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static s32 adpt_i2o_reparse_lct(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) int tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) struct i2o_device *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) i2o_lct *lct = pHba->lct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) u8 bus_no = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) s16 scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) u64 scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) u32 buf[10]; // at least 8 u32's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) struct adpt_device* pDev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) struct i2o_device* pI2o_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (lct == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) printk(KERN_ERR "%s: LCT is empty???\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) max = lct->table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) max -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) max /= 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) // Mark each drive as unscanned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) for (d = pHba->devices; d; d = d->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) pDev =(struct adpt_device*) d->owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if(!pDev){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) pDev->state |= DPTI_DEV_UNSCANNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) printk(KERN_INFO "%s: LCT has %d entries.\n", pHba->name,max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) for(i=0;i<max;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if( lct->lct_entry[i].user_tid != 0xfff){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if( lct->lct_entry[i].class_id == I2O_CLASS_RANDOM_BLOCK_STORAGE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) lct->lct_entry[i].class_id == I2O_CLASS_SCSI_PERIPHERAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) lct->lct_entry[i].class_id == I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) tid = lct->lct_entry[i].tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)<0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) printk(KERN_ERR"%s: Could not query device\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) bus_no = buf[0]>>16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (bus_no >= MAX_CHANNEL) { /* Something wrong skip it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) "%s: Channel number %d out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pHba->name, bus_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) scsi_id = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) scsi_lun = scsilun_to_int((struct scsi_lun *)&buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) pDev = pHba->channel[bus_no].device[scsi_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* da lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) while(pDev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if(pDev->scsi_lun == scsi_lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) pDev = pDev->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if(!pDev ) { // Something new add it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) d = kmalloc(sizeof(struct i2o_device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if(d==NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) printk(KERN_CRIT "Out of memory for I2O device data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) d->controller = pHba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) d->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) d->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) adpt_i2o_report_hba_unit(pHba, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) adpt_i2o_install_device(pHba, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) pDev = pHba->channel[bus_no].device[scsi_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if( pDev == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) pDev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) kzalloc(sizeof(struct adpt_device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if(pDev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) pHba->channel[bus_no].device[scsi_id] = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) while (pDev->next_lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) pDev = pDev->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) pDev = pDev->next_lun =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) kzalloc(sizeof(struct adpt_device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if(pDev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) pDev->tid = d->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) pDev->scsi_channel = bus_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) pDev->scsi_id = scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) pDev->scsi_lun = scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) pDev->pI2o_dev = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) d->owner = pDev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) pDev->type = (buf[0])&0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) pDev->flags = (buf[0]>>8)&0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) // Too late, SCSI system has made up it's mind, but what the hey ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if(scsi_id > pHba->top_scsi_id){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) pHba->top_scsi_id = scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if(scsi_lun > pHba->top_scsi_lun){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) pHba->top_scsi_lun = scsi_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) } // end of new i2o device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) // We found an old device - check it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) while(pDev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if(pDev->scsi_lun == scsi_lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if(!scsi_device_online(pDev->pScsi_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) printk(KERN_WARNING"%s: Setting device (%d,%d,%llu) back online\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) pHba->name,bus_no,scsi_id,scsi_lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) if (pDev->pScsi_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) scsi_device_set_state(pDev->pScsi_dev, SDEV_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) d = pDev->pI2o_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if(d->lct_data.tid != tid) { // something changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) pDev->tid = tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (pDev->pScsi_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) pDev->pScsi_dev->changed = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) pDev->pScsi_dev->removable = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) // Found it - mark it scanned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) pDev->state = DPTI_DEV_ONLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pDev = pDev->next_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) for (pI2o_dev = pHba->devices; pI2o_dev; pI2o_dev = pI2o_dev->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) pDev =(struct adpt_device*) pI2o_dev->owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if(!pDev){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) // Drive offline drives that previously existed but could not be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) // in the LCT table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (pDev->state & DPTI_DEV_UNSCANNED){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) pDev->state = DPTI_DEV_OFFLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) printk(KERN_WARNING"%s: Device (%d,%d,%llu) offline\n",pHba->name,pDev->scsi_channel,pDev->scsi_id,pDev->scsi_lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) if (pDev->pScsi_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) scsi_device_set_state(pDev->pScsi_dev, SDEV_OFFLINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * Routines from i2o subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * Bring an I2O controller into HOLD state. See the spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static int adpt_i2o_activate_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) int rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if(pHba->initialized ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (adpt_i2o_status_get(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if((rcode = adpt_i2o_reset_hba(pHba)) != 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) printk(KERN_WARNING"%s: Could NOT reset.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (adpt_i2o_status_get(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) printk(KERN_INFO "HBA not responding.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if(pHba->status_block->iop_state == ADAPTER_STATE_FAULTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) printk(KERN_CRIT "%s: hardware fault\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (pHba->status_block->iop_state == ADAPTER_STATE_READY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) pHba->status_block->iop_state == ADAPTER_STATE_OPERATIONAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) pHba->status_block->iop_state == ADAPTER_STATE_HOLD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) pHba->status_block->iop_state == ADAPTER_STATE_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) adpt_i2o_reset_hba(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (adpt_i2o_status_get(pHba) < 0 || pHba->status_block->iop_state != ADAPTER_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) printk(KERN_ERR "%s: Failed to initialize.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if((rcode = adpt_i2o_reset_hba(pHba)) != 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) printk(KERN_WARNING"%s: Could NOT reset.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return rcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (adpt_i2o_init_outbound_q(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* In HOLD state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (adpt_i2o_hrt_get(pHba) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * Bring a controller online into OPERATIONAL state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static int adpt_i2o_online_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (adpt_i2o_systab_send(pHba) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) /* In READY state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (adpt_i2o_enable_hba(pHba) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) /* In OPERATIONAL state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static s32 adpt_send_nop(adpt_hba*pHba,u32 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) u32 __iomem *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ulong timeout = jiffies + 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) while(m == EMPTY_QUEUE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if(m != EMPTY_QUEUE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) printk(KERN_ERR "%s: Timeout waiting for message frame!\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) msg = (u32 __iomem *)(pHba->msg_addr_virt + m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) writel( THREE_WORD_MSG_SIZE | SGL_OFFSET_0,&msg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) writel( I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | 0,&msg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) writel( 0,&msg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) writel(m, pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static s32 adpt_i2o_init_outbound_q(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) u8 *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) u32 __iomem *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ulong timeout = jiffies + TMOUT_INITOUTBOUND*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (m != EMPTY_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) printk(KERN_WARNING"%s: Timeout waiting for message frame\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) } while(m == EMPTY_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) msg=(u32 __iomem *)(pHba->msg_addr_virt+m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) status = dma_alloc_coherent(&pHba->pDev->dev, 4, &addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) adpt_send_nop(pHba, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) printk(KERN_WARNING"%s: IOP reset failed - no free memory.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) writel(EIGHT_WORD_MSG_SIZE| SGL_OFFSET_6, &msg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) writel(I2O_CMD_OUTBOUND_INIT<<24 | HOST_TID<<12 | ADAPTER_TID, &msg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) writel(0, &msg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) writel(0x0106, &msg[3]); /* Transaction context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) writel(4096, &msg[4]); /* Host page frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) writel((REPLY_FRAME_SIZE)<<16|0x80, &msg[5]); /* Outbound msg frame size and Initcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) writel(0xD0000004, &msg[6]); /* Simple SG LE, EOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) writel((u32)addr, &msg[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) writel(m, pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) // Wait for the reply status to come back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (*status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) if (*status != 0x01 /*I2O_EXEC_OUTBOUND_INIT_IN_PROGRESS*/) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) printk(KERN_WARNING"%s: Timeout Initializing\n",pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /* We lose 4 bytes of "status" here, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) cannot free these because controller may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) awake and corrupt those bytes at any time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /* dma_free_coherent(&pHba->pDev->dev, 4, status, addr); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) // If the command was successful, fill the fifo with our reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) // message packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) if(*status != 0x04 /*I2O_EXEC_OUTBOUND_INIT_COMPLETE*/) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) if(pHba->reply_pool != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) dma_free_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) pHba->reply_pool, pHba->reply_pool_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) pHba->reply_pool = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) &pHba->reply_pool_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) if (!pHba->reply_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) printk(KERN_ERR "%s: Could not allocate reply pool\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) for(i = 0; i < pHba->reply_fifo_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) writel(pHba->reply_pool_pa + (i * REPLY_FRAME_SIZE * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) pHba->reply_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) * I2O System Table. Contains information about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) * all the IOPs in the system. Used to inform IOPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) * about each other's existence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) * sys_tbl_ver is the CurrentChangeIndicator that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) * used by IOPs to track changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) static s32 adpt_i2o_status_get(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) ulong timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) u32 __iomem *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) u8 *status_block=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) if(pHba->status_block == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) pHba->status_block = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) sizeof(i2o_status_block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) &pHba->status_block_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) if(pHba->status_block == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) "dpti%d: Get Status Block failed; Out of memory. \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) memset(pHba->status_block, 0, sizeof(i2o_status_block));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) status_block = (u8*)(pHba->status_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) timeout = jiffies+TMOUT_GETSTATUS*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) m = readl(pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (m != EMPTY_QUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) printk(KERN_ERR "%s: Timeout waiting for message !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) } while(m==EMPTY_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) msg=(u32 __iomem *)(pHba->msg_addr_virt+m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) writel(NINE_WORD_MSG_SIZE|SGL_OFFSET_0, &msg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) writel(I2O_CMD_STATUS_GET<<24|HOST_TID<<12|ADAPTER_TID, &msg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) writel(1, &msg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) writel(0, &msg[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) writel(0, &msg[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) writel(0, &msg[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) writel( dma_low(pHba->status_block_pa), &msg[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) writel( dma_high(pHba->status_block_pa), &msg[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) writel(sizeof(i2o_status_block), &msg[8]); // 88 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) //post message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) writel(m, pHba->post_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) while(status_block[87]!=0xff){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if(time_after(jiffies,timeout)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) printk(KERN_ERR"dpti%d: Get status timeout.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) // Set up our number of outbound and inbound messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) pHba->post_fifo_size = pHba->status_block->max_inbound_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) if (pHba->post_fifo_size > MAX_TO_IOP_MESSAGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) pHba->post_fifo_size = MAX_TO_IOP_MESSAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) pHba->reply_fifo_size = pHba->status_block->max_outbound_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) if (pHba->reply_fifo_size > MAX_FROM_IOP_MESSAGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) pHba->reply_fifo_size = MAX_FROM_IOP_MESSAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) // Calculate the Scatter Gather list size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) if (dpt_dma64(pHba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) pHba->sg_tablesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) = ((pHba->status_block->inbound_frame_size * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) - 14 * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) / (sizeof(struct sg_simple_element) + sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) pHba->sg_tablesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) = ((pHba->status_block->inbound_frame_size * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) - 12 * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) / sizeof(struct sg_simple_element));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) if (pHba->sg_tablesize > SG_LIST_ELEMENTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) pHba->sg_tablesize = SG_LIST_ELEMENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) printk("dpti%d: State = ",pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) switch(pHba->status_block->iop_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) printk("INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) printk("RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) printk("HOLD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) case 0x05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) printk("READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) printk("OPERATIONAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) printk("FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) printk("FAULTED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) printk("%x (unknown!!)\n",pHba->status_block->iop_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) * Get the IOP's Logical Configuration Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static int adpt_i2o_lct_get(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) u32 msg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) u32 buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if ((pHba->lct_size == 0) || (pHba->lct == NULL)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) pHba->lct_size = pHba->status_block->expected_lct_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (pHba->lct == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) pHba->lct = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) pHba->lct_size, &pHba->lct_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) if(pHba->lct == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) printk(KERN_CRIT "%s: Lct Get failed. Out of memory.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) memset(pHba->lct, 0, pHba->lct_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) msg[0] = EIGHT_WORD_MSG_SIZE|SGL_OFFSET_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) msg[1] = I2O_CMD_LCT_NOTIFY<<24 | HOST_TID<<12 | ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) msg[4] = 0xFFFFFFFF; /* All devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) msg[5] = 0x00000000; /* Report now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) msg[6] = 0xD0000000|pHba->lct_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) msg[7] = (u32)pHba->lct_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) if ((ret=adpt_i2o_post_wait(pHba, msg, sizeof(msg), 360))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) printk(KERN_ERR "%s: LCT Get failed (status=%#10x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) pHba->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) printk(KERN_ERR"Adaptec: Error Reading Hardware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) if ((pHba->lct->table_size << 2) > pHba->lct_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) pHba->lct_size = pHba->lct->table_size << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) dma_free_coherent(&pHba->pDev->dev, pHba->lct_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) pHba->lct, pHba->lct_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) pHba->lct = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) } while (pHba->lct == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) PDEBUG("%s: Hardware resource table read.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) // I2O_DPT_EXEC_IOP_BUFFERS_GROUP_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) if(adpt_i2o_query_scalar(pHba, 0 , 0x8000, -1, buf, sizeof(buf))>=0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) pHba->FwDebugBufferSize = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) pHba->FwDebugBuffer_P = ioremap(pHba->base_addr_phys + buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) pHba->FwDebugBufferSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if (pHba->FwDebugBuffer_P) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) pHba->FwDebugFlags_P = pHba->FwDebugBuffer_P +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) FW_DEBUG_FLAGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) pHba->FwDebugBLEDvalue_P = pHba->FwDebugBuffer_P +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) FW_DEBUG_BLED_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) pHba->FwDebugBLEDflag_P = pHba->FwDebugBLEDvalue_P + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) pHba->FwDebugStrLength_P = pHba->FwDebugBuffer_P +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) FW_DEBUG_STR_LENGTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) pHba->FwDebugBuffer_P += buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) pHba->FwDebugFlags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) static int adpt_i2o_build_sys_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) adpt_hba* pHba = hba_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (sys_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) dma_free_coherent(&pHba->pDev->dev, sys_tbl_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) sys_tbl, sys_tbl_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) sys_tbl_len = sizeof(struct i2o_sys_tbl) + // Header + IOPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) (hba_count) * sizeof(struct i2o_sys_tbl_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) sys_tbl = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) sys_tbl_len, &sys_tbl_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) if (!sys_tbl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) printk(KERN_WARNING "SysTab Set failed. Out of memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) sys_tbl->num_entries = hba_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) sys_tbl->version = I2OVERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) sys_tbl->change_ind = sys_tbl_ind++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) for(pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) // Get updated Status Block so we have the latest information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (adpt_i2o_status_get(pHba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) sys_tbl->num_entries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) continue; // try next one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) sys_tbl->iops[count].org_id = pHba->status_block->org_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) sys_tbl->iops[count].iop_id = pHba->unit + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) sys_tbl->iops[count].seg_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) sys_tbl->iops[count].i2o_version = pHba->status_block->i2o_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) sys_tbl->iops[count].iop_state = pHba->status_block->iop_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) sys_tbl->iops[count].msg_type = pHba->status_block->msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) sys_tbl->iops[count].frame_size = pHba->status_block->inbound_frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) sys_tbl->iops[count].last_changed = sys_tbl_ind - 1; // ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) sys_tbl->iops[count].iop_capabilities = pHba->status_block->iop_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) addr = pHba->base_addr_phys + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) sys_tbl->iops[count].inbound_low = dma_low(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) sys_tbl->iops[count].inbound_high = dma_high(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) u32 *table = (u32*)sys_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) printk(KERN_DEBUG"sys_tbl_len=%d in 32bit words\n",(sys_tbl_len >>2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) for(count = 0; count < (sys_tbl_len >>2); count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) printk(KERN_INFO "sys_tbl[%d] = %0#10x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) count, table[count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) * Dump the information block associated with a given unit (TID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static void adpt_i2o_report_hba_unit(adpt_hba* pHba, struct i2o_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) char buf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) int unit = d->lct_data.tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) printk(KERN_INFO "TID %3.3d ", unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 3, buf, 16)>=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) buf[16]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) printk(" Vendor: %-12.12s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 4, buf, 16)>=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) buf[16]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) printk(" Device: %-12.12s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 6, buf, 8)>=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) buf[8]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) printk(" Rev: %-12.12s\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) printk(KERN_INFO "\tClass: %.21s\n", adpt_i2o_get_class_name(d->lct_data.class_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) printk(KERN_INFO "\tSubclass: 0x%04X\n", d->lct_data.sub_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) printk(KERN_INFO "\tFlags: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) if(d->lct_data.device_flags&(1<<0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) printk("C"); // ConfigDialog requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) if(d->lct_data.device_flags&(1<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) printk("U"); // Multi-user capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if(!(d->lct_data.device_flags&(1<<4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) printk("P"); // Peer service enabled!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) if(!(d->lct_data.device_flags&(1<<5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) printk("M"); // Mgmt service enabled!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) * Do i2o class name lookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) static const char *adpt_i2o_get_class_name(int class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) int idx = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) static char *i2o_class_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) "Executive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) "Device Driver Module",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) "Block Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) "Tape Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) "LAN Interface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) "WAN Interface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) "Fibre Channel Port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) "Fibre Channel Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) "SCSI Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) "ATE Port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) "ATE Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) "Floppy Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) "Floppy Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) "Secondary Bus Port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) "Peer Transport Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) "Peer Transport",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) "Unknown"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) switch(class&0xFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) case I2O_CLASS_EXECUTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) idx = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) case I2O_CLASS_DDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) idx = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) case I2O_CLASS_RANDOM_BLOCK_STORAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) idx = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) case I2O_CLASS_SEQUENTIAL_STORAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) idx = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) case I2O_CLASS_LAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) idx = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) case I2O_CLASS_WAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) idx = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) case I2O_CLASS_FIBRE_CHANNEL_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) idx = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) case I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) idx = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) case I2O_CLASS_SCSI_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) idx = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) case I2O_CLASS_ATE_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) idx = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) case I2O_CLASS_ATE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) idx = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) case I2O_CLASS_FLOPPY_CONTROLLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) idx = 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) case I2O_CLASS_FLOPPY_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) idx = 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) case I2O_CLASS_BUS_ADAPTER_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) idx = 13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) case I2O_CLASS_PEER_TRANSPORT_AGENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) idx = 14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) case I2O_CLASS_PEER_TRANSPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) idx = 15; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) return i2o_class_name[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) static s32 adpt_i2o_hrt_get(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) u32 msg[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) int ret, size = sizeof(i2o_hrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) if (pHba->hrt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) pHba->hrt = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) size, &pHba->hrt_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) if (pHba->hrt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) printk(KERN_CRIT "%s: Hrt Get failed; Out of memory.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) msg[0]= SIX_WORD_MSG_SIZE| SGL_OFFSET_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) msg[1]= I2O_CMD_HRT_GET<<24 | HOST_TID<<12 | ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) msg[2]= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) msg[3]= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) msg[4]= (0xD0000000 | size); /* Simple transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) msg[5]= (u32)pHba->hrt_pa; /* Dump it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if ((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg),20))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) printk(KERN_ERR "%s: Unable to get HRT (status=%#10x)\n", pHba->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) if (pHba->hrt->num_entries * pHba->hrt->entry_len << 2 > size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) int newsize = pHba->hrt->num_entries * pHba->hrt->entry_len << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) dma_free_coherent(&pHba->pDev->dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) pHba->hrt, pHba->hrt_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) size = newsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) pHba->hrt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) } while(pHba->hrt == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) * Query one scalar group value or a whole scalar group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) static int adpt_i2o_query_scalar(adpt_hba* pHba, int tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) int group, int field, void *buf, int buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) u16 opblk[] = { 1, 0, I2O_PARAMS_FIELD_GET, group, 1, field };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) u8 *opblk_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) dma_addr_t opblk_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) u8 *resblk_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) dma_addr_t resblk_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /* 8 bytes for header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) resblk_va = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) sizeof(u8) * (8 + buflen), &resblk_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (resblk_va == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) printk(KERN_CRIT "%s: query scalar failed; Out of memory.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) opblk_va = dma_alloc_coherent(&pHba->pDev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) sizeof(opblk), &opblk_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if (opblk_va == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) resblk_va, resblk_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) printk(KERN_CRIT "%s: query operation failed; Out of memory.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) if (field == -1) /* whole group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) opblk[4] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) memcpy(opblk_va, opblk, sizeof(opblk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) size = adpt_i2o_issue_params(I2O_CMD_UTIL_PARAMS_GET, pHba, tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) opblk_va, opblk_pa, sizeof(opblk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) resblk_va, resblk_pa, sizeof(u8)*(8+buflen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) dma_free_coherent(&pHba->pDev->dev, sizeof(opblk), opblk_va, opblk_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (size == -ETIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) resblk_va, resblk_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) printk(KERN_WARNING "%s: issue params failed; Timed out.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) } else if (size == -EINTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) resblk_va, resblk_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) printk(KERN_WARNING "%s: issue params failed; Interrupted.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) memcpy(buf, resblk_va+8, buflen); /* cut off header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) resblk_va, resblk_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) if (size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) return buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) /* Issue UTIL_PARAMS_GET or UTIL_PARAMS_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) * This function can be used for all UtilParamsGet/Set operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) * The OperationBlock is given in opblk-buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) * and results are returned in resblk-buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) * Note that the minimum sized resblk is 8 bytes and contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) * ResultCount, ErrorInfoSize, BlockStatus and BlockSize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) static int adpt_i2o_issue_params(int cmd, adpt_hba* pHba, int tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) void *opblk_va, dma_addr_t opblk_pa, int oplen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) void *resblk_va, dma_addr_t resblk_pa, int reslen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) u32 msg[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) u32 *res = (u32 *)resblk_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) int wait_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) msg[0] = NINE_WORD_MSG_SIZE | SGL_OFFSET_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) msg[1] = cmd << 24 | HOST_TID << 12 | tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) msg[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) msg[5] = 0x54000000 | oplen; /* OperationBlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) msg[6] = (u32)opblk_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) msg[7] = 0xD0000000 | reslen; /* ResultBlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) msg[8] = (u32)resblk_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if ((wait_status = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 20))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) printk("adpt_i2o_issue_params: post_wait failed (%p)\n", resblk_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) return wait_status; /* -DetailedStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) if (res[1]&0x00FF0000) { /* BlockStatus != SUCCESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) printk(KERN_WARNING "%s: %s - Error:\n ErrorInfoSize = 0x%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) "BlockStatus = 0x%02x, BlockSize = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) pHba->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) (cmd == I2O_CMD_UTIL_PARAMS_SET) ? "PARAMS_SET"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) : "PARAMS_GET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) res[1]>>24, (res[1]>>16)&0xFF, res[1]&0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) return -((res[1] >> 16) & 0xFF); /* -BlockStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) return 4 + ((res[1] & 0x0000FFFF) << 2); /* bytes used in resblk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) static s32 adpt_i2o_quiesce_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) u32 msg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) /* SysQuiesce discarded if IOP not in READY or OPERATIONAL state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) if((pHba->status_block->iop_state != ADAPTER_STATE_READY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) (pHba->status_block->iop_state != ADAPTER_STATE_OPERATIONAL)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) msg[1] = I2O_CMD_SYS_QUIESCE<<24|HOST_TID<<12|ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 240))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) printk(KERN_INFO"dpti%d: Unable to quiesce (status=%#x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) pHba->unit, -ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) printk(KERN_INFO"dpti%d: Quiesced.\n",pHba->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) * Enable IOP. Allows the IOP to resume external operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) static int adpt_i2o_enable_hba(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) u32 msg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) if(!pHba->status_block){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) /* Enable only allowed on READY state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if(pHba->status_block->iop_state == ADAPTER_STATE_OPERATIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) if(pHba->status_block->iop_state != ADAPTER_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) msg[0]=FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) msg[1]=I2O_CMD_SYS_ENABLE<<24|HOST_TID<<12|ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) msg[2]= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) msg[3]= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) if ((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 240))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) printk(KERN_WARNING"%s: Could not enable (status=%#10x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) pHba->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) PDEBUG("%s: Enabled.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) adpt_i2o_status_get(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) static int adpt_i2o_systab_send(adpt_hba* pHba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) u32 msg[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) msg[0] = I2O_MESSAGE_SIZE(12) | SGL_OFFSET_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) msg[1] = I2O_CMD_SYS_TAB_SET<<24 | HOST_TID<<12 | ADAPTER_TID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) msg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) msg[4] = (0<<16) | ((pHba->unit+2) << 12); /* Host 0 IOP ID (unit + 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) msg[5] = 0; /* Segment 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) * Provide three SGL-elements:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) * System table (SysTab), Private memory space declaration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) * Private i/o space declaration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) msg[6] = 0x54000000 | sys_tbl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) msg[7] = (u32)sys_tbl_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) msg[8] = 0x54000000 | 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) msg[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) msg[10] = 0xD4000000 | 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) msg[11] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) if ((ret=adpt_i2o_post_wait(pHba, msg, sizeof(msg), 120))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) printk(KERN_INFO "%s: Unable to set SysTab (status=%#10x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) pHba->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) PINFO("%s: SysTab set.\n", pHba->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) /*============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) *============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) #ifdef UARTDELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) static static void adpt_delay(int millisec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) for (i = 0; i < millisec; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) udelay(1000); /* delay for one millisecond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) static struct scsi_host_template driver_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) .name = "dpt_i2o",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) .proc_name = "dpt_i2o",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) .show_info = adpt_show_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) .info = adpt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) .queuecommand = adpt_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) .eh_abort_handler = adpt_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) .eh_device_reset_handler = adpt_device_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) .eh_bus_reset_handler = adpt_bus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .eh_host_reset_handler = adpt_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .bios_param = adpt_bios_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) .slave_configure = adpt_slave_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) .can_queue = MAX_TO_IOP_MESSAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) .this_id = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) static int __init adpt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) adpt_hba *pHba, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) printk("Loading Adaptec I2O RAID: Version " DPT_I2O_VERSION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) error = adpt_detect(&driver_template);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) if (hba_chain == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) for (pHba = hba_chain; pHba; pHba = pHba->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) error = scsi_add_host(pHba->host, &pHba->pDev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) scsi_scan_host(pHba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) for (pHba = hba_chain; pHba; pHba = next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) next = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) scsi_remove_host(pHba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) static void __exit adpt_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) adpt_hba *pHba, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) for (pHba = hba_chain; pHba; pHba = next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) next = pHba->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) adpt_release(pHba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) module_init(adpt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) module_exit(adpt_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags