Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)                           dpti_ioctl.h  -  description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)                              -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     begin                : Thu Sep 7 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     copyright            : (C) 2001 by Adaptec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     See Documentation/scsi/dpti.rst for history, notes, license info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     and credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *                                                                         *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *                                                                         *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * This file is generated from  osd_unix.h                                 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #ifndef _dpti_ioctl_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define _dpti_ioctl_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) // IOCTL interface commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifndef _IOWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) # define _IOWR(x,y,z)	(((x)<<8)|y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef _IOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) # define _IOW(x,y,z)	(((x)<<8)|y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #ifndef _IOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) # define _IOR(x,y,z)	(((x)<<8)|y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #ifndef _IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) # define _IO(x,y)	(((x)<<8)|y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* EATA PassThrough Command	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EATAUSRCMD      _IOWR('D',65,EATA_CP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Set Debug Level If Enabled	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DPT_DEBUG       _IOW('D',66,int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Get Signature Structure	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DPT_SIGNATURE   _IOR('D',67,dpt_sig_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #if defined __bsdi__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DPT_SIGNATURE_PACKED   _IOR('D',67,dpt_sig_S_Packed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Get Number Of DPT Adapters	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DPT_NUMCTRLS    _IOR('D',68,int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Get Adapter Info Structure	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DPT_CTRLINFO    _IOR('D',69,CtrlInfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Get Statistics If Enabled	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DPT_STATINFO    _IO('D',70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Clear Stats If Enabled	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DPT_CLRSTAT     _IO('D',71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Get System Info Structure	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DPT_SYSINFO     _IOR('D',72,sysInfo_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* Set Timeout Value		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DPT_TIMEOUT     _IO('D',73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* Get config Data  		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DPT_CONFIG      _IO('D',74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Get Blink LED Code	        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DPT_BLINKLED    _IOR('D',75,int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Get Statistical information (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DPT_STATS_INFO        _IOR('D',80,STATS_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Clear the statistical information          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DPT_STATS_CLEAR       _IO('D',81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Get Performance metrics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DPT_PERF_INFO        _IOR('D',82,dpt_perf_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* Send an I2O command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define I2OUSRCMD	_IO('D',76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Inform driver to re-acquire LCT information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define I2ORESCANCMD	_IO('D',77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Inform driver to reset adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define I2ORESETCMD	_IO('D',78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* See if the target is mounted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DPT_TARGET_BUSY	_IOR('D',79, TARGET_BUSY_T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)   /* Structure Returned From Get Controller Info                             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	uCHAR    state;            /* Operational state               */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	uCHAR    id;               /* Host adapter SCSI id            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int      vect;             /* Interrupt vector number         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int      base;             /* Base I/O address                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int      njobs;            /* # of jobs sent to HA            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int      qdepth;           /* Controller queue depth.         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int      wakebase;         /* mpx wakeup base index.          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	uINT     SGsize;           /* Scatter/Gather list size.       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned heads;            /* heads for drives on cntlr.      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned sectors;          /* sectors for drives on cntlr.    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	uCHAR    do_drive32;       /* Flag for Above 16 MB Ability    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	uCHAR    BusQuiet;         /* SCSI Bus Quiet Flag             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	char     idPAL[4];         /* 4 Bytes Of The ID Pal           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	uCHAR    primary;          /* 1 For Primary, 0 For Secondary  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	uCHAR    eataVersion;      /* EATA Version                    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	uINT     cpLength;         /* EATA Command Packet Length      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	uINT     spLength;         /* EATA Status Packet Length       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	uCHAR    drqNum;           /* DRQ Index (0,5,6,7)             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	uCHAR    flag1;            /* EATA Flags 1 (Byte 9)           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	uCHAR    flag2;            /* EATA Flags 2 (Byte 30)          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } CtrlInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	uSHORT length;		// Remaining length of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	uSHORT drvrHBAnum;	// Relative HBA # used by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	uINT baseAddr;		// Base I/O address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	uSHORT blinkState;	// Blink LED state (0=Not in blink LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	uCHAR pciBusNum;	// PCI Bus # (Optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	uCHAR pciDeviceNum;	// PCI Device # (Optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	uSHORT hbaFlags;	// Miscellaneous HBA flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	uSHORT Interrupt;	// Interrupt set for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #   if (defined(_DPT_ARC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uINT baseLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ADAPTER_OBJECT *AdapterObject;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	LARGE_INTEGER DmaLogicalAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PVOID DmaVirtualAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	LARGE_INTEGER ReplyLogicalAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	PVOID ReplyVirtualAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #   else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	uINT reserved1;		// Reserved for future expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	uINT reserved2;		// Reserved for future expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	uINT reserved3;		// Reserved for future expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #   endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } drvrHBAinfo_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) typedef struct TARGET_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)   uLONG channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)   uLONG id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)   uLONG lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)   uLONG isBusy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } TARGET_BUSY_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)