Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * CXL Flash Device Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	       Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2018 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OCXL_MAX_IRQS	4	/* Max interrupts per process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct ocxlflash_irqs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u32 virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	void __iomem *vtrig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* OCXL hardware AFU associated with the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct ocxl_hw_afu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct ocxlflash_context *ocxl_ctx; /* Host context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct pci_dev *pdev;		/* PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct device *dev;		/* Generic device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	bool perst_same_image;		/* Same image loaded on perst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	struct ocxl_fn_config fcfg;	/* DVSEC config of the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	struct ocxl_afu_config acfg;	/* AFU configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int fn_actag_base;		/* Function acTag base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	int fn_actag_enabled;		/* Function acTag number enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int afu_actag_base;		/* AFU acTag base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	int afu_actag_enabled;		/* AFU acTag number enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	phys_addr_t ppmmio_phys;	/* Per process MMIO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	phys_addr_t gmmio_phys;		/* Global AFU MMIO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	void __iomem *gmmio_virt;	/* Global MMIO map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	void *link_token;		/* Link token for the SPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct idr idr;			/* IDR to manage contexts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int max_pasid;			/* Maximum number of contexts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bool is_present;		/* Function has AFUs defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum ocxlflash_ctx_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	CLOSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	OPENED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	STARTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ocxlflash_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct ocxl_hw_afu *hw_afu;	/* HW AFU back pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct address_space *mapping;	/* Mapping for pseudo filesystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	bool master;			/* Whether this is a master context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	int pe;				/* Process element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	phys_addr_t psn_phys;		/* Process mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	u64 psn_size;			/* Process mapping size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	spinlock_t slock;		/* Protects irq/fault/event updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	wait_queue_head_t wq;		/* Wait queue for poll and interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct mutex state_mutex;	/* Mutex to update context state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	enum ocxlflash_ctx_state state;	/* Context state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct ocxlflash_irqs *irqs;	/* Pointer to array of structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	int num_irqs;			/* Number of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	bool pending_irq;		/* Pending interrupt on the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	ulong irq_bitmap;		/* Bits indicating pending irq num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	u64 fault_addr;			/* Address that triggered the fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	u64 fault_dsisr;		/* Value of dsisr register at fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	bool pending_fault;		/* Pending translation fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };