^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CXL Flash Device Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2015 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _CXLFLASH_MAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _CXLFLASH_MAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "backend.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CXLFLASH_NAME "cxlflash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CXLFLASH_MAX_ADAPTERS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_IBM_CORSA 0x04F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_DEVICE_ID_IBM_BRIARD 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Since there is only one target, make it 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CXLFLASH_TARGET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CXLFLASH_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Really only one target per bus since the Texan is directly attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* FC defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FC_MTIP_CMDCONFIG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FC_MTIP_STATUS 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FC_PNAME 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FC_CONFIG 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FC_CONFIG2 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FC_STATUS 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FC_ERROR 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FC_ERRCAP 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FC_ERRMSK 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FC_CNT_CRCERR 0x538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FC_CRC_THRESH 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FC_MTIP_STATUS_MASK 0x30ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FC_MTIP_STATUS_ONLINE 0x20ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FC_MTIP_STATUS_OFFLINE 0x10ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* TIMEOUT and RETRY definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* AFU command timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* AFU command room retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MC_ROOM_RETRY_CNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* FC CRC clear periodic timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC_CRC_THRESH 100 /* threshold in 5 mins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* VPD defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CXLFLASH_VPD_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WWPN_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WWPN_BUF_LEN (WWPN_LEN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum undo_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) UNDO_NOOP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FREE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) UNMAP_ONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) UNMAP_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) UNMAP_THREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dev_dependent_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u64 max_sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CXLFLASH_OCXL_DEV 0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline const struct cxlflash_backend_ops *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cxlflash_assign_ops(struct dev_dependent_vals *ddv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct cxlflash_backend_ops *ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_OCXL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ddv->flags & CXLFLASH_OCXL_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ops = &cxlflash_ocxl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_CXL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!(ddv->flags & CXLFLASH_OCXL_DEV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ops = &cxlflash_cxl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct asyc_intr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLR_FC_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LINK_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCAN_HOST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* _CXLFLASH_MAIN_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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