Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2014- QLogic Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * www.qlogic.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * bfi_reg.h ASIC register defines for all QLogic BR-series adapter ASICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #ifndef __BFI_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define __BFI_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HOSTFN0_INT_STATUS		0x00014000	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HOSTFN1_INT_STATUS		0x00014100	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HOSTFN2_INT_STATUS		0x00014300	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HOSTFN3_INT_STATUS		0x00014400	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HOSTFN0_INT_MSK			0x00014004	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HOSTFN1_INT_MSK			0x00014104	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HOSTFN2_INT_MSK			0x00014304	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HOSTFN3_INT_MSK			0x00014404	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HOST_PAGE_NUM_FN0		0x00014008	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HOST_PAGE_NUM_FN1		0x00014108	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HOST_PAGE_NUM_FN2		0x00014308	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HOST_PAGE_NUM_FN3		0x00014408	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define APP_PLL_LCLK_CTL_REG		0x00014204	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define __P_LCLK_PLL_LOCK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define __APP_PLL_LCLK_SRAM_USE_100MHZ	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define __APP_PLL_LCLK_RESET_TIMER_MK	0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define __APP_PLL_LCLK_RESET_TIMER_SH	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define __APP_PLL_LCLK_RESET_TIMER(_v)	((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define __APP_PLL_LCLK_LOGIC_SOFT_RESET	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define __APP_PLL_LCLK_CNTLMT0_1_MK	0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define __APP_PLL_LCLK_CNTLMT0_1_SH	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define __APP_PLL_LCLK_CNTLMT0_1(_v)	((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define __APP_PLL_LCLK_JITLMT0_1_MK	0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define __APP_PLL_LCLK_JITLMT0_1_SH	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define __APP_PLL_LCLK_JITLMT0_1(_v)	((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define __APP_PLL_LCLK_HREF		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define __APP_PLL_LCLK_HDIV		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define __APP_PLL_LCLK_P0_1_MK		0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define __APP_PLL_LCLK_P0_1_SH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define __APP_PLL_LCLK_P0_1(_v)		((_v) << __APP_PLL_LCLK_P0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define __APP_PLL_LCLK_Z0_2_MK		0x000000e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define __APP_PLL_LCLK_Z0_2_SH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define __APP_PLL_LCLK_Z0_2(_v)		((_v) << __APP_PLL_LCLK_Z0_2_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define __APP_PLL_LCLK_RSEL200500	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define __APP_PLL_LCLK_ENARST		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define __APP_PLL_LCLK_BYPASS		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define __APP_PLL_LCLK_LRESETN		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define __APP_PLL_LCLK_ENABLE		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define APP_PLL_SCLK_CTL_REG		0x00014208	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define __P_SCLK_PLL_LOCK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define __APP_PLL_SCLK_RESET_TIMER_MK	0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define __APP_PLL_SCLK_RESET_TIMER_SH	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define __APP_PLL_SCLK_RESET_TIMER(_v)	((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define __APP_PLL_SCLK_LOGIC_SOFT_RESET	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define __APP_PLL_SCLK_CNTLMT0_1_MK	0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define __APP_PLL_SCLK_CNTLMT0_1_SH	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define __APP_PLL_SCLK_CNTLMT0_1(_v)	((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define __APP_PLL_SCLK_JITLMT0_1_MK	0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define __APP_PLL_SCLK_JITLMT0_1_SH	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define __APP_PLL_SCLK_JITLMT0_1(_v)	((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define __APP_PLL_SCLK_HREF		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define __APP_PLL_SCLK_HDIV		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define __APP_PLL_SCLK_P0_1_MK		0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define __APP_PLL_SCLK_P0_1_SH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define __APP_PLL_SCLK_P0_1(_v)		((_v) << __APP_PLL_SCLK_P0_1_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define __APP_PLL_SCLK_Z0_2_MK		0x000000e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define __APP_PLL_SCLK_Z0_2_SH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define __APP_PLL_SCLK_Z0_2(_v)		((_v) << __APP_PLL_SCLK_Z0_2_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define __APP_PLL_SCLK_RSEL200500	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define __APP_PLL_SCLK_ENARST		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define __APP_PLL_SCLK_BYPASS		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define __APP_PLL_SCLK_LRESETN		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define __APP_PLL_SCLK_ENABLE		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define __ENABLE_MAC_AHB_1		0x00800000	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define __ENABLE_MAC_AHB_0		0x00400000	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define __ENABLE_MAC_1			0x00200000	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define __ENABLE_MAC_0			0x00100000	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HOST_SEM0_REG			0x00014230	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HOST_SEM1_REG			0x00014234	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HOST_SEM2_REG			0x00014238	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HOST_SEM3_REG			0x0001423c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HOST_SEM4_REG			0x00014610	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HOST_SEM5_REG			0x00014614	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define HOST_SEM6_REG			0x00014618	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HOST_SEM7_REG			0x0001461c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HOST_SEM0_INFO_REG		0x00014240	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HOST_SEM1_INFO_REG		0x00014244	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HOST_SEM2_INFO_REG		0x00014248	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HOST_SEM3_INFO_REG		0x0001424c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HOST_SEM4_INFO_REG		0x00014620	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HOST_SEM5_INFO_REG		0x00014624	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HOST_SEM6_INFO_REG		0x00014628	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HOST_SEM7_INFO_REG		0x0001462c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HOSTFN0_LPU0_CMD_STAT		0x00019000	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HOSTFN0_LPU1_CMD_STAT		0x00019004	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HOSTFN1_LPU0_CMD_STAT		0x00019010	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HOSTFN1_LPU1_CMD_STAT		0x00019014	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HOSTFN2_LPU0_CMD_STAT		0x00019150	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HOSTFN2_LPU1_CMD_STAT		0x00019154	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HOSTFN3_LPU0_CMD_STAT		0x00019160	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HOSTFN3_LPU1_CMD_STAT		0x00019164	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LPU0_HOSTFN0_CMD_STAT		0x00019008	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LPU1_HOSTFN0_CMD_STAT		0x0001900c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LPU0_HOSTFN1_CMD_STAT		0x00019018	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LPU1_HOSTFN1_CMD_STAT		0x0001901c	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LPU0_HOSTFN2_CMD_STAT		0x00019158	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LPU1_HOSTFN2_CMD_STAT		0x0001915c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LPU0_HOSTFN3_CMD_STAT		0x00019168	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LPU1_HOSTFN3_CMD_STAT		0x0001916c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PSS_CTL_REG			0x00018800	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define __PSS_I2C_CLK_DIV_MK		0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define __PSS_I2C_CLK_DIV_SH		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define __PSS_I2C_CLK_DIV(_v)		((_v) << __PSS_I2C_CLK_DIV_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define __PSS_LMEM_INIT_DONE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define __PSS_LMEM_RESET		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define __PSS_LMEM_INIT_EN		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define __PSS_LPU1_RESET		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define __PSS_LPU0_RESET		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PSS_ERR_STATUS_REG		0x00018810	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ERR_SET_REG			0x00018818	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PSS_GPIO_OUT_REG		0x000188c0	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define __PSS_GPIO_OUT_REG		0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PSS_GPIO_OE_REG			0x000188c8	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define __PSS_GPIO_OE_REG		0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HOSTFN0_LPU_MBOX0_0		0x00019200	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HOSTFN1_LPU_MBOX0_8		0x00019260	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LPU_HOSTFN0_MBOX0_0		0x00019280	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LPU_HOSTFN1_MBOX0_8		0x000192e0	/* cb/ct	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HOSTFN2_LPU_MBOX0_0		0x00019400	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HOSTFN3_LPU_MBOX0_8		0x00019460	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LPU_HOSTFN2_MBOX0_0		0x00019480	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LPU_HOSTFN3_MBOX0_8		0x000194e0	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HOST_MSIX_ERR_INDEX_FN0		0x0001400c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HOST_MSIX_ERR_INDEX_FN1		0x0001410c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HOST_MSIX_ERR_INDEX_FN2		0x0001430c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HOST_MSIX_ERR_INDEX_FN3		0x0001440c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MBIST_CTL_REG			0x00014220	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define __EDRAM_BISTR_START		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MBIST_STAT_REG			0x00014224	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ETH_MAC_SER_REG			0x00014288	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define __APP_EMS_CKBUFAMPIN		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define __APP_EMS_REFCLKSEL		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define __APP_EMS_CMLCKSEL		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define __APP_EMS_REFCKBUFEN2		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define __APP_EMS_REFCKBUFEN1		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define __APP_EMS_CHANNEL_SEL		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FNC_PERS_REG			0x00014604	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define __F3_FUNCTION_ACTIVE		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define __F3_FUNCTION_MODE		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define __F3_PORT_MAP_MK		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define __F3_PORT_MAP_SH		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define __F3_PORT_MAP(_v)		((_v) << __F3_PORT_MAP_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define __F3_VM_MODE			0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define __F3_INTX_STATUS_MK		0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define __F3_INTX_STATUS_SH		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define __F3_INTX_STATUS(_v)		((_v) << __F3_INTX_STATUS_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define __F2_FUNCTION_ACTIVE		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define __F2_FUNCTION_MODE		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define __F2_PORT_MAP_MK		0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define __F2_PORT_MAP_SH		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define __F2_PORT_MAP(_v)		((_v) << __F2_PORT_MAP_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define __F2_VM_MODE			0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define __F2_INTX_STATUS_MK		0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define __F2_INTX_STATUS_SH		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define __F2_INTX_STATUS(_v)		((_v) << __F2_INTX_STATUS_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define __F1_FUNCTION_ACTIVE		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define __F1_FUNCTION_MODE		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define __F1_PORT_MAP_MK		0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define __F1_PORT_MAP_SH		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define __F1_PORT_MAP(_v)		((_v) << __F1_PORT_MAP_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define __F1_VM_MODE			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define __F1_INTX_STATUS_MK		0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define __F1_INTX_STATUS_SH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define __F1_INTX_STATUS(_v)		((_v) << __F1_INTX_STATUS_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define __F0_FUNCTION_ACTIVE		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define __F0_FUNCTION_MODE		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define __F0_PORT_MAP_MK		0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define __F0_PORT_MAP_SH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define __F0_PORT_MAP(_v)		((_v) << __F0_PORT_MAP_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define __F0_VM_MODE			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define __F0_INTX_STATUS		0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	__F0_INTX_STATUS_MSIX = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	__F0_INTX_STATUS_INTA = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	__F0_INTX_STATUS_INTB = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	__F0_INTX_STATUS_INTC = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	__F0_INTX_STATUS_INTD = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OP_MODE				0x0001460c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define __APP_ETH_CLK_LOWSPEED		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define __GLOBAL_CORECLK_HALFSPEED	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define __GLOBAL_FCOE_MODE		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define FW_INIT_HALT_P0			0x000191ac	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define __FW_INIT_HALT_P		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FW_INIT_HALT_P1			0x000191bc	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PMM_1T_RESET_REG_P0		0x0002381c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define __PMM_1T_RESET_P		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PMM_1T_RESET_REG_P1		0x00023c1c	/* ct		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * Catapult-2 specific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CT2_PCI_CPQ_BASE		0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CT2_PCI_APP_BASE		0x00030100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CT2_PCI_ETH_BASE		0x00030400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * APP block registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CT2_HOSTFN_INT_STATUS		(CT2_PCI_APP_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CT2_HOSTFN_INTR_MASK		(CT2_PCI_APP_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CT2_HOSTFN_PERSONALITY0		(CT2_PCI_APP_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define __PME_STATUS_			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define __PF_VF_BAR_SIZE_MODE__MK	0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define __PF_VF_BAR_SIZE_MODE__SH	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define __PF_VF_BAR_SIZE_MODE_(_v)	((_v) << __PF_VF_BAR_SIZE_MODE__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define __FC_LL_PORT_MAP__MK		0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define __FC_LL_PORT_MAP__SH		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define __FC_LL_PORT_MAP_(_v)		((_v) << __FC_LL_PORT_MAP__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define __PF_VF_ACTIVE_			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define __PF_VF_CFG_RDY_		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define __PF_VF_ENABLE_			0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define __PF_DRIVER_ACTIVE_		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define __PF_PME_SEND_ENABLE_		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define __PF_EXROM_OFFSET__MK		0x00000ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define __PF_EXROM_OFFSET__SH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define __PF_EXROM_OFFSET_(_v)		((_v) << __PF_EXROM_OFFSET__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define __FC_LL_MODE_			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define __PF_INTX_PIN_			0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CT2_HOSTFN_PERSONALITY1		(CT2_PCI_APP_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define __PF_NUM_QUEUES1__MK		0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define __PF_NUM_QUEUES1__SH		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define __PF_NUM_QUEUES1_(_v)		((_v) << __PF_NUM_QUEUES1__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define __PF_VF_QUE_OFFSET1__MK		0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define __PF_VF_QUE_OFFSET1__SH		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define __PF_VF_QUE_OFFSET1_(_v)	((_v) << __PF_VF_QUE_OFFSET1__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define __PF_VF_NUM_QUEUES__MK		0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define __PF_VF_NUM_QUEUES__SH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define __PF_VF_NUM_QUEUES_(_v)		((_v) << __PF_VF_NUM_QUEUES__SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define __PF_VF_QUE_OFFSET_		0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CT2_HOSTFN_PAGE_NUM		(CT2_PCI_APP_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR	(CT2_PCI_APP_BASE + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * Catapult-2 CPQ block registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CT2_HOSTFN_LPU0_MBOX0		(CT2_PCI_CPQ_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CT2_HOSTFN_LPU1_MBOX0		(CT2_PCI_CPQ_BASE + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CT2_LPU0_HOSTFN_MBOX0		(CT2_PCI_CPQ_BASE + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CT2_LPU1_HOSTFN_MBOX0		(CT2_PCI_CPQ_BASE + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CT2_HOSTFN_LPU0_CMD_STAT	(CT2_PCI_CPQ_BASE + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CT2_HOSTFN_LPU1_CMD_STAT	(CT2_PCI_CPQ_BASE + 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CT2_LPU0_HOSTFN_CMD_STAT	(CT2_PCI_CPQ_BASE + 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CT2_LPU1_HOSTFN_CMD_STAT	(CT2_PCI_CPQ_BASE + 0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CT2_HOSTFN_LPU0_READ_STAT	(CT2_PCI_CPQ_BASE + 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CT2_HOSTFN_LPU1_READ_STAT	(CT2_PCI_CPQ_BASE + 0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CT2_LPU0_HOSTFN_MBOX0_MSK	(CT2_PCI_CPQ_BASE + 0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CT2_LPU1_HOSTFN_MBOX0_MSK	(CT2_PCI_CPQ_BASE + 0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CT2_HOST_SEM0_REG		0x000148f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CT2_HOST_SEM1_REG		0x000148f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CT2_HOST_SEM2_REG		0x000148f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CT2_HOST_SEM3_REG		0x000148fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CT2_HOST_SEM4_REG		0x00014900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CT2_HOST_SEM5_REG		0x00014904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CT2_HOST_SEM6_REG		0x00014908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CT2_HOST_SEM7_REG		0x0001490c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CT2_HOST_SEM0_INFO_REG		0x000148b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CT2_HOST_SEM1_INFO_REG		0x000148b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CT2_HOST_SEM2_INFO_REG		0x000148b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CT2_HOST_SEM3_INFO_REG		0x000148bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CT2_HOST_SEM4_INFO_REG		0x000148c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CT2_HOST_SEM5_INFO_REG		0x000148c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CT2_HOST_SEM6_INFO_REG		0x000148c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CT2_HOST_SEM7_INFO_REG		0x000148cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CT2_APP_PLL_LCLK_CTL_REG	0x00014808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define __APP_LPUCLK_HALFSPEED		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define __APP_PLL_LCLK_LOAD		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define __APP_PLL_LCLK_FBCNT_MK		0x1fe00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define __APP_PLL_LCLK_FBCNT_SH		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define __APP_PLL_LCLK_FBCNT(_v)	((_v) << __APP_PLL_SCLK_FBCNT_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	__APP_PLL_LCLK_FBCNT_425_MHZ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	__APP_PLL_LCLK_FBCNT_468_MHZ = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define __APP_PLL_LCLK_EXTFB		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define __APP_PLL_LCLK_ENOUTS		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define __APP_PLL_LCLK_RATE		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CT2_APP_PLL_SCLK_CTL_REG	0x0001480c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define __P_SCLK_PLL_LOCK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define __APP_PLL_SCLK_REFCLK_SEL	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define __APP_PLL_SCLK_CLK_DIV2		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define __APP_PLL_SCLK_LOAD		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define __APP_PLL_SCLK_FBCNT_MK		0x0ff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define __APP_PLL_SCLK_FBCNT_SH		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define __APP_PLL_SCLK_FBCNT(_v)	((_v) << __APP_PLL_SCLK_FBCNT_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	__APP_PLL_SCLK_FBCNT_NORM = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	__APP_PLL_SCLK_FBCNT_10G_FC = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define __APP_PLL_SCLK_EXTFB		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define __APP_PLL_SCLK_ENOUTS		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define __APP_PLL_SCLK_RATE		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CT2_PCIE_MISC_REG		0x00014804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define __ETH_CLK_ENABLE_PORT1		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CT2_CHIP_MISC_PRG		0x000148a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define __ETH_CLK_ENABLE_PORT0		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define __APP_LPU_SPEED			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CT2_MBIST_STAT_REG		0x00014818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CT2_MBIST_CTL_REG		0x0001481c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CT2_PMM_1T_CONTROL_REG_P0	0x0002381c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define __PMM_1T_PNDB_P			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CT2_PMM_1T_CONTROL_REG_P1	0x00023c1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CT2_WGN_STATUS			0x00014990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define __A2T_AHB_LOAD			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define __WGN_READY			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define __GLBL_PF_VF_CFG_RDY		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CT2_NFC_STS_REG			0x00027410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CT2_NFC_CSR_CLR_REG		0x00027420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CT2_NFC_CSR_SET_REG		0x00027424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define __HALT_NFC_CONTROLLER		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define __NFC_CONTROLLER_HALTED		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CT2_RSC_GPR15_REG		0x0002765c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CT2_CSI_FW_CTL_REG		0x00027080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CT2_CSI_FW_CTL_SET_REG		0x00027088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CT2_CSI_MAC0_CONTROL_REG	0x000270d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define __CSI_MAC_RESET			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define __CSI_MAC_AHB_RESET		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CT2_CSI_MAC1_CONTROL_REG	0x000270d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CT2_CSI_MAC_CONTROL_REG(__n)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	(CT2_CSI_MAC0_CONTROL_REG +	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	(__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CT2_NFC_FLASH_STS_REG		0x00014834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * Name semaphore registers based on usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BFA_IOC0_HBEAT_REG		HOST_SEM0_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BFA_IOC0_STATE_REG		HOST_SEM1_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BFA_IOC1_HBEAT_REG		HOST_SEM2_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BFA_IOC1_STATE_REG		HOST_SEM3_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define BFA_FW_USE_COUNT		HOST_SEM4_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BFA_IOC_FAIL_SYNC		HOST_SEM5_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * CT2 semaphore register locations changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CT2_BFA_IOC0_HBEAT_REG		CT2_HOST_SEM0_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CT2_BFA_IOC0_STATE_REG		CT2_HOST_SEM1_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CT2_BFA_IOC1_HBEAT_REG		CT2_HOST_SEM2_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CT2_BFA_IOC1_STATE_REG		CT2_HOST_SEM3_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CT2_BFA_FW_USE_COUNT		CT2_HOST_SEM4_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CT2_BFA_IOC_FAIL_SYNC		CT2_HOST_SEM5_INFO_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CPE_Q_NUM(__fn, __q)	(((__fn) << 2) + (__q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define RME_Q_NUM(__fn, __q)	(((__fn) << 2) + (__q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  * And corresponding host interrupt status bit field defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define __HFN_INT_CPE_Q0	0x00000001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define __HFN_INT_CPE_Q1	0x00000002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define __HFN_INT_CPE_Q2	0x00000004U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define __HFN_INT_CPE_Q3	0x00000008U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define __HFN_INT_CPE_Q4	0x00000010U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define __HFN_INT_CPE_Q5	0x00000020U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define __HFN_INT_CPE_Q6	0x00000040U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define __HFN_INT_CPE_Q7	0x00000080U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define __HFN_INT_RME_Q0	0x00000100U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define __HFN_INT_RME_Q1	0x00000200U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define __HFN_INT_RME_Q2	0x00000400U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define __HFN_INT_RME_Q3	0x00000800U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define __HFN_INT_RME_Q4	0x00001000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define __HFN_INT_RME_Q5	0x00002000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define __HFN_INT_RME_Q6	0x00004000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define __HFN_INT_RME_Q7	0x00008000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define __HFN_INT_ERR_EMC	0x00010000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define __HFN_INT_ERR_LPU0	0x00020000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define __HFN_INT_ERR_LPU1	0x00040000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define __HFN_INT_ERR_PSS	0x00080000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define __HFN_INT_MBOX_LPU0	0x00100000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define __HFN_INT_MBOX_LPU1	0x00200000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define __HFN_INT_MBOX1_LPU0	0x00400000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define __HFN_INT_MBOX1_LPU1	0x00800000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define __HFN_INT_LL_HALT	0x01000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define __HFN_INT_CPE_MASK	0x000000ffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define __HFN_INT_RME_MASK	0x0000ff00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define __HFN_INT_ERR_MASK	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	(__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	 __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define __HFN_INT_FN0_MASK	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	(__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define __HFN_INT_FN1_MASK	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	(__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)  * Host interrupt status defines for catapult-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define __HFN_INT_MBOX_LPU0_CT2	0x00010000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define __HFN_INT_MBOX_LPU1_CT2	0x00020000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define __HFN_INT_ERR_PSS_CT2	0x00040000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define __HFN_INT_ERR_LPU0_CT2	0x00080000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define __HFN_INT_ERR_LPU1_CT2	0x00100000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define __HFN_INT_CPQ_HALT_CT2	0x00200000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define __HFN_INT_ERR_WGN_CT2	0x00400000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define __HFN_INT_ERR_LEHRX_CT2	0x00800000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define __HFN_INT_ERR_LEHTX_CT2	0x01000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define __HFN_INT_ERR_MASK_CT2	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	(__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	 __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	 __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	 __HFN_INT_ERR_LEHTX_CT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define __HFN_INT_FN0_MASK_CT2	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	(__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define __HFN_INT_FN1_MASK_CT2	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	(__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)  * asic memory map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PSS_SMEM_PAGE_START		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PSS_SMEM_PGNUM(_pg0, _ma)	((_pg0) + ((_ma) >> 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PSS_SMEM_PGOFF(_ma)		((_ma) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #endif /* __BFI_REG_H__ */