^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 Broadcom. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact Information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux-drivers@broadcom.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _BEISCSI_MAIN_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _BEISCSI_MAIN_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <scsi/iscsi_proto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <scsi/libiscsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <scsi/scsi_transport_iscsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_NAME "be2iscsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BUILD_STR "11.4.0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BE_NAME "Emulex OneConnect" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "Open-iSCSI Driver version" BUILD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_DESC BE_NAME " " "Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BE_VENDOR_ID 0x19A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ELX_VENDOR_ID 0x10DF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* DEVICE ID's for BE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BE_DEVICE_ID1 0x212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OC_DEVICE_ID1 0x702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OC_DEVICE_ID2 0x703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* DEVICE ID's for BE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BE_DEVICE_ID2 0x222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OC_DEVICE_ID3 0x712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* DEVICE ID for SKH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OC_SKH_ID1 0x722
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BE2_IO_DEPTH 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BE2_MAX_SESSIONS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BE2_TMFS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BE2_NOPOUT_REQ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BE2_SGE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BE2_DEFPDU_HDR_SZ 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BE2_DEFPDU_DATA_SZ 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BE2_MAX_NUM_CQ_PROC 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX_CPUS 64U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BEISCSI_MAX_NUM_CPUS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BEISCSI_VER_STRLEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BEISCSI_SGLIST_ELEMENTS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * be invalidated at a time, consider it before changing the value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * BEISCSI_CMD_PER_LUN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BEISCSI_MAX_FRAGS_INIT 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BE_SENSE_INFO_SIZE 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BE_ISCSI_PDU_HEADER_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BE_MIN_MEM_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX_CMD_SZ 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IIOC_SCSI_DATA 0x05 /* Write Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * hardware needs the async PDU buffers to be posted in multiples of 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * So have atleast 8 of them by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (phwi->phwi_ctxt->pasync_ctx[ulp_num])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /********* Memory BAR register ************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Disable" may still globally block interrupts in addition to individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * interrupt masks; a mechanism for the device driver to block all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * atomically without having to arbitrate for the PCI Interrupt Disable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * with the OS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /********* ISR0 Register offset **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CEV_ISR0_OFFSET 0xC18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CEV_ISR_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Macros for reading/writing a protection domain or CSR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * in BladeEngine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DB_TXULP0_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DB_RXULP0_OFFSET 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /********* Event Q door bell *************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DB_EQ_OFFSET DB_CQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Clear the interrupt for this eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Must be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Higher Order EQ_ID bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DB_EQ_HIGH_SET_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DB_EQ_HIGH_FEILD_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Number of event entries processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Rearm bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /********* Compl Q door bell *************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DB_CQ_OFFSET 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Higher Order CQ_ID bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DB_CQ_HIGH_SET_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DB_CQ_HIGH_FEILD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Number of event entries processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Rearm bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PAGES_REQUIRED(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MEM_DESCR_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BEISCSI_DEFQ_HDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BEISCSI_DEFQ_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum be_mem_enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) HWI_MEM_ADDN_CONTEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) HWI_MEM_WRB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HWI_MEM_WRBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) HWI_MEM_SGLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) HWI_MEM_SGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) HWI_MEM_TEMPLATE_HDR_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HWI_MEM_ASYNC_DATA_BUF_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HWI_MEM_ASYNC_HEADER_RING_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) HWI_MEM_ASYNC_DATA_RING_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) HWI_MEM_TEMPLATE_HDR_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) HWI_MEM_ASYNC_DATA_BUF_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) HWI_MEM_ASYNC_HEADER_RING_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HWI_MEM_ASYNC_DATA_RING_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ISCSI_MEM_GLOBAL_HEADER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SE_MEM_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct be_bus_address32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct be_bus_address64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long long address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct be_bus_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct be_bus_address32 a32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct be_bus_address64 a64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct mem_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct be_bus_address bus_address; /* Bus address of location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void *virtual_address; /* virtual address to the location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int size; /* Size required by memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct be_mem_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int size_in_bytes; /* Size required by memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int num_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mem_array *mem_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct sgl_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int sgl_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct iscsi_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct iscsi_sge *pfrag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct hba_parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int ios_per_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int cxns_per_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int icds_per_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int num_sge_per_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int defpdu_hdr_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int defpdu_data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int num_cq_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int num_eq_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int wrbs_per_cxn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int hwi_ws_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (phwi_ctrlr->wrb_context[cri].ulp_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct hwi_wrb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spinlock_t wrb_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct wrb_handle **pwrb_handle_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct wrb_handle **pwrb_handle_basestd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct iscsi_wrb *plast_wrb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned short alloc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned short free_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned short wrb_handles_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned short cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint8_t ulp_num; /* ULP to which CID binded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint32_t doorbell_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ulp_cid_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned short *cid_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned short avlbl_cids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned short cid_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned short cid_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #include "be.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define chip_be2(phba) (phba->generation == BE_GEN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define chip_be3_r(phba) (phba->generation == BE_GEN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BEISCSI_ULP0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BEISCSI_ULP1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BEISCSI_ULP_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BEISCSI_ULP0_LOADED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BEISCSI_ULP1_LOADED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BEISCSI_ULP0_AVLBL_CID(phba) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define BEISCSI_ULP1_AVLBL_CID(phba) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct beiscsi_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct hba_parameters params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct hwi_controller *phwi_ctrlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int mem_req[SE_MEM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* PCI BAR mapped addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 __iomem *csr_va; /* CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 __iomem *db_va; /* Door Bell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 __iomem *pci_va; /* PCI Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* PCI representation of our HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pci_dev *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int num_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int nxt_cqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) char *msi_name[MAX_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct be_mem_descriptor *init_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned short io_sgl_alloc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned short io_sgl_free_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned short io_sgl_hndl_avbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct sgl_handle **io_sgl_hndl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned short eh_sgl_alloc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned short eh_sgl_free_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned short eh_sgl_hndl_avbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sgl_handle **eh_sgl_hndl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) spinlock_t io_sgl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spinlock_t mgmt_sgl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spinlock_t async_pdu_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct list_head hba_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BE_MAX_SESSION 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BE_INVALID_CID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BE_SET_CID_TO_CRI(cri_index, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (phba->cid_to_cri_map[cid] = cri_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned short cid_to_cri_map[BE_MAX_SESSION];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct iscsi_endpoint **ep_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct beiscsi_conn **conn_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct iscsi_iface *ipv4_iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct iscsi_iface *ipv6_iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * group together since they are used most frequently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * for cid to cri conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BEISCSI_PHYS_PORT_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int phys_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* valid values of phys_port id are 0, 1, 2, 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int eqid_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int cqid_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (phba->fw_config.iscsi_cid_count[ulp_num])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned short iscsi_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint16_t dual_ulp_aware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long ulp_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } fw_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BEISCSI_HBA_ONLINE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BEISCSI_HBA_LINK_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BEISCSI_HBA_BOOT_FOUND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BEISCSI_HBA_BOOT_WORK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define BEISCSI_HBA_UER_SUPP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BEISCSI_HBA_PCI_ERR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define BEISCSI_HBA_FW_TIMEOUT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define BEISCSI_HBA_IN_UE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BEISCSI_HBA_IN_TPE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define BEISCSI_HBA_IN_ERR ((1 << BEISCSI_HBA_PCI_ERR) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (1 << BEISCSI_HBA_FW_TIMEOUT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (1 << BEISCSI_HBA_IN_UE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (1 << BEISCSI_HBA_IN_TPE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 optic_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct delayed_work eqd_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* update EQ delay timer every 1000ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BEISCSI_EQD_UPDATE_INTERVAL 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct timer_list hw_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* check for UE every 1000ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BEISCSI_UE_DETECT_INTERVAL 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 ue2rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct delayed_work recover_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct work_struct sess_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bool mac_addr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 mac_address[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 port_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 port_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) char fw_ver_str[BEISCSI_VER_STRLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct workqueue_struct *wq; /* The actuak work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct be_ctrl_info ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int interface_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct be_aic_obj aic_obj[MAX_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int attr_log_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int (*iotask_fn)(struct iscsi_task *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uint32_t num_sg, uint32_t xferlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) uint32_t writedir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct boot_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int s_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct be_dma_mem nonemb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) BEISCSI_BOOT_REOPEN_SESS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) BEISCSI_BOOT_GET_SHANDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BEISCSI_BOOT_GET_SINFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BEISCSI_BOOT_LOGOUT_SESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BEISCSI_BOOT_CREATE_KSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct mgmt_session_info boot_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct iscsi_boot_kset *boot_kset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } boot_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct work_struct boot_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define beiscsi_hba_is_online(phba) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (!beiscsi_hba_in_error((phba)) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) test_bit(BEISCSI_HBA_ONLINE, &phba->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct beiscsi_session {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct dma_pool *bhs_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * struct beiscsi_conn - iscsi connection structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct beiscsi_conn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct iscsi_conn *conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct beiscsi_hba *phba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 exp_statsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 doorbell_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 beiscsi_conn_cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct beiscsi_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned short login_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct wrb_handle *plogin_wrb_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct sgl_handle *plogin_sgl_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct beiscsi_session *beiscsi_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct iscsi_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* This structure is used by the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct pdu_data_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 dw[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct amap_pdu_data_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 opcode[6]; /* opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 rsvd0[2]; /* should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 rsvd1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 final_bit; /* F bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 rsvd2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 ahs_length[8]; /* no AHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 data_len_hi[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 data_len_lo[16]; /* DataSegmentLength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 lun[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 itt[32]; /* ITT; initiator task tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 rsvd3[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 exp_stat_sn[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 rsvd4[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 data_sn[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 buffer_offset[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 rsvd5[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct be_cmd_bhs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct iscsi_scsi_req iscsi_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned char pad1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct pdu_data_out iscsi_data_pdu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned char pad2[BE_SENSE_INFO_SIZE -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sizeof(struct pdu_data_out)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct beiscsi_io_task {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct wrb_handle *pwrb_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct sgl_handle *psgl_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct beiscsi_conn *conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct scsi_cmnd *scsi_cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct hwi_wrb_context *pwrb_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) itt_t libiscsi_itt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct be_cmd_bhs *cmd_bhs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct be_bus_address bhs_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned short bhs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dma_addr_t mtask_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint32_t mtask_data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint8_t wrb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct be_nonio_bhs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct iscsi_hdr iscsi_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned char pad1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct pdu_data_out iscsi_data_pdu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned char pad2[BE_SENSE_INFO_SIZE -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sizeof(struct pdu_data_out)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct be_status_bhs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct iscsi_scsi_req iscsi_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned char pad1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * The plus 2 below is to hold the sense info length that gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * DMA'ed by RxULP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned char sense_info[BE_SENSE_INFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct iscsi_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 dw[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct amap_iscsi_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 addr_hi[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 addr_lo[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 sge_offset[22]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 rsvd0[9]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 last_sge; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 len[17]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 rsvd1[15]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct beiscsi_offload_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 dw[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define OFFLD_PARAMS_ERL 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define OFFLD_PARAMS_DDE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define OFFLD_PARAMS_HDE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define OFFLD_PARAMS_IR2T 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define OFFLD_PARAMS_IMD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct amap_beiscsi_offload_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 max_burst_length[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 max_send_data_segment_length[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 first_burst_length[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 erl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 dde[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 hde[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 ir2t[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 imd[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 data_seq_inorder[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 pdu_seq_inorder[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 max_r2t[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 pad[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 exp_statsn[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 max_recv_data_segment_length[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct hd_async_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct be_bus_address pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) void *pbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 buffer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u16 cri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u8 is_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 is_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u8 in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) (BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * This has list of async PDUs that are waiting to be processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Buffers live in this list for a brief duration before they get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * processed and posted back to hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Note that we don't really need one cri_wait_queue per async_entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * We need one cri_wait_queue per CRI. Its easier to manage if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * is tagged along with the async_entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct hd_async_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct cri_wait_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned short hdr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int bytes_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int bytes_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* handles posted to FW resides here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct hd_async_handle *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct hd_async_handle *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct hd_async_buf_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct be_bus_address pa_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) void *va_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) void *ring_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct hd_async_handle *handle_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * hd_async_context is declared for each ULP supporting iSCSI function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct hd_async_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct hd_async_buf_context async_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct hd_async_buf_context async_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * When unsol PDU is in, it needs to be chained till all the bytes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * received and then processing is done. hd_async_entry is created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * based on the cid_count for each ULP. When unsol PDU comes in based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * on the conn_id it needs to be added to the correct async_entry wq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Below defined cid_to_async_cri_map is used to reterive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * async_cri_map for a particular connection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * This array is initialized after beiscsi_create_wrb_rings returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * - this method takes more memory space, fixed to 2K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * - any support for connections greater than this the array size needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * to be incremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * This is a variable size array. Don`t add anything after this field!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct hd_async_entry *async_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct i_t_dpdu_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 dw[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct amap_i_t_dpdu_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u8 db_addr_hi[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u8 db_addr_lo[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 code[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 cid[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u8 dpl[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 index[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 num_cons[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u8 rsvd0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u8 final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u8 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct amap_i_t_dpdu_cqe_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 db_addr_hi[32]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 db_addr_lo[32]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 code[6]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 num_cons; /* DWORD 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 rsvd0[8]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 dpl[17]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 index[16]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 cid[13]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u8 rsvd1; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 final; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 valid; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define CQE_VALID_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define CQE_CODE_MASK 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define CQE_CID_MASK 0x0000FFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define EQE_VALID_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define EQE_MAJORCODE_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define EQE_RESID_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct be_eq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 dw[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct amap_eq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 valid; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 major_code[3]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 minor_code[12]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u8 resource_id[16]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct cq_db {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 dw[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct amap_cq_db {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 qid[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u8 event[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 rsvd0[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 num_popped[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 rearm[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 rsvd1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) void beiscsi_process_eq(struct beiscsi_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct iscsi_wrb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 dw[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define WRB_TYPE_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SKH_WRB_TYPE_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define BE_WRB_TYPE_OFFSET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (pwrb->dw[0] |= (wrb_type << type_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct amap_iscsi_wrb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u8 lun[14]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 lt; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 invld; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 wrb_idx[8]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u8 dsp; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u8 dmsg; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 undr_run; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 over_run; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u8 type[4]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 ptr2nextwrb[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u8 r2t_exp_dtl[24]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u8 sgl_icd_idx[12]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u8 rsvd0[20]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u8 exp_data_sn[32]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u8 cmdsn_itt[32]; /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 dif_ref_tag[32]; /* DWORD 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 sge0_addr_hi[32]; /* DWORD 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 sge0_addr_lo[32]; /* DWORD 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u8 sge0_offset[22]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 pbs; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u8 dif_mode[2]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u8 rsvd1[6]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u8 sge0_last; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u8 sge0_len[17]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u8 dif_meta_tag[14]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 sge0_in_ddr; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u8 sge1_addr_hi[32]; /* DWORD 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u8 sge1_addr_lo[32]; /* DWORD 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u8 sge1_r2t_offset[22]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u8 rsvd2[9]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 sge1_last; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u8 sge1_len[17]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u8 rsvd3[2]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 sge1_in_ddr; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct amap_iscsi_wrb_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 r2t_exp_dtl[25]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 rsvd0[2]; /* DWORD 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 type[5]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u8 ptr2nextwrb[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u8 wrb_idx[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u8 lun[16]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 sgl_idx[16]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u8 exp_data_sn[32]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u8 cq_id[16]; /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 rsvd1[16]; /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u8 cmdsn_itt[32]; /* DWORD 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 sge0_addr_hi[32]; /* DWORD 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 sge0_addr_lo[32]; /* DWORD 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u8 sge0_offset[24]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 rsvd2[7]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u8 sge0_last; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 sge0_len[17]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u8 rsvd3[7]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u8 diff_enbl; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u8 u_run; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 o_run; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u8 invld; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u8 dsp; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 dmsg; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 rsvd4; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 lt; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 sge1_addr_hi[32]; /* DWORD 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u8 sge1_addr_lo[32]; /* DWORD 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u8 sge1_r2t_offset[24]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u8 rsvd5[7]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u8 sge1_last; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u8 sge1_len[17]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 rsvd6[15]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct hwi_wrb_context **pcontext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct iscsi_task *task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) void hwi_ring_cq_db(struct beiscsi_hba *phba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned int id, unsigned int num_processed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned char rearm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct pdu_nop_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 dw[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct amap_pdu_nop_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 opcode[6]; /* opcode 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u8 i_bit; /* I Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u8 x_bit; /* reserved; should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 fp_bit_filler1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 f_bit; /* always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u8 reserved1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u8 ahs_length[8]; /* no AHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u8 data_len_hi[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u8 data_len_lo[16]; /* DataSegmentLength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 lun[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 itt[32]; /* initiator id for ping or 0xffffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u8 ttt[32]; /* target id for ping or 0xffffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 cmd_sn[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u8 exp_stat_sn[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u8 reserved5[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define PDUBASE_OPCODE_MASK 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define PDUBASE_DATALENHI_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define PDUBASE_DATALENLO_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct pdu_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 dw[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct amap_pdu_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 opcode[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 i_bit; /* immediate bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 x_bit; /* reserved, always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 reserved1[24]; /* opcode-specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 ahs_length[8]; /* length units is 4 byte words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 data_len_hi[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u8 data_len_lo[16]; /* DatasegmentLength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 lun[64]; /* lun or opcode-specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 itt[32]; /* initiator task tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 reserved4[224];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct iscsi_target_context_update_wrb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 dw[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Pseudo amap definition in which each bit of the actual structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * as a byte: used to calculate offset/shift/mask of each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define BE_TGT_CTX_UPDT_CMD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct amap_iscsi_target_context_update_wrb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 lun[14]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 lt; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u8 invld; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 wrb_idx[8]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u8 dsp; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u8 dmsg; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 undr_run; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u8 over_run; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 type[4]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u8 ptr2nextwrb[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u8 max_burst_length[19]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u8 rsvd0[5]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u8 rsvd1[15]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u8 max_send_data_segment_length[17]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u8 first_burst_length[14]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u8 rsvd2[2]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u8 rsvd3[5]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u8 session_state[3]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u8 rsvd4[16]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u8 tx_jumbo; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u8 hde; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u8 dde; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 erl[2]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u8 domain_id[5]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u8 mode; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u8 imd; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u8 ir2t; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u8 notpredblq[2]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u8 compltonack; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u8 stat_sn[32]; /* DWORD 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u8 pad_addr_hi[32]; /* DWORD 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u8 pad_addr_lo[32]; /* DWORD 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u8 rsvd5[32]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u8 rsvd6[32]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u8 rsvd7[32]; /* DWORD 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u8 rsvd8[32]; /* DWORD 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u8 rsvd9[32]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u8 rsvd10[32]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define BEISCSI_MAX_CXNS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct amap_iscsi_target_context_update_wrb_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u8 max_burst_length[24]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u8 rsvd0[3]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u8 type[5]; /* DWORD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u8 ptr2nextwrb[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u8 wrb_idx[8]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u8 rsvd1[16]; /* DWORD 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u8 max_send_data_segment_length[24]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u8 rsvd2[8]; /* DWORD 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u8 first_burst_length[24]; /* DWORD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 rsvd3[8]; /* DOWRD 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u8 max_r2t[16]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u8 rsvd4; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u8 hde; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u8 dde; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u8 erl[2]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u8 rsvd5[6]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u8 imd; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u8 ir2t; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u8 rsvd6[3]; /* DWORD 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u8 stat_sn[32]; /* DWORD 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u8 rsvd7[32]; /* DWORD 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u8 rsvd8[32]; /* DWORD 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u8 max_recv_dataseg_len[24]; /* DWORD 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u8 rsvd9[8]; /* DWORD 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u8 rsvd10[32]; /* DWORD 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u8 rsvd11[32]; /* DWORD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u8 max_cxns[16]; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u8 rsvd12[11]; /* DWORD 11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 invld; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u8 rsvd13;/* DWORD 11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 dmsg; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 data_seq_inorder; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u8 pdu_seq_inorder; /* DWORD 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u8 rsvd14[32]; /*DWORD 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u8 rsvd15[32]; /* DWORD 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u8 rsvd16[32]; /* DWORD 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u8 rsvd17[32]; /* DWORD 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct be_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 pages; /* queue size in pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 id; /* queue id assigned by beklib */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 num; /* number of elements in queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 cidx; /* consumer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u32 pidx; /* producer index -- not used by most rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 item_size; /* size in bytes of one object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u8 ulp_num; /* ULP to which CID binded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u16 register_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u16 doorbell_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 doorbell_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) void *va; /* The virtual address of the ring. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * should be last to allow 32 & 64 bit debugger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * extensions to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct hwi_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct hwi_wrb_context *wrb_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct hwi_context_memory *phwi_ctxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) enum hwh_type_enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) HWH_TYPE_IO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) HWH_TYPE_LOGOUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) HWH_TYPE_TMF = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) HWH_TYPE_NOP = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) HWH_TYPE_IO_RD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) HWH_TYPE_LOGIN = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) HWH_TYPE_INVALID = 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct wrb_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned short wrb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct iscsi_task *pio_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct iscsi_wrb *pwrb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct hwi_context_memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct be_eq_obj be_eq[MAX_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct be_queue_info be_cq[MAX_CPUS - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct be_queue_info *be_wrbq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Create array of ULP number for below entries as DEFQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * will be created for both ULP if iSCSI Protocol is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * loaded on both ULP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Logging related definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define __beiscsi_log(phba, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define beiscsi_log(phba, level, mask, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) uint32_t log_value = phba->attr_log_enable; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (((mask) & log_value) || (level[1] <= '3')) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) __beiscsi_log(phba, level, fmt, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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