^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/acorn/scsi/fas216.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * FAS216 generic driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef FAS216_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define FAS216_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "queue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "msgqueue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* FAS register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* transfer count low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_CTCL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_STCL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* transfer count medium */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_CTCM (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_STCM (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* fifo data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_FF (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_CMD (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMD_NOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMD_FLUSHFIFO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMD_RESETCHIP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMD_RESETSCSI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMD_TRANSFERINFO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMD_INITCMDCOMPLETE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMD_MSGACCEPTED 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMD_PADBYTES 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_SETATN 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMD_RSETATN 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMD_SELECTWOATN 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMD_SELECTATN 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD_SELECTATNSTOP 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMD_ENABLESEL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMD_DISABLESEL 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMD_SELECTATN3 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_RESEL3 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMD_WITHDMA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* status register (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_STAT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STAT_IO (1 << 0) /* IO phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STAT_CD (1 << 1) /* CD phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STAT_MSG (1 << 2) /* MSG phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STAT_TRANSFERDONE (1 << 3) /* Transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STAT_TRANSFERCNTZ (1 << 4) /* Transfer counter is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STAT_PARITYERROR (1 << 5) /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STAT_REALBAD (1 << 6) /* Something bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STAT_INT (1 << 7) /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STAT_BUSMASK (STAT_MSG|STAT_CD|STAT_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STAT_DATAOUT (0) /* Data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STAT_DATAIN (STAT_IO) /* Data in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STAT_COMMAND (STAT_CD) /* Command out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STAT_STATUS (STAT_CD|STAT_IO) /* Status In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STAT_MESGOUT (STAT_MSG|STAT_CD) /* Message out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STAT_MESGIN (STAT_MSG|STAT_CD|STAT_IO) /* Message In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* bus ID for select / reselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_SDID (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BUSID(target) ((target) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Interrupt status register (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_INST (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define INST_SELWOATN (1 << 0) /* Select w/o ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INST_SELATN (1 << 1) /* Select w/ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define INST_RESELECTED (1 << 2) /* Reselected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define INST_FUNCDONE (1 << 3) /* Function done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INST_BUSSERVICE (1 << 4) /* Bus service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define INST_DISCONNECT (1 << 5) /* Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define INST_ILLEGALCMD (1 << 6) /* Illegal command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INST_BUSRESET (1 << 7) /* SCSI Bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Timeout register (write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_STIM (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Sequence step register (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_IS (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IS_BITS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IS_SELARB 0x00 /* Select & Arb ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IS_MSGBYTESENT 0x01 /* One byte message sent*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IS_NOTCOMMAND 0x02 /* Not in command state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IS_EARLYPHASE 0x03 /* Early phase change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IS_COMPLETE 0x04 /* Command ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IS_SOF 0x08 /* Sync off flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Transfer period step (write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_STP (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Synchronous Offset (write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_SOF (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Fifo state register (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_CFIS (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CFIS_CF 0x1f /* Num bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CFIS_IS 0xe0 /* Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* config register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_CNTL1 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CNTL1_CID (7 << 0) /* Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CNTL1_STE (1 << 3) /* Self test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CNTL1_PERE (1 << 4) /* Parity enable reporting en. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CNTL1_PTE (1 << 5) /* Parity test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CNTL1_DISR (1 << 6) /* Disable Irq on SCSI reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CNTL1_ETM (1 << 7) /* Extended Timing Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clock conversion factor (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_CLKF (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLKF_F37MHZ 0x00 /* 35.01 - 40 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLKF_F10MHZ 0x02 /* 10 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLKF_F12MHZ 0x03 /* 10.01 - 15 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLKF_F17MHZ 0x04 /* 15.01 - 20 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKF_F22MHZ 0x05 /* 20.01 - 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKF_F27MHZ 0x06 /* 25.01 - 30 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKF_F32MHZ 0x07 /* 30.01 - 35 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Chip test register (write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_FTM (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEST_FTM 0x01 /* Force target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEST_FIM 0x02 /* Force initiator mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEST_FHI 0x04 /* Force high impedance mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Configuration register 2 (read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_CNTL2 (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CNTL2_PGDP (1 << 0) /* Pass Th/Generate Data Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CNTL2_PGRP (1 << 1) /* Pass Th/Generate Reg Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CNTL2_ACDPE (1 << 2) /* Abort on Cmd/Data Parity Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CNTL2_S2FE (1 << 3) /* SCSI2 Features Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CNTL2_TSDR (1 << 4) /* Tristate DREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CNTL2_SBO (1 << 5) /* Select Byte Order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CNTL2_ENF (1 << 6) /* Enable features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CNTL2_DAE (1 << 7) /* Data Alignment Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Configuration register 3 (read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define REG_CNTL3 (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CNTL3_BS8 (1 << 0) /* Burst size 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CNTL3_MDM (1 << 1) /* Modify DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CNTL3_LBTM (1 << 2) /* Last Byte Transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CNTL3_FASTCLK (1 << 3) /* Fast SCSI clocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CNTL3_FASTSCSI (1 << 4) /* Fast SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CNTL3_G2CB (1 << 5) /* Group2 SCSI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CNTL3_QTAG (1 << 6) /* Enable 3 byte msgs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CNTL3_ADIDCHK (1 << 7) /* Additional ID check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* High transfer count (read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define REG_CTCH (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define REG_STCH (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* ID register (read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define REG_ID (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define REG_DAL (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PHASE_IDLE, /* we're not planning on doing anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PHASE_SELECTION, /* selecting a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PHASE_SELSTEPS, /* selection with command steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PHASE_COMMAND, /* command sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PHASE_MESSAGESENT, /* selected, and we're sending cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PHASE_DATAOUT, /* data out to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PHASE_DATAIN, /* data in from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PHASE_MSGIN, /* message in from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PHASE_MSGIN_DISCONNECT, /* disconnecting from bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PHASE_MSGOUT, /* after message out phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PHASE_MSGOUT_EXPECT, /* expecting message out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PHASE_STATUS, /* status from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PHASE_DONE /* Command complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } phase_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DMA_OUT, /* DMA from memory to chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DMA_IN /* DMA from chip to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } fasdmadir_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) fasdma_none, /* No dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) fasdma_pio, /* PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) fasdma_pseudo, /* Pseudo DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fasdma_real_block, /* Real DMA, on block by block basis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) fasdma_real_all /* Real DMA, on request by request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } fasdmatype_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) neg_wait, /* Negotiate with device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) neg_inprogress, /* Negotiation sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) neg_complete, /* Negotiation complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) neg_targcomplete, /* Target completed negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) neg_invalid /* Negotiation not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } neg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MAGIC 0x441296bdUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define NR_MSGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define FASCAP_DMA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define FASCAP_PSEUDODMA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long magic_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spinlock_t host_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct Scsi_Host *host; /* host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct scsi_cmnd *SCpnt; /* currently processing command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct scsi_cmnd *origSCpnt; /* original connecting command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct scsi_cmnd *reqSCpnt; /* request sense command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct scsi_cmnd *rstSCpnt; /* reset command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct scsi_cmnd *pending_SCpnt[8]; /* per-device pending commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int next_pending; /* next pending device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Error recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) wait_queue_head_t eh_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct timer_list eh_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int rst_dev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int rst_bus_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* driver information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) phase_t phase; /* current phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void __iomem *io_base; /* iomem base of FAS216 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int io_shift; /* shift to adjust reg offsets by */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned char cfg[4]; /* configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) const char *type; /* chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int irq; /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int dma; /* dma channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct scsi_pointer SCp; /* current commands data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MsgQueue_t msgs; /* message queue for connected device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int async_stp; /* Async transfer STP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned char msgin_fifo; /* bytes in fifo at time of message in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned char message[256]; /* last message received from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned char disconnectable:1; /* this command can be disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned char aborting:1; /* aborting command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } scsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* statistics information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int removes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int fins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int reads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int writes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int miscs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int disconnects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int aborts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int bus_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int host_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* configuration information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned char clockrate; /* clock rate of FAS device (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned char select_timeout; /* timeout (R5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned char sync_max_depth; /* Synchronous xfer max fifo depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned char wide_max_size; /* Maximum wide transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char cntl3; /* Control Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int asyncperiod; /* Async transfer period (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int capabilities; /* driver capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int disconnect_ok:1; /* Disconnects allowed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } ifcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* queue handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) Queue_t issue; /* issue queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) Queue_t disconnected; /* disconnected command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* per-device info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct fas216_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned char disconnect_ok:1; /* device can disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned char parity_enabled:1; /* parity checking enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned char parity_check:1; /* need to check parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned char period; /* sync xfer period in (*4ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned char stp; /* synchronous transfer period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned char sof; /* synchronous offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned char wide_xfer; /* currently negociated wide transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) neg_t sync_state; /* synchronous transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) neg_t wide_state; /* wide transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } device[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long busyluns[64/sizeof(unsigned long)];/* array of bits indicating LUNs busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) fasdmatype_t transfer_type; /* current type of DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fasdmatype_t (*setup) (struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, fasdmatype_t min_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void (*pseudo)(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void (*stop) (struct Scsi_Host *host, struct scsi_pointer *SCp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* miscellaneous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int internal_done; /* flag to indicate request done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct scsi_eh_save ses; /* holds request sense restore info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long magic_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } FAS216_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Function: int fas216_init (struct Scsi_Host *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Purpose : initialise FAS/NCR/AMD SCSI structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Params : instance - a driver-specific filled-out structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Returns : 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) extern int fas216_init (struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Function: int fas216_add (struct Scsi_Host *instance, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Purpose : initialise FAS/NCR/AMD SCSI ic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Params : instance - a driver-specific filled-out structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Returns : 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) extern int fas216_add (struct Scsi_Host *instance, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Function: int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Purpose : queue a command for adapter to process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Params : h - host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * : SCpnt - Command to queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Returns : 0 - success, else error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) extern int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Function: int fas216_noqueue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Purpose : queue a command for adapter to process, and process it to completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Params : h - host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * : SCpnt - Command to queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Returns : 0 - success, else error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) extern int fas216_noqueue_command(struct Scsi_Host *, struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Function: irqreturn_t fas216_intr (FAS216_Info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Purpose : handle interrupts from the interface to progress a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Params : info - interface to service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) extern irqreturn_t fas216_intr (FAS216_Info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) extern void fas216_remove (struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Function: void fas216_release (struct Scsi_Host *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Purpose : release all resources and put everything to bed for FAS/NCR/AMD SCSI ic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Params : instance - a driver-specific filled-out structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Returns : 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) extern void fas216_release (struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) extern void fas216_print_host(FAS216_Info *info, struct seq_file *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) extern void fas216_print_stats(FAS216_Info *info, struct seq_file *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) extern void fas216_print_devices(FAS216_Info *info, struct seq_file *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Function: int fas216_eh_abort(struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Purpose : abort this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Params : SCpnt - command to abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Returns : FAILED if unable to abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) extern int fas216_eh_abort(struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Function: int fas216_eh_device_reset(struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Purpose : Reset the device associated with this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Params : SCpnt - command specifing device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Returns : FAILED if unable to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) extern int fas216_eh_device_reset(struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Function: int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Purpose : Reset the complete bus associated with this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Params : SCpnt - command specifing bus to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Returns : FAILED if unable to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) extern int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Function: int fas216_eh_host_reset(struct scsi_cmnd *SCpnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Purpose : Reset the host associated with this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Params : SCpnt - command specifing host to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Returns : FAILED if unable to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) extern int fas216_eh_host_reset(struct scsi_cmnd *SCpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif /* FAS216_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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