^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** O.S : Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ** FILE NAME : arcmsr_hba.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** BY : Nick Cheng, C.L. Huang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** Description: SCSI RAID Device Driver for Areca RAID Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** Web site: www.areca.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** E-mail: support@areca.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ** 3. The name of the author may not be used to endorse or promote products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ** derived from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ** Firmware Specification, see Documentation/scsi/arcmsr_spec.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <scsi/scsi_transport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <scsi/scsicam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include "arcmsr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_VERSION(ARCMSR_DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int msix_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) module_param(msix_enable, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int msi_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param(msi_enable, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param(host_can_queue, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param(cmd_per_lun, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int dma_mask_64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) module_param(dma_mask_64, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int set_date_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_param(set_date_time, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ARCMSR_SLEEPTIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ARCMSR_RETRYCOUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static wait_queue_head_t wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int arcmsr_abort(struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int arcmsr_bus_reset(struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int arcmsr_bios_param(struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct block_device *bdev, sector_t capacity, int *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int arcmsr_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct pci_device_id *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int arcmsr_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void arcmsr_remove(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void arcmsr_shutdown(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void arcmsr_iop_init(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 intmask_org);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void arcmsr_request_device_map(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void arcmsr_message_isr_bh_fn(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const char *arcmsr_info(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void arcmsr_set_iop_datetime(struct timer_list *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) queue_depth = ARCMSR_MAX_CMD_PERLUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return scsi_change_queue_depth(sdev, queue_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct scsi_host_template arcmsr_scsi_host_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "Areca SAS/SATA RAID driver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .info = arcmsr_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .queuecommand = arcmsr_queue_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .eh_abort_handler = arcmsr_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .eh_bus_reset_handler = arcmsr_bus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .bios_param = arcmsr_bios_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .change_queue_depth = arcmsr_adjust_disk_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .this_id = ARCMSR_SCSI_INITIATOR_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .shost_attrs = arcmsr_host_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .no_write_same = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct pci_device_id arcmsr_device_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .driver_data = ACB_ADAPTER_TYPE_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .driver_data = ACB_ADAPTER_TYPE_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .driver_data = ACB_ADAPTER_TYPE_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .driver_data = ACB_ADAPTER_TYPE_B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .driver_data = ACB_ADAPTER_TYPE_D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .driver_data = ACB_ADAPTER_TYPE_A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .driver_data = ACB_ADAPTER_TYPE_C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .driver_data = ACB_ADAPTER_TYPE_E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1886),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .driver_data = ACB_ADAPTER_TYPE_F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0, 0}, /* Terminating entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct pci_driver arcmsr_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "arcmsr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .id_table = arcmsr_device_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .probe = arcmsr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .remove = arcmsr_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .suspend = arcmsr_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .resume = arcmsr_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .shutdown = arcmsr_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void arcmsr_free_io_queue(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) acb->dma_coherent2, acb->dma_coherent_handle2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct pci_dev *pdev = acb->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (acb->adapter_type){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case ACB_ADAPTER_TYPE_A:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!acb->pmuA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case ACB_ADAPTER_TYPE_B:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void __iomem *mem_base0, *mem_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!mem_base0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!mem_base1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) iounmap(mem_base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) acb->mem_base0 = mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) acb->mem_base1 = mem_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case ACB_ADAPTER_TYPE_C:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!acb->pmuC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long addr, range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) addr = (unsigned long)pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) range = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mem_base0 = ioremap(addr, range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!mem_base0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pr_notice("arcmsr%d: memory mapping region fail\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) acb->mem_base0 = mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) acb->pmuE = ioremap(pci_resource_start(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!acb->pmuE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pr_notice("arcmsr%d: memory mapping region fail \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) acb->in_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) acb->out_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) acb->pmuF = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!acb->pmuF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_notice("arcmsr%d: memory mapping region fail\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(0, &acb->pmuF->host_int_status); /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) acb->in_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) acb->out_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iounmap(acb->pmuA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iounmap(acb->mem_base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) iounmap(acb->mem_base1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iounmap(acb->pmuC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) iounmap(acb->mem_base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) iounmap(acb->pmuE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) iounmap(acb->pmuF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) irqreturn_t handle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct AdapterControlBlock *acb = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) handle_state = arcmsr_interrupt(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return handle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int arcmsr_bios_param(struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct block_device *bdev, sector_t capacity, int *geom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int heads, sectors, cylinders, total_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (scsi_partsize(bdev, capacity, geom))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) total_capacity = capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) heads = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sectors = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cylinders = total_capacity / (heads * sectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (cylinders > 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) heads = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cylinders = total_capacity / (heads * sectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) geom[0] = heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) geom[1] = sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) geom[2] = cylinders;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (readl(®->outbound_intstatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ®->outbound_intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } /* max 20 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (readl(reg->iop2drv_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } /* max 20 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (readl(&phbcmu->outbound_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } /* max 20 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct MessageUnit_D *reg = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (readl(reg->outbound_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } /* max 20 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint32_t read_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) read_doorbell = readl(&phbcmu->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writel(0, &phbcmu->host_int_status); /*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pACB->in_doorbell = read_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } /* max 20 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int retry_count = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (arcmsr_hbaA_wait_msgint_ready(acb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) retry_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) timeout, retry count down = %d \n", acb->host->host_no, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } while (retry_count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int retry_count = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (arcmsr_hbaB_wait_msgint_ready(acb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) retry_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) timeout,retry count down = %d \n", acb->host->host_no, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } while (retry_count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct MessageUnit_C __iomem *reg = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) retry_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } while (retry_count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int retry_count = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct MessageUnit_D *reg = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (arcmsr_hbaD_wait_msgint_ready(pACB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) retry_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pr_notice("arcmsr%d: wait 'flush adapter "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "cache' timeout, retry count down = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pACB->host->host_no, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } while (retry_count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int retry_count = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct MessageUnit_E __iomem *reg = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(pACB->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (arcmsr_hbaE_wait_msgint_ready(pACB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) retry_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pr_notice("arcmsr%d: wait 'flush adapter "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "cache' timeout, retry count down = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pACB->host->host_no, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } while (retry_count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) arcmsr_hbaA_flush_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) arcmsr_hbaB_flush_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) arcmsr_hbaC_flush_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) arcmsr_hbaD_flush_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) arcmsr_hbaE_flush_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void arcmsr_hbaF_assign_regAddr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dma_addr_t host_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct MessageUnit_F __iomem *pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) memset(acb->dma_coherent2, 0xff, acb->completeQ_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) acb->message_wbuffer = (uint32_t *)round_up((unsigned long)acb->dma_coherent2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) acb->completeQ_size, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) acb->message_rbuffer = ((void *)acb->message_wbuffer) + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) acb->msgcode_rwbuffer = ((void *)acb->message_wbuffer) + 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) host_buffer_dma = round_up(acb->dma_coherent_handle2 + acb->completeQ_size, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pmuF = acb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* host buffer low address, bit0:1 all buffer active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* host buffer high address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* set host buffer physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bool rtn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) void *dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma_addr_t dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct pci_dev *pdev = acb->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &dma_coherent_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!dma_coherent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) acb->dma_coherent_handle2 = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) acb->dma_coherent2 = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) acb->pmuB = (struct MessageUnit_B *)dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) arcmsr_hbaB_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &dma_coherent_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!dma_coherent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) acb->dma_coherent_handle2 = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) acb->dma_coherent2 = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) acb->pmuD = (struct MessageUnit_D *)dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) arcmsr_hbaD_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint32_t completeQ_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) acb->ioqueue_size = roundup(completeQ_size, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &dma_coherent_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!dma_coherent){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) acb->dma_coherent_handle2 = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) acb->dma_coherent2 = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) acb->pCompletionQ = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) acb->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint32_t QueueDepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uint32_t depthTbl[] = {256, 512, 1024, 128, 64, 32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) arcmsr_wait_firmware_ready(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) QueueDepth = depthTbl[readl(&acb->pmuF->outbound_msgaddr1) & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) acb->completeQ_size = sizeof(struct deliver_completeQ) * QueueDepth + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) acb->ioqueue_size = roundup(acb->completeQ_size + MESG_RW_BUFFER_SIZE, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) &dma_coherent_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!dma_coherent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) acb->dma_coherent_handle2 = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) acb->dma_coherent2 = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) acb->pCompletionQ = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) acb->completionQ_entry = acb->completeQ_size / sizeof(struct deliver_completeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) acb->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) arcmsr_hbaF_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct pci_dev *pdev = acb->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) void *dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dma_addr_t dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct CommandControlBlock *ccb_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int i = 0, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned long cdb_phyaddr, next_ccb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned long roundup_ccbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned long max_xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned long max_sg_entrys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint32_t firm_config_version, curr_phy_upper32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) acb->devstate[i][j] = ARECA_RAID_GONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) max_xfer_len = ARCMSR_MAX_XFER_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) firm_config_version = acb->firm_cfg_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if((firm_config_version & 0xFF) >= 3){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) max_sg_entrys = (max_xfer_len/4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) acb->host->max_sectors = max_xfer_len/512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) acb->host->sg_tablesize = max_sg_entrys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) acb->uncache_size += acb->ioqueue_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if(!dma_coherent){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) acb->dma_coherent = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) acb->dma_coherent_handle = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) memset(dma_coherent, 0, acb->uncache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) acb->ccbsize = roundup_ccbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ccb_tmp = dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) curr_phy_upper32 = upper_32_bits(dma_coherent_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for(i = 0; i < acb->maxFreeCCB; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ccb_tmp->cdb_phyaddr = cdb_phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) acb->pccb_pool[i] = ccb_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ccb_tmp->acb = acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ccb_tmp->smid = (u32)i << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) INIT_LIST_HEAD(&ccb_tmp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) next_ccb_phy = dma_coherent_handle + roundup_ccbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) acb->maxFreeCCB = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) acb->host->can_queue = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dma_coherent_handle = next_ccb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (acb->adapter_type != ACB_ADAPTER_TYPE_F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) acb->dma_coherent_handle2 = dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) acb->dma_coherent2 = ccb_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) arcmsr_hbaB_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) arcmsr_hbaD_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) acb->pCompletionQ = acb->dma_coherent2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) acb->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void arcmsr_message_isr_bh_fn(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct AdapterControlBlock *acb = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct AdapterControlBlock, arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) char *acb_dev_map = (char *)acb->device_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint32_t __iomem *signature = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) char __iomem *devicemap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int target, lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct scsi_device *psdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) char diff, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) devicemap = (char __iomem *)(®->message_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) devicemap = (char __iomem *)(®->message_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) signature = (uint32_t __iomem *)(&acb->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) devicemap = (char __iomem *)(&acb->msgcode_rwbuffer[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) target++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) temp = readb(devicemap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) diff = (*acb_dev_map) ^ temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (diff != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *acb_dev_map = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) lun++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if ((diff & 0x01) == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) (temp & 0x01) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) scsi_add_device(acb->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 0, target, lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) } else if ((diff & 0x01) == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) && (temp & 0x01) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) psdev = scsi_device_lookup(acb->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) 0, target, lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (psdev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) scsi_remove_device(psdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) scsi_device_put(psdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) temp >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) diff >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) devicemap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) acb_dev_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int nvec, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (msix_enable == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) goto msi_int0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (nvec > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) msi_int0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (msi_enable == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (nvec == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_info(&pdev->dev, "msi enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) goto msi_int1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (nvec < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) msi_int1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) acb->vector_count = nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) for (i = 0; i < nvec; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) flags, "arcmsr", acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pr_warn("arcmsr%d: request_irq =%d failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) acb->host->host_no, pci_irq_vector(pdev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) free_irq(pci_irq_vector(pdev, i), acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pacb->fw_flag = FW_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) add_timer(&pacb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) add_timer(&pacb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct pci_dev *pcidev = acb->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (IS_DMA64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto dma32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) printk("arcmsr: set DMA 64 mask failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dma32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) printk("arcmsr: set DMA 32-bit mask failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct AdapterControlBlock *acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint8_t bus,dev_fun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) error = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if(error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if(!host){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto pci_disable_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) init_waitqueue_head(&wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) bus = pdev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_fun = pdev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) acb = (struct AdapterControlBlock *) host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) memset(acb,0,sizeof(struct AdapterControlBlock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) acb->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) acb->adapter_type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (arcmsr_set_dma_mask(acb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto scsi_host_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) acb->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) host->max_lun = ARCMSR_MAX_TARGETLUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) host->can_queue = host_can_queue; /* max simultaneous cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) host->cmd_per_lun = cmd_per_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) host->this_id = ARCMSR_SCSI_INITIATOR_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) host->unique_id = (bus << 8) | dev_fun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pci_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) error = pci_request_regions(pdev, "arcmsr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if(error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto scsi_host_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) spin_lock_init(&acb->eh_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) spin_lock_init(&acb->ccblist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) spin_lock_init(&acb->postq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) spin_lock_init(&acb->doneq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) spin_lock_init(&acb->rqbuffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_lock_init(&acb->wqbuffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ACB_F_MESSAGE_RQBUFFER_CLEARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ACB_F_MESSAGE_WQBUFFER_READED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) INIT_LIST_HEAD(&acb->ccb_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) error = arcmsr_remap_pciregion(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if(!error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto pci_release_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) error = arcmsr_alloc_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto unmap_pci_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) error = arcmsr_get_firmware_spec(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if(!error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto free_hbb_mu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) arcmsr_free_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) error = arcmsr_alloc_ccb_pool(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if(error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto unmap_pci_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) error = scsi_add_host(host, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if(error){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto free_ccb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (arcmsr_request_irq(pdev, acb) == FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) goto scsi_host_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) arcmsr_iop_init(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) arcmsr_init_get_devmap_timer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) arcmsr_init_set_datetime_timer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if(arcmsr_alloc_sysfs_attr(acb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) goto out_free_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) scsi_scan_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) out_free_sysfs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) del_timer_sync(&acb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) del_timer_sync(&acb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) flush_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) arcmsr_free_irq(pdev, acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) scsi_host_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) scsi_remove_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) free_ccb_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) arcmsr_free_ccb_pool(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) goto unmap_pci_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) free_hbb_mu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) arcmsr_free_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) unmap_pci_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) arcmsr_unmap_pciregion(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pci_release_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) scsi_host_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) pci_disable_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static void arcmsr_free_irq(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) for (i = 0; i < acb->vector_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) free_irq(pci_irq_vector(pdev, i), acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct Scsi_Host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) (struct AdapterControlBlock *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) arcmsr_free_irq(pdev, acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) del_timer_sync(&acb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) del_timer_sync(&acb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) flush_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pci_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pci_set_power_state(pdev, pci_choose_state(pdev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int arcmsr_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct Scsi_Host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) (struct AdapterControlBlock *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pci_enable_wake(pdev, PCI_D0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pr_warn("%s: pci_enable_device error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (arcmsr_set_dma_mask(acb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) goto controller_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (arcmsr_request_irq(pdev, acb) == FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto controller_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) reg->post_qbuffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) reg->done_qbuffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) reg->postq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) reg->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel(0, &acb->pmuE->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) acb->in_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) acb->out_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) acb->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) writel(0, &acb->pmuF->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) acb->in_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) acb->out_doorbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) acb->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) arcmsr_hbaF_assign_regAddr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) arcmsr_iop_init(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) arcmsr_init_get_devmap_timer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) arcmsr_init_set_datetime_timer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) controller_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) controller_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) scsi_remove_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) arcmsr_free_ccb_pool(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) arcmsr_free_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) arcmsr_unmap_pciregion(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "arcmsr%d: wait 'abort all outstanding command' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) , acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "arcmsr%d: wait 'abort all outstanding command' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) , acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct MessageUnit_C __iomem *reg = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "arcmsr%d: wait 'abort all outstanding command' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) , pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct MessageUnit_D *reg = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) pr_notice("arcmsr%d: wait 'abort all outstanding "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "command' timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct MessageUnit_E __iomem *reg = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) writel(pACB->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) pr_notice("arcmsr%d: wait 'abort all outstanding "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) "command' timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) uint8_t rtnval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) rtnval = arcmsr_hbaA_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) rtnval = arcmsr_hbaB_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) rtnval = arcmsr_hbaC_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) rtnval = arcmsr_hbaD_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) rtnval = arcmsr_hbaE_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return rtnval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct scsi_cmnd *pcmd = ccb->pcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) scsi_dma_unmap(pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct AdapterControlBlock *acb = ccb->acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct scsi_cmnd *pcmd = ccb->pcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) atomic_dec(&acb->ccboutstandingcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) arcmsr_pci_unmap_dma(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ccb->startdone = ARCMSR_CCB_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) spin_lock_irqsave(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) list_add_tail(&ccb->list, &acb->ccb_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) spin_unlock_irqrestore(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pcmd->scsi_done(pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct scsi_cmnd *pcmd = ccb->pcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (sensebuffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int sense_data_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) sensebuffer->Valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) pcmd->result |= (DRIVER_SENSE << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u32 orig_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) case ACB_ADAPTER_TYPE_A : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) orig_mask = readl(®->outbound_intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ®->outbound_intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case ACB_ADAPTER_TYPE_B : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) orig_mask = readl(reg->iop2drv_doorbell_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) writel(0, reg->iop2drv_doorbell_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) case ACB_ADAPTER_TYPE_C:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) orig_mask = readl(®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) readl(®->host_int_mask); /* Dummy readl to force pci flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return orig_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct CommandControlBlock *ccb, bool error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) uint8_t id, lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) id = ccb->pcmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) lun = ccb->pcmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (acb->devstate[id][lun] == ARECA_RAID_GONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) acb->devstate[id][lun] = ARECA_RAID_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ccb->pcmd->result = DID_OK << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) switch (ccb->arcmsr_cdb.DeviceStatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case ARCMSR_DEV_SELECT_TIMEOUT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) acb->devstate[id][lun] = ARECA_RAID_GONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ccb->pcmd->result = DID_NO_CONNECT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case ARCMSR_DEV_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case ARCMSR_DEV_INIT_FAIL: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) acb->devstate[id][lun] = ARECA_RAID_GONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ccb->pcmd->result = DID_BAD_TARGET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case ARCMSR_DEV_CHECK_CONDITION: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) acb->devstate[id][lun] = ARECA_RAID_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) arcmsr_report_sense_info(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) but got unknown DeviceStatus = 0x%x \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) , id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) , lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) , ccb->arcmsr_cdb.DeviceStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) acb->devstate[id][lun] = ARECA_RAID_GONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ccb->pcmd->result = DID_NO_CONNECT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct scsi_cmnd *abortcmd = pCCB->pcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (abortcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) abortcmd->result |= DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) arcmsr_ccb_complete(pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) acb->host->host_no, pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) done acb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) " ccboutstandingcount = %d \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) , acb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) , pCCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) , pCCB->acb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) , pCCB->startdone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) arcmsr_report_ccb_state(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) uint32_t flag_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct ARCMSR_CDB *pARCMSR_CDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned long ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) uint32_t outbound_intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) outbound_intstatus = readl(®->outbound_intstatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /*clear and abort all outbound posted Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) && (i++ < acb->maxOutstanding)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*clear all outbound posted Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) flag_ccb = reg->done_qbuffer[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (flag_ccb != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) reg->done_qbuffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) reg->post_qbuffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) reg->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) reg->postq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /*need to do*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) flag_ccb = readl(®->outbound_queueport_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct MessageUnit_D *pmu = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) uint32_t outbound_write_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) residual = atomic_read(&acb->ccboutstandingcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) for (i = 0; i < residual; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) outbound_write_pointer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pmu->done_qbuffer[0].addressLow + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if ((doneq_index & 0xFFF) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) (outbound_write_pointer & 0xFFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) toggle = doneq_index & 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) index_stripped = (doneq_index & 0xFFF) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ((toggle ^ 0x4000) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) addressLow = pmu->done_qbuffer[doneq_index &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) 0xFFF].addressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) pARCMSR_CDB = (struct ARCMSR_CDB *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) (acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) pCCB = container_of(pARCMSR_CDB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) error = (addressLow &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) writel(doneq_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) pmu->outboundlist_read_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pmu->postq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) pmu->doneq_index = 0x40FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) arcmsr_hbaE_postqueue_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) arcmsr_hbaF_postqueue_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) char *acb_dev_map = (char *)acb->device_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) int target, lun, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct scsi_device *psdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) for (i = 0; i < acb->maxFreeCCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ccb = acb->pccb_pool[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (ccb->startdone == ARCMSR_CCB_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ccb->pcmd->result = DID_NO_CONNECT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) arcmsr_pci_unmap_dma(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ccb->pcmd->scsi_done(ccb->pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) temp = *acb_dev_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (temp & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) psdev = scsi_device_lookup(acb->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) 0, target, lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (psdev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) scsi_remove_device(psdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) scsi_device_put(psdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) temp >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) *acb_dev_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) acb_dev_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) host = acb->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) arcmsr_free_sysfs_attr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) scsi_remove_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) flush_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) del_timer_sync(&acb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) del_timer_sync(&acb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) pdev = acb->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) arcmsr_free_irq(pdev, acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) arcmsr_free_ccb_pool(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) arcmsr_free_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) arcmsr_unmap_pciregion(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static void arcmsr_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct Scsi_Host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) (struct AdapterControlBlock *) host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) uint16_t dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (dev_id == 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) acb->acb_flags &= ~ACB_F_IOP_INITED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) arcmsr_remove_scsi_devices(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) arcmsr_free_pcidev(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) arcmsr_free_sysfs_attr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) scsi_remove_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) flush_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) del_timer_sync(&acb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) del_timer_sync(&acb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) acb->acb_flags &= ~ACB_F_IOP_INITED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (!atomic_read(&acb->ccboutstandingcount))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) arcmsr_interrupt(acb);/* FIXME: need spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (atomic_read(&acb->ccboutstandingcount)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) arcmsr_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) arcmsr_done4abort_postqueue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) for (i = 0; i < acb->maxFreeCCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct CommandControlBlock *ccb = acb->pccb_pool[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (ccb->startdone == ARCMSR_CCB_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ccb->startdone = ARCMSR_CCB_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ccb->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) arcmsr_free_irq(pdev, acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) arcmsr_free_ccb_pool(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) arcmsr_free_io_queue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) arcmsr_unmap_pciregion(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static void arcmsr_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct Scsi_Host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) (struct AdapterControlBlock *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) del_timer_sync(&acb->eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (set_date_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) del_timer_sync(&acb->refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) arcmsr_free_irq(pdev, acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) flush_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static int arcmsr_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) error = pci_register_driver(&arcmsr_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static void arcmsr_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) pci_unregister_driver(&arcmsr_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) module_init(arcmsr_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) module_exit(arcmsr_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) u32 intmask_org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) writel(mask, ®->outbound_intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ARCMSR_IOP2DRV_DATA_READ_OK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ARCMSR_IOP2DRV_CDB_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) writel(mask, reg->iop2drv_doorbell_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) writel(intmask_org & mask, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) writel(intmask_org | mask, reg->pcief0_int_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) writel(intmask_org & mask, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int8_t *psge = (int8_t *)&arcmsr_cdb->u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) __le32 address_lo, address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) int arccdbsize = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) __le32 length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) int nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ccb->pcmd = pcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) arcmsr_cdb->TargetID = pcmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) arcmsr_cdb->LUN = pcmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) arcmsr_cdb->Function = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) arcmsr_cdb->msgContext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) nseg = scsi_dma_map(pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) scsi_for_each_sg(pcmd, sg, nseg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* Get the physical address of the current data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) length = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (address_hi == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pdma_sg->address = address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) pdma_sg->length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) psge += sizeof (struct SG32ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) arccdbsize += sizeof (struct SG32ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) pdma_sg->addresshigh = address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) pdma_sg->address = address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) psge += sizeof (struct SG64ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) arccdbsize += sizeof (struct SG64ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) arcmsr_cdb->sgcount = (uint8_t)nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if ( arccdbsize > 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (pcmd->sc_data_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ccb->arc_cdb_size = arccdbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) atomic_inc(&acb->ccboutstandingcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ccb->startdone = ARCMSR_CCB_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ®->inbound_queueport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) writel(cdb_phyaddr, ®->inbound_queueport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) uint32_t ending_index, index = reg->postq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) reg->post_qbuffer[ending_index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) reg->post_qbuffer[index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) reg->post_qbuffer[index] = cdb_phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) reg->postq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) uint32_t ccb_post_stamp, arc_cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) struct MessageUnit_D *pmu = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) u16 index_stripped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) u16 postq_index, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct InBound_SRB *pinbound_srb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) spin_lock_irqsave(&acb->postq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) postq_index = pmu->postq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) pinbound_srb->addressLow = cdb_phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) pinbound_srb->length = ccb->arc_cdb_size >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) toggle = postq_index & 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) index_stripped = postq_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) pmu->postq_index = index_stripped ? (index_stripped | toggle) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) (toggle ^ 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) writel(postq_index, pmu->inboundlist_write_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) spin_unlock_irqrestore(&acb->postq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct MessageUnit_E __iomem *pmu = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) u32 ccb_post_stamp, arc_cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) writel(0, &pmu->inbound_queueport_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) writel(ccb_post_stamp, &pmu->inbound_queueport_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) struct MessageUnit_F __iomem *pmu = acb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) u32 ccb_post_stamp, arc_cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (ccb->arc_cdb_size <= 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) arc_cdb_size = (ccb->arc_cdb_size - 1) >> 6 | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) arc_cdb_size = ((ccb->arc_cdb_size + 0xff) >> 8) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (arc_cdb_size > 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) arc_cdb_size = 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) arc_cdb_size = (arc_cdb_size << 1) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ccb_post_stamp = (ccb->smid | arc_cdb_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) writel(0, &pmu->inbound_queueport_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) writel(ccb_post_stamp, &pmu->inbound_queueport_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) , acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) , acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) struct MessageUnit_C __iomem *reg = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) , pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct MessageUnit_D *reg = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (!arcmsr_hbaD_wait_msgint_ready(pACB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) "timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct MessageUnit_E __iomem *reg = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) writel(pACB->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) "timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) arcmsr_hbaA_stop_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) arcmsr_hbaB_stop_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) arcmsr_hbaC_stop_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) arcmsr_hbaD_stop_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) arcmsr_hbaE_stop_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) reg->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ** push inbound doorbell tell iop, driver data write ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ** and wait reply on next hwinterrupt for next Qbuffer post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ** push inbound doorbell tell iop, driver data write ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ** and wait reply on next hwinterrupt for next Qbuffer post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ** push inbound doorbell tell iop, driver data write ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ** and wait reply on next hwinterrupt for next Qbuffer post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) reg->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) struct QBUFFER __iomem *qbuffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) qbuffer = (struct QBUFFER __iomem *)acb->message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return qbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) struct QBUFFER __iomem *pqbuffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) pqbuffer = (struct QBUFFER __iomem *)acb->message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) return pqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct QBUFFER __iomem *prbuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) uint8_t *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) uint8_t *buf1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) uint32_t __iomem *iop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) uint32_t iop_len, data_len, *buf2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) iop_data = (uint32_t __iomem *)prbuffer->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) iop_len = readl(&prbuffer->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (iop_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) buf1 = kmalloc(128, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) buf2 = (uint32_t *)buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (buf1 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) data_len = iop_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) while (data_len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) *buf2++ = readl(iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) iop_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) data_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) *buf2 = readl(iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) buf2 = (uint32_t *)buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) while (iop_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) *pQbuffer = *buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) acb->rqbuf_putIndex++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) /* if last, index number set it to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) buf1++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) iop_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) kfree(buf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /* let IOP know data has been read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) arcmsr_iop_message_read(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct QBUFFER __iomem *prbuffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) uint8_t *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) uint8_t __iomem *iop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) uint32_t iop_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) iop_data = (uint8_t __iomem *)prbuffer->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) iop_len = readl(&prbuffer->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) while (iop_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) *pQbuffer = readb(iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) acb->rqbuf_putIndex++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) iop_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) iop_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) arcmsr_iop_message_read(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct QBUFFER __iomem *prbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) int32_t buf_empty_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) spin_lock_irqsave(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) prbuffer = arcmsr_get_iop_rqbuffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) (ARCMSR_MAX_QBUFFER - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (buf_empty_len >= readl(&prbuffer->data_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) uint8_t *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct QBUFFER __iomem *pwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) uint8_t *buf1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) uint32_t __iomem *iop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) buf1 = kmalloc(128, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) buf2 = (uint32_t *)buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (buf1 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) pwbuffer = arcmsr_get_iop_wqbuffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) iop_data = (uint32_t __iomem *)pwbuffer->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) && (allxfer_len < 124)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) *buf1 = *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) acb->wqbuf_getIndex++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) buf1++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) allxfer_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) data_len = allxfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) buf1 = (uint8_t *)buf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) while (data_len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) data = *buf2++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) writel(data, iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) iop_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) data_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (data_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) data = *buf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) writel(data, iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) writel(allxfer_len, &pwbuffer->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) kfree(buf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) arcmsr_iop_message_wrote(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) uint8_t *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) struct QBUFFER __iomem *pwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) uint8_t __iomem *iop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) int32_t allxfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) arcmsr_write_ioctldata2iop_in_DWORD(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pwbuffer = arcmsr_get_iop_wqbuffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) iop_data = (uint8_t __iomem *)pwbuffer->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) && (allxfer_len < 124)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) writeb(*pQbuffer, iop_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) acb->wqbuf_getIndex++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) iop_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) allxfer_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) writel(allxfer_len, &pwbuffer->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) arcmsr_iop_message_wrote(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) spin_lock_irqsave(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) arcmsr_write_ioctldata2iop(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) uint32_t outbound_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) writel(outbound_doorbell, ®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) arcmsr_iop2drv_data_wrote_handle(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) arcmsr_iop2drv_data_read_handle(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) uint32_t outbound_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) struct MessageUnit_C __iomem *reg = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) *******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ** Maybe here we need to check wrqbuffer_lock is lock or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) ** DOORBELL: din! don!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ** check if there are any mail need to pack from firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) *******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) writel(outbound_doorbell, ®->outbound_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) readl(®->outbound_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) arcmsr_iop2drv_data_wrote_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) arcmsr_iop2drv_data_read_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) arcmsr_hbaC_message_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) uint32_t outbound_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct MessageUnit_D *pmu = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) outbound_doorbell = readl(pmu->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) writel(outbound_doorbell, pmu->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) arcmsr_hbaD_message_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) arcmsr_iop2drv_data_wrote_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) arcmsr_iop2drv_data_read_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) outbound_doorbell = readl(pmu->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) uint32_t outbound_doorbell, in_doorbell, tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) struct MessageUnit_E __iomem *reg = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (pACB->adapter_type == ACB_ADAPTER_TYPE_F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) in_doorbell = readl(®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (in_doorbell != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) in_doorbell = readl(®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) writel(0, ®->host_int_status); /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) arcmsr_iop2drv_data_wrote_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) arcmsr_iop2drv_data_read_handle(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) arcmsr_hbaE_message_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) tmp = in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) in_doorbell = readl(®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) outbound_doorbell = tmp ^ in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) pACB->in_doorbell = in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) uint32_t flag_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) struct ARCMSR_CDB *pARCMSR_CDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) unsigned long cdb_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) uint32_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) uint32_t flag_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) struct ARCMSR_CDB *pARCMSR_CDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) unsigned long cdb_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) index = reg->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) arcmsr_drain_donequeue(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) reg->done_qbuffer[index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) index %= ARCMSR_MAX_HBB_POSTQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) reg->doneq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) struct MessageUnit_C __iomem *phbcmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) uint32_t flag_ccb, throttling = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) unsigned long ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) phbcmu = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* areca cdb command done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* Use correct offset and size for syncing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* check if command done with no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) arcmsr_drain_donequeue(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) throttling++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) &phbcmu->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) throttling = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) uint32_t addressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct MessageUnit_D *pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) unsigned long flags, ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) pmu = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) toggle = doneq_index & 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) index_stripped = (doneq_index & 0xFFF) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) ((toggle ^ 0x4000) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) addressLow = pmu->done_qbuffer[doneq_index &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) 0xFFF].addressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ccb = container_of(arcmsr_cdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) arcmsr_drain_donequeue(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) writel(doneq_index, pmu->outboundlist_read_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) } while ((doneq_index & 0xFFF) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) (outbound_write_pointer & 0xFFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) pmu->outboundlist_interrupt_cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) readl(pmu->outboundlist_interrupt_cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) uint32_t doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) uint16_t cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) struct MessageUnit_E __iomem *pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) doneq_index = acb->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) pmu = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ccb = acb->pccb_pool[cmdSMID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) error = (acb->pCompletionQ[doneq_index].cmdFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) arcmsr_drain_donequeue(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) doneq_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (doneq_index >= acb->completionQ_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) acb->doneq_index = doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) writel(doneq_index, &pmu->reply_post_consumer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) uint32_t doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) uint16_t cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct MessageUnit_F __iomem *phbcmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) doneq_index = acb->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) phbcmu = acb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (cmdSMID == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) ccb = acb->pccb_pool[cmdSMID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) error = (acb->pCompletionQ[doneq_index].cmdFlag &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) arcmsr_drain_donequeue(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) doneq_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (doneq_index >= acb->completionQ_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) acb->doneq_index = doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) writel(doneq_index, &phbcmu->reply_post_consumer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) ** Handle a message interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) ** The only message interrupt we expect is in response to a query for the current adapter config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /*clear interrupt and message state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) schedule_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /*clear interrupt and message state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) schedule_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) ** Handle a message interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) ** The only message interrupt we expect is in response to a query for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ** current adapter config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /*clear interrupt and message state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) schedule_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) readl(reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) schedule_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) writel(0, ®->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) schedule_work(&acb->arcmsr_do_message_isr_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) uint32_t outbound_intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) outbound_intstatus = readl(®->outbound_intstatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) writel(outbound_intstatus, ®->outbound_intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) arcmsr_hbaA_doorbell_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) arcmsr_hbaA_postqueue_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) arcmsr_hbaA_message_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) outbound_intstatus = readl(®->outbound_intstatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) uint32_t outbound_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) outbound_doorbell = readl(reg->iop2drv_doorbell) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) if (!outbound_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) writel(~outbound_doorbell, reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) arcmsr_iop2drv_data_wrote_handle(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) arcmsr_iop2drv_data_read_handle(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) arcmsr_hbaB_postqueue_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) arcmsr_hbaB_message_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) outbound_doorbell = readl(reg->iop2drv_doorbell) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) | ARCMSR_IOP2DRV_DATA_READ_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) | ARCMSR_IOP2DRV_CDB_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) uint32_t host_interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) *********************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ** check outbound intstatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) *********************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) host_interrupt_status = readl(&phbcmu->host_int_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if (!host_interrupt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) arcmsr_hbaC_doorbell_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) /* MU post queue interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) arcmsr_hbaC_postqueue_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) host_interrupt_status = readl(&phbcmu->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) u32 host_interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) struct MessageUnit_D *pmu = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) host_interrupt_status = readl(pmu->host_int_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) if (!host_interrupt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) /* MU post queue interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (host_interrupt_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) arcmsr_hbaD_postqueue_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) if (host_interrupt_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) arcmsr_hbaD_doorbell_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) host_interrupt_status = readl(pmu->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) } while (host_interrupt_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) uint32_t host_interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) struct MessageUnit_E __iomem *pmu = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) host_interrupt_status = readl(&pmu->host_int_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) if (!host_interrupt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* MU ioctl transfer doorbell interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) arcmsr_hbaE_doorbell_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) /* MU post queue interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) arcmsr_hbaE_postqueue_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) host_interrupt_status = readl(&pmu->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static irqreturn_t arcmsr_hbaF_handle_isr(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) uint32_t host_interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) struct MessageUnit_F __iomem *phbcmu = pACB->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) host_interrupt_status = readl(&phbcmu->host_int_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (!host_interrupt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* MU post queue interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) arcmsr_hbaF_postqueue_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) /* MU ioctl transfer doorbell interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) arcmsr_hbaE_doorbell_isr(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) host_interrupt_status = readl(&phbcmu->host_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) return arcmsr_hbaA_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) return arcmsr_hbaB_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) return arcmsr_hbaC_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) return arcmsr_hbaD_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) return arcmsr_hbaE_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) return arcmsr_hbaF_handle_isr(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) if (acb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) /* stop adapter background rebuild */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) intmask_org = arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) arcmsr_stop_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) arcmsr_enable_outbound_ints(acb, intmask_org);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) for (i = 0; i < 15; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) acb->rqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) acb->rqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) arcmsr_iop_message_read(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) mdelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) } else if (acb->rqbuf_getIndex !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) acb->rqbuf_putIndex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) acb->rqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) acb->rqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) mdelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) char *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) unsigned short use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) int retvalue = 0, transfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) struct CMD_MESSAGE_FIELD *pcmdmessagefld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) (uint32_t)cmd->cmnd[6] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) (uint32_t)cmd->cmnd[7] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) (uint32_t)cmd->cmnd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) use_sg = scsi_sg_count(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) sg = scsi_sglist(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) buffer = kmap_atomic(sg_page(sg)) + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) if (use_sg > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) goto message_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) transfer_len += sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) goto message_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) switch (controlcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) case ARCMSR_MESSAGE_READ_RQBUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) unsigned char *ver_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) uint8_t *ptmpQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) uint32_t allxfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (!ver_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) pr_info("%s: memory not enough!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) goto message_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) ptmpQbuffer = ver_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) spin_lock_irqsave(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) unsigned int tail = acb->rqbuf_getIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) unsigned int head = acb->rqbuf_putIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) allxfer_len = ARCMSR_API_DATA_BUFLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (allxfer_len <= cnt_to_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) allxfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) struct QBUFFER __iomem *prbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) prbuffer = arcmsr_get_iop_rqbuffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) kfree(ver_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) pcmdmessagefld->cmdmessage.Length = allxfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) unsigned char *ver_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) uint32_t user_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) int32_t cnt2end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) uint8_t *pQbuffer, *ptmpuserbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) user_len = pcmdmessagefld->cmdmessage.Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) if (user_len > ARCMSR_API_DATA_BUFLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) goto message_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) if (!ver_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) goto message_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) ptmpuserbuffer = ver_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) memcpy(ptmpuserbuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) pcmdmessagefld->messagedatabuffer, user_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) spin_lock_irqsave(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) struct SENSE_DATA *sensebuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) (struct SENSE_DATA *)cmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) arcmsr_write_ioctldata2iop(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) /* has error report sensedata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) sensebuffer->SenseKey = ILLEGAL_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) sensebuffer->AdditionalSenseLength = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) sensebuffer->AdditionalSenseCode = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) sensebuffer->Valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) if (user_len > cnt2end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) ptmpuserbuffer += cnt2end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) user_len -= cnt2end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) acb->wqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) pQbuffer = acb->wqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) memcpy(pQbuffer, ptmpuserbuffer, user_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) acb->wqbuf_putIndex += user_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) acb->acb_flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) arcmsr_write_ioctldata2iop(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) kfree(ver_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) uint8_t *pQbuffer = acb->rqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) arcmsr_clear_iop2drv_rqueue_buffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) spin_lock_irqsave(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) acb->rqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) acb->rqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) uint8_t *pQbuffer = acb->wqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) spin_lock_irqsave(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) ACB_F_MESSAGE_WQBUFFER_READED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) acb->wqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) acb->wqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) uint8_t *pQbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) arcmsr_clear_iop2drv_rqueue_buffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) spin_lock_irqsave(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) acb->rqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) acb->rqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) pQbuffer = acb->rqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) memset(pQbuffer, 0, sizeof(struct QBUFFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) spin_lock_irqsave(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) ACB_F_MESSAGE_WQBUFFER_READED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) acb->wqbuf_getIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) acb->wqbuf_putIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) pQbuffer = acb->wqbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) memset(pQbuffer, 0, sizeof(struct QBUFFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) case ARCMSR_MESSAGE_RETURN_CODE_3F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) ARCMSR_MESSAGE_RETURNCODE_3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) case ARCMSR_MESSAGE_SAY_HELLO: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) int8_t *hello_string = "Hello! I am ARCMSR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) memcpy(pcmdmessagefld->messagedatabuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) hello_string, (int16_t)strlen(hello_string));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) case ARCMSR_MESSAGE_SAY_GOODBYE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) arcmsr_iop_parking(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) if (acb->fw_flag == FW_DEADLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pcmdmessagefld->cmdmessage.ReturnCode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) ARCMSR_MESSAGE_RETURNCODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) arcmsr_flush_adapter_cache(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) retvalue = ARCMSR_MESSAGE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) pr_info("%s: unknown controlcode!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) message_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (use_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) struct scatterlist *sg = scsi_sglist(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) kunmap_atomic(buffer - sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) return retvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) struct list_head *head = &acb->ccb_free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct CommandControlBlock *ccb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) spin_lock_irqsave(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) if (!list_empty(head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) ccb = list_entry(head->next, struct CommandControlBlock, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) list_del_init(&ccb->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) }else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) spin_unlock_irqrestore(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) spin_unlock_irqrestore(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) return ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) switch (cmd->cmnd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) case INQUIRY: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) unsigned char inqdata[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) char *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) if (cmd->device->lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) cmd->result = (DID_TIME_OUT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) inqdata[0] = TYPE_PROCESSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) /* Periph Qualifier & Periph Dev Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) inqdata[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) /* rem media bit & Dev Type Modifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) inqdata[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) /* ISO, ECMA, & ANSI versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) inqdata[4] = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /* length of additional data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) strncpy(&inqdata[8], "Areca ", 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) /* Vendor Identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) strncpy(&inqdata[16], "RAID controller ", 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) /* Product Identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) strncpy(&inqdata[32], "R001", 4); /* Product Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) sg = scsi_sglist(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) buffer = kmap_atomic(sg_page(sg)) + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) memcpy(buffer, inqdata, sizeof(inqdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) sg = scsi_sglist(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) kunmap_atomic(buffer - sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) case WRITE_BUFFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) case READ_BUFFER: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (arcmsr_iop_message_xfer(acb, cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) cmd->result = (DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) void (* done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) struct Scsi_Host *host = cmd->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) int target = cmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) cmd->result = (DID_NO_CONNECT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) cmd->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) cmd->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (target == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) /* virtual device for iop message transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) arcmsr_handle_virtual_command(acb, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) ccb = arcmsr_get_freeccb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) if (!ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) arcmsr_post_ccb(acb, ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) static DEF_SCSI_QCMD(arcmsr_queue_command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) uint32_t *firm_model = &rwbuffer[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) uint32_t *firm_version = &rwbuffer[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) uint32_t *device_map = &rwbuffer[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) *acb_firm_model = readl(firm_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) acb_firm_model++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) firm_model++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) *acb_firm_version = readl(firm_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) acb_firm_version++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) firm_version++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) *acb_device_map = readl(device_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) acb_device_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) device_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) pACB->signature = readl(&rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) pACB->firm_request_len = readl(&rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) pACB->firm_numbers_queue = readl(&rwbuffer[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) pACB->firm_sdram_size = readl(&rwbuffer[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) pACB->firm_hd_channels = readl(&rwbuffer[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pACB->firm_cfg_version = readl(&rwbuffer[25]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) pACB->host->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) pACB->firm_model,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) pACB->firm_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) arcmsr_wait_firmware_ready(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) miscellaneous data' timeout \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) arcmsr_wait_firmware_ready(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) miscellaneous data' timeout \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) struct MessageUnit_C __iomem *reg = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) /* wait firmware ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) arcmsr_wait_firmware_ready(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* post "get config" instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* wait message ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) miscellaneous data' timeout \n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (readl(acb->pmuD->outbound_doorbell) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) acb->pmuD->outbound_doorbell);/*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) arcmsr_wait_firmware_ready(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) /* post "get config" instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) /* wait message ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) pr_notice("arcmsr%d: wait get adapter firmware "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) "miscellaneous data timeout\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) struct MessageUnit_E __iomem *reg = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) /* wait firmware ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) arcmsr_wait_firmware_ready(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) mdelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) /* post "get config" instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) writel(pACB->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) /* wait message ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) pr_notice("arcmsr%d: wait get adapter firmware "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) "miscellaneous data timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) static bool arcmsr_hbaF_get_config(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) struct MessageUnit_F __iomem *reg = pACB->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) /* wait firmware ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) arcmsr_wait_firmware_ready(pACB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) /* post "get config" instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) writel(pACB->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) /* wait message ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) pr_notice("arcmsr%d: wait get adapter firmware miscellaneous data timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) arcmsr_get_adapter_config(pACB, pACB->msgcode_rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) bool rtn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) rtn = arcmsr_hbaA_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) rtn = arcmsr_hbaB_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) rtn = arcmsr_hbaC_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) rtn = arcmsr_hbaD_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) rtn = arcmsr_hbaE_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) rtn = arcmsr_hbaF_get_config(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) acb->maxOutstanding = acb->firm_numbers_queue - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) if (acb->host->can_queue >= acb->firm_numbers_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) acb->host->can_queue = acb->maxOutstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) acb->maxOutstanding = acb->host->can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) acb->maxFreeCCB = acb->host->can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) acb->maxFreeCCB += 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) unsigned long ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) polling_hba_ccb_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) poll_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) if (poll_ccb_done){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) }else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) if (poll_count > 100){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) goto polling_hba_ccb_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) " poll command abort successfully \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) , ccb->pcmd->device->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) , (u32)ccb->pcmd->device->lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) , ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) ccb->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) " command done ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) "ccboutstandingcount = %d \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) , ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) arcmsr_report_ccb_state(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) int index, rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) unsigned long ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) polling_hbb_ccb_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) poll_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) /* clear doorbell interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) while(1){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) index = reg->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) flag_ccb = reg->done_qbuffer[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) if (flag_ccb == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) if (poll_ccb_done){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) }else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) if (poll_count > 100){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) goto polling_hbb_ccb_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) reg->done_qbuffer[index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) /*if last index number set it to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) index %= ARCMSR_MAX_HBB_POSTQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) reg->doneq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) /* check if command done with no error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) " poll command abort successfully \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) ,acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) ,ccb->pcmd->device->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) ,(u32)ccb->pcmd->device->lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) ,ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) ccb->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) arcmsr_ccb_complete(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) " command done ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) "ccboutstandingcount = %d \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) , ccb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) arcmsr_report_ccb_state(acb, ccb, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) uint32_t flag_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) uint32_t poll_ccb_done = 0, poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) unsigned long ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) polling_hbc_ccb_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) poll_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) if (poll_ccb_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) if (poll_count > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) goto polling_hbc_ccb_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) flag_ccb = readl(®->outbound_queueport_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) /* check ifcommand done with no error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) " poll command abort successfully \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) , pCCB->pcmd->device->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) , (u32)pCCB->pcmd->device->lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) , pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) pCCB->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) arcmsr_ccb_complete(pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) " command done ccb = '0x%p'"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) "ccboutstandingcount = %d \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) , pCCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) arcmsr_report_ccb_state(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) unsigned long flags, ccb_cdb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) struct ARCMSR_CDB *arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) struct MessageUnit_D *pmu = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) polling_hbaD_ccb_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) poll_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) if (poll_ccb_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) if (poll_count > 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) goto polling_hbaD_ccb_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) toggle = doneq_index & 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) index_stripped = (doneq_index & 0xFFF) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) ((toggle ^ 0x4000) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) doneq_index = pmu->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) if (acb->cdb_phyadd_hipart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) ccb_cdb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) if ((pCCB->acb != acb) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) (pCCB->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) pr_notice("arcmsr%d: scsi id = %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) "lun = %d ccb = '0x%p' poll command "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) "abort successfully\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) , pCCB->pcmd->device->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) , (u32)pCCB->pcmd->device->lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) , pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) pCCB->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) arcmsr_ccb_complete(pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) pr_notice("arcmsr%d: polling an illegal "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) "ccb command done ccb = '0x%p' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) "ccboutstandingcount = %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) , pCCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) arcmsr_report_ccb_state(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) uint16_t cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) struct CommandControlBlock *pCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) polling_hbaC_ccb_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) poll_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) spin_lock_irqsave(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) doneq_index = acb->doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) if ((readl(®->reply_post_producer_index) & 0xFFFF) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) doneq_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) if (poll_ccb_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) if (poll_count > 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) goto polling_hbaC_ccb_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) doneq_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) if (doneq_index >= acb->completionQ_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) acb->doneq_index = doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) spin_unlock_irqrestore(&acb->doneq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) pCCB = acb->pccb_pool[cmdSMID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) /* check if command done with no error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) pr_notice("arcmsr%d: scsi id = %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) "lun = %d ccb = '0x%p' poll command "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) "abort successfully\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) , pCCB->pcmd->device->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) , (u32)pCCB->pcmd->device->lun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) , pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) pCCB->pcmd->result = DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) arcmsr_ccb_complete(pCCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) pr_notice("arcmsr%d: polling an illegal "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) "ccb command done ccb = '0x%p' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) "ccboutstandingcount = %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) , acb->host->host_no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) , pCCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) , atomic_read(&acb->ccboutstandingcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) error = (acb->pCompletionQ[doneq_index].cmdFlag &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) arcmsr_report_ccb_state(acb, pCCB, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) writel(doneq_index, ®->reply_post_consumer_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) struct CommandControlBlock *poll_ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) int rtn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) static void arcmsr_set_iop_datetime(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) unsigned int next_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) struct tm tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) uint16_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) uint8_t year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) uint8_t month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) uint8_t date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) uint8_t hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) uint8_t minute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) uint8_t second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) } a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) uint32_t msg_time[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) } datetime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) datetime.a.signature = 0x55AA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) datetime.a.month = tm.tm_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) datetime.a.date = tm.tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) datetime.a.hour = tm.tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) datetime.a.minute = tm.tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) datetime.a.second = tm.tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) switch (pacb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) struct MessageUnit_A __iomem *reg = pacb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) uint32_t __iomem *rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) struct MessageUnit_B *reg = pacb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) rwbuffer = reg->message_rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) writel(datetime.b.msg_time[0], rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) writel(datetime.b.msg_time[1], rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) struct MessageUnit_C __iomem *reg = pacb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) uint32_t __iomem *rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) struct MessageUnit_D *reg = pacb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) rwbuffer = reg->msgcode_rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) writel(datetime.b.msg_time[0], rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) writel(datetime.b.msg_time[1], rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) struct MessageUnit_E __iomem *reg = pacb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) writel(pacb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) struct MessageUnit_F __iomem *reg = pacb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) pacb->msgcode_rwbuffer[0] = datetime.b.msg_time[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) pacb->msgcode_rwbuffer[1] = datetime.b.msg_time[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) writel(pacb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) if (sys_tz.tz_minuteswest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) next_time = ARCMSR_HOURS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) next_time = ARCMSR_MINUTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) dma_addr_t dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) ********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) ** here we need to tell iop 331 our freeccb.HighPart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) ** if freeccb.HighPart is not zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) ********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) dma_coherent_handle = acb->dma_coherent_handle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) dma_coherent_handle = acb->dma_coherent_handle +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) offsetof(struct CommandControlBlock, arcmsr_cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) dma_coherent_handle = acb->dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) cdb_phyaddr = lower_32_bits(dma_coherent_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) ***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) ** if adapter type B, set window of "post command Q"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) ***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) if (cdb_phyaddr_hi32 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) writel(ARCMSR_SIGNATURE_SET_CONFIG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) ®->message_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) part physical address timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) uint32_t __iomem *rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) reg->postq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) reg->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) rwbuffer = reg->message_rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) /* driver "set config" signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) /* normal should be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) writel(cdb_phyaddr_hi32, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) /* postQ size (256 + 8)*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) writel(cdb_phyaddr, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) /* doneQ size (256 + 8)*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) writel(cdb_phyaddr + 1056, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) /* ccb maxQ size must be --> [(256 + 8)*4]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) writel(1056, rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) timeout \n",acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) pr_err("arcmsr%d: can't set driver mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) acb->adapter_index, cdb_phyaddr_hi32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) timeout \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) uint32_t __iomem *rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) reg->postq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) reg->doneq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) rwbuffer = reg->msgcode_rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) writel(cdb_phyaddr_hi32, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) writel(cdb_phyaddr, rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) sizeof(struct InBound_SRB)), rwbuffer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) writel(0x100, rwbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) pr_notice("arcmsr%d: 'set command Q window' timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) writel(acb->ccbsize, ®->msgcode_rwbuffer[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) writel(lower_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) writel(upper_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) pr_notice("arcmsr%d: 'set command Q window' timeout \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) struct MessageUnit_F __iomem *reg = acb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) acb->msgcode_rwbuffer[2] = cdb_phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) acb->msgcode_rwbuffer[3] = cdb_phyaddr_hi32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) acb->msgcode_rwbuffer[4] = acb->ccbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) acb->msgcode_rwbuffer[5] = lower_32_bits(acb->dma_coherent_handle2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) acb->msgcode_rwbuffer[6] = upper_32_bits(acb->dma_coherent_handle2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) acb->msgcode_rwbuffer[7] = acb->completeQ_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) pr_notice("arcmsr%d: 'set command Q window' timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) uint32_t firmware_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) if (!(acb->acb_flags & ACB_F_IOP_INITED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) firmware_state = readl(®->outbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) if (!(acb->acb_flags & ACB_F_IOP_INITED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) firmware_state = readl(reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) if (!(acb->acb_flags & ACB_F_IOP_INITED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) firmware_state = readl(®->outbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) if (!(acb->acb_flags & ACB_F_IOP_INITED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) firmware_state = readl(reg->outbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) } while ((firmware_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) if (!(acb->acb_flags & ACB_F_IOP_INITED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) firmware_state = readl(®->outbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) static void arcmsr_request_device_map(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) if (acb->acb_flags & (ACB_F_MSG_GET_CONFIG | ACB_F_BUS_RESET | ACB_F_ABORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) acb->fw_flag = FW_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) case ACB_ADAPTER_TYPE_E: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) struct MessageUnit_F __iomem *reg = acb->pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) uint32_t outMsg1 = readl(®->outbound_msgaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) goto nxt6s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) nxt6s:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) acb->acb_flags |= ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) rebuild' timeout \n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) acb->acb_flags |= ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) rebuild' timeout \n",acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) pACB->acb_flags |= ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) rebuild' timeout \n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) struct MessageUnit_D *pmu = pACB->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) pACB->acb_flags |= ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) pr_notice("arcmsr%d: wait 'start adapter "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) "background rebuild' timeout\n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) struct MessageUnit_E __iomem *pmu = pACB->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) pACB->acb_flags |= ACB_F_MSG_START_BGRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) writel(pACB->out_doorbell, &pmu->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) pr_notice("arcmsr%d: wait 'start adapter "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) "background rebuild' timeout \n", pACB->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) arcmsr_hbaA_start_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) arcmsr_hbaB_start_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) arcmsr_hbaC_start_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) case ACB_ADAPTER_TYPE_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) arcmsr_hbaD_start_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) case ACB_ADAPTER_TYPE_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) arcmsr_hbaE_start_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) case ACB_ADAPTER_TYPE_A: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) uint32_t outbound_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) /* empty doorbell Qbuffer if door bell ringed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) /*clear doorbell interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) writel(outbound_doorbell, ®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) case ACB_ADAPTER_TYPE_B: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) uint32_t outbound_doorbell, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) /* let IOP know data has been read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) for(i=0; i < 200; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) outbound_doorbell = readl(reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) case ACB_ADAPTER_TYPE_C: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) uint32_t outbound_doorbell, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) /* empty doorbell Qbuffer if door bell ringed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) writel(outbound_doorbell, ®->outbound_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) for (i = 0; i < 200; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) outbound_doorbell = readl(®->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) if (outbound_doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) writel(outbound_doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) ®->outbound_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) ®->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) case ACB_ADAPTER_TYPE_D: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) uint32_t outbound_doorbell, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) /* empty doorbell Qbuffer if door bell ringed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) outbound_doorbell = readl(reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) writel(outbound_doorbell, reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) reg->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) for (i = 0; i < 200; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) outbound_doorbell = readl(reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) if (outbound_doorbell &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) writel(outbound_doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) reg->outbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) reg->inbound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) case ACB_ADAPTER_TYPE_F: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) uint32_t i, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) acb->in_doorbell = readl(®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) writel(0, ®->host_int_status); /*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) for(i=0; i < 200; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) tmp = acb->in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) acb->in_doorbell = readl(®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) writel(0, ®->host_int_status); /*clear interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) writel(acb->out_doorbell, ®->iobound_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) switch (acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) case ACB_ADAPTER_TYPE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) case ACB_ADAPTER_TYPE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) case ACB_ADAPTER_TYPE_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) uint8_t value[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) struct MessageUnit_A __iomem *pmuA = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) struct MessageUnit_C __iomem *pmuC = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) struct MessageUnit_D *pmuD = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) /* backup pci config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) for (i = 0; i < 64; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) pci_read_config_byte(acb->pdev, i, &value[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) /* hardware reset signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) if (acb->dev_id == 0x1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) } else if (acb->dev_id == 0x1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) writel(0xF, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) writel(0x4, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) writel(0xB, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) writel(0x2, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) writel(0x7, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) writel(0xD, &pmuC->write_sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) } else if (acb->dev_id == 0x1884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) struct MessageUnit_E __iomem *pmuE = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) writel(0x4, &pmuE->write_sequence_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) writel(0xB, &pmuE->write_sequence_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) writel(0x2, &pmuE->write_sequence_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) writel(0x7, &pmuE->write_sequence_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) writel(0xD, &pmuE->write_sequence_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) } while (((readl(&pmuE->host_diagnostic_3xxx) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) } else if (acb->dev_id == 0x1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) writel(0x20, pmuD->reset_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) pci_write_config_byte(acb->pdev, 0x84, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) msleep(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) /* write back pci config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) for (i = 0; i < 64; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) pci_write_config_byte(acb->pdev, i, value[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) bool rtn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) switch(acb->adapter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) case ACB_ADAPTER_TYPE_A:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) struct MessageUnit_A __iomem *reg = acb->pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) rtn = ((readl(®->outbound_msgaddr1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) case ACB_ADAPTER_TYPE_B:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) struct MessageUnit_B *reg = acb->pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) rtn = ((readl(reg->iop2drv_doorbell) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) case ACB_ADAPTER_TYPE_C:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) struct MessageUnit_C __iomem *reg = acb->pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) rtn = (readl(®->host_diagnostic) & 0x04) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) case ACB_ADAPTER_TYPE_D:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) struct MessageUnit_D *reg = acb->pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) case ACB_ADAPTER_TYPE_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) case ACB_ADAPTER_TYPE_F:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) struct MessageUnit_E __iomem *reg = acb->pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) rtn = (readl(®->host_diagnostic_3xxx) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) static void arcmsr_iop_init(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) intmask_org = arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) arcmsr_wait_firmware_ready(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) arcmsr_iop_confirm(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) /*start background rebuild*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) arcmsr_start_adapter_bgrb(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) /* empty doorbell Qbuffer if door bell ringed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) arcmsr_clear_doorbell_queue_buffer(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) arcmsr_enable_eoi_mode(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) /* enable outbound Post Queue,outbound doorbell Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) arcmsr_enable_outbound_ints(acb, intmask_org);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) acb->acb_flags |= ACB_F_IOP_INITED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) struct CommandControlBlock *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) uint8_t rtnval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) if (atomic_read(&acb->ccboutstandingcount) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) /* disable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) intmask_org = arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) /* talk to iop 331 outstanding command aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) rtnval = arcmsr_abort_allcmd(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) /* clear all outbound posted Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) arcmsr_done4abort_postqueue(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) for (i = 0; i < acb->maxFreeCCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) ccb = acb->pccb_pool[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) if (ccb->startdone == ARCMSR_CCB_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) scsi_dma_unmap(ccb->pcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) ccb->startdone = ARCMSR_CCB_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) ccb->ccb_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) spin_lock_irqsave(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) list_add_tail(&ccb->list, &acb->ccb_free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) spin_unlock_irqrestore(&acb->ccblist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) atomic_set(&acb->ccboutstandingcount, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) /* enable all outbound interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) arcmsr_enable_outbound_ints(acb, intmask_org);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) return rtnval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) return rtnval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) struct AdapterControlBlock *acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) int retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) int rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) acb->num_resets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) if (acb->acb_flags & ACB_F_BUS_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) timeout = wait_event_timeout(wait_q, (acb->acb_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) & ACB_F_BUS_RESET) == 0, 220 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) if (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) acb->acb_flags |= ACB_F_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) if (!arcmsr_iop_reset(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) arcmsr_hardware_reset(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) acb->acb_flags &= ~ACB_F_IOP_INITED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) wait_reset_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) ssleep(ARCMSR_SLEEPTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) if (arcmsr_reset_in_progress(acb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) if (retry_count > ARCMSR_RETRYCOUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) acb->fw_flag = FW_DEADLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) pr_notice("arcmsr%d: waiting for hw bus reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) " return, RETRY TERMINATED!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) acb->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) retry_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) goto wait_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) arcmsr_iop_init(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) acb->fw_flag = FW_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) mod_timer(&acb->eternal_timer, jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) msecs_to_jiffies(6 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) acb->acb_flags &= ~ACB_F_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) pr_notice("arcmsr: scsi bus reset eh returns with success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) acb->acb_flags &= ~ACB_F_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) acb->fw_flag = FW_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) mod_timer(&acb->eternal_timer, jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) msecs_to_jiffies(6 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) rtn = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) struct CommandControlBlock *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) rtn = arcmsr_polling_ccbdone(acb, ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) static int arcmsr_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) (struct AdapterControlBlock *)cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) int rtn = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) uint32_t intmask_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) printk(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) acb->acb_flags |= ACB_F_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) acb->num_aborts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) ************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) ** the all interrupt service routine is locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) ** we need to handle it as soon as possible and exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) ************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) if (!atomic_read(&acb->ccboutstandingcount)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) acb->acb_flags &= ~ACB_F_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) intmask_org = arcmsr_disable_outbound_ints(acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) for (i = 0; i < acb->maxFreeCCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) struct CommandControlBlock *ccb = acb->pccb_pool[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) ccb->startdone = ARCMSR_CCB_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) rtn = arcmsr_abort_one_cmd(acb, ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) acb->acb_flags &= ~ACB_F_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) arcmsr_enable_outbound_ints(acb, intmask_org);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) static const char *arcmsr_info(struct Scsi_Host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) struct AdapterControlBlock *acb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) (struct AdapterControlBlock *) host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) static char buf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) char *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) int raid6 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) switch (acb->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) case PCI_DEVICE_ID_ARECA_1110:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) case PCI_DEVICE_ID_ARECA_1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) case PCI_DEVICE_ID_ARECA_1202:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) case PCI_DEVICE_ID_ARECA_1210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) raid6 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) case PCI_DEVICE_ID_ARECA_1120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) case PCI_DEVICE_ID_ARECA_1130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) case PCI_DEVICE_ID_ARECA_1160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) case PCI_DEVICE_ID_ARECA_1170:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) case PCI_DEVICE_ID_ARECA_1201:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) case PCI_DEVICE_ID_ARECA_1203:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) case PCI_DEVICE_ID_ARECA_1220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) case PCI_DEVICE_ID_ARECA_1230:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) case PCI_DEVICE_ID_ARECA_1260:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) case PCI_DEVICE_ID_ARECA_1270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) case PCI_DEVICE_ID_ARECA_1280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) type = "SATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) case PCI_DEVICE_ID_ARECA_1214:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) case PCI_DEVICE_ID_ARECA_1380:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) case PCI_DEVICE_ID_ARECA_1381:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) case PCI_DEVICE_ID_ARECA_1680:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) case PCI_DEVICE_ID_ARECA_1681:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) case PCI_DEVICE_ID_ARECA_1880:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) case PCI_DEVICE_ID_ARECA_1884:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) type = "SAS/SATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) case PCI_DEVICE_ID_ARECA_1886:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) type = "NVMe/SAS/SATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) type = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) raid6 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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